Searched refs:max_dppclk_vmin0p65 (Results 1 – 2 of 2) sorted by relevance
80 .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */662 v->max_dispclk[0] = v->max_dppclk_vmin0p65; in hack_disable_optional_pipe_split()728 v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65; in dcn_validate_bandwidth()818 v->max_dppclk[0] = v->max_dppclk_vmin0p65; in dcn_validate_bandwidth()989 v->max_dppclk[0] = v->max_dppclk_vmin0p65; in dcn_validate_bandwidth()1065 (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000); in dcn_validate_bandwidth()1243 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) { in dcn_find_normalized_clock_vdd_Level()1508 dc->dcn_soc->max_dppclk_vmin0p65 * 1000, in dcn_bw_sync_calcs_and_dml()
126 float max_dppclk_vmin0p65; member563 float max_dppclk_vmin0p65; /*MHz*/ member
