Searched refs:max_cu_per_sh (Results 1 – 17 of 17) sorted by relevance
1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v6_0_get_cu_enabled()1567 adev->gfx.config.max_cu_per_sh = 8; in gfx_v6_0_gpu_init()1584 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_gpu_init()1601 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_gpu_init()1618 adev->gfx.config.max_cu_per_sh = 6; in gfx_v6_0_gpu_init()1635 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_gpu_init()3575 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v6_0_get_cu_info()3594 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v6_0_get_cu_info()
346 adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
425 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in get_cu_info()
3909 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()4334 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()4351 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()4368 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()4387 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()5199 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()5218 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v7_0_get_cu_info()
1795 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()1812 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()1859 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()1878 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()1895 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()1910 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()7363 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()7381 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()7398 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()
487 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
742 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; in amdgpu_atombios_get_gfx_info()
659 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in amdgpu_info_ioctl()
4866 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()4896 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()4898 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()
808 unsigned max_cu_per_sh; member
1431 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); in amdgpu_device_parse_gpu_info_fw()
426 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()428 *value = rdev->config.si.max_cu_per_sh; in radeon_info_ioctl()
3102 rdev->config.si.max_cu_per_sh = 8; in si_gpu_init()3119 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()3137 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()3154 rdev->config.si.max_cu_per_sh = 6; in si_gpu_init()3171 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()3294 rdev->config.si.max_cu_per_sh); in si_gpu_init()5310 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) { in si_get_cu_active_bitmap()5329 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { in si_init_ao_cu_mask()
3190 rdev->config.cik.max_cu_per_sh = 7; in cik_gpu_init()3207 rdev->config.cik.max_cu_per_sh = 11; in cik_gpu_init()3224 rdev->config.cik.max_cu_per_sh = 8; in cik_gpu_init()3243 rdev->config.cik.max_cu_per_sh = 2; in cik_gpu_init()6550 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) { in cik_get_cu_active_bitmap()6569 for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) { in cik_init_ao_cu_mask()
2135 unsigned max_cu_per_sh; member2166 unsigned max_cu_per_sh; member
1191 uint8_t max_cu_per_sh; member1211 uint8_t max_cu_per_sh; member
5652 UCHAR max_cu_per_sh; member
