Searched refs:max_backends_per_se (Results 1 – 17 of 17) sorted by relevance
907 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()945 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()959 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()973 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()980 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()1101 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1105 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1135 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()1147 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
357 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()360 *value = rdev->config.si.max_backends_per_se * in radeon_info_ioctl()363 *value = rdev->config.cayman.max_backends_per_se * in radeon_info_ioctl()
3104 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3121 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3139 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3156 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()3173 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()3290 rdev->config.si.max_backends_per_se); in si_gpu_init()
2098 unsigned max_backends_per_se; member2137 unsigned max_backends_per_se; member2168 unsigned max_backends_per_se; member
2339 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()3192 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3209 rdev->config.cik.max_backends_per_se = 4; in cik_gpu_init()3225 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3245 rdev->config.cik.max_backends_per_se = 1; in cik_gpu_init()3347 rdev->config.cik.max_backends_per_se); in cik_gpu_init()
1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()1569 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_gpu_init()1586 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_gpu_init()1603 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_gpu_init()1620 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_gpu_init()1637 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_gpu_init()
348 adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se; in amdgpu_atomfirmware_get_gfx_info()
1630 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()1792 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()1810 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()4336 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4353 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()4369 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4389 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
1797 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1814 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()1861 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1877 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1894 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()1912 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()3586 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()3748 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()3766 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
489 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
744 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; in amdgpu_atombios_get_gfx_info()
606 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
810 unsigned max_backends_per_se; member
1433 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
1702 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()1713 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
1193 uint8_t max_backends_per_se; member1213 uint8_t max_backends_per_se; member
5654 UCHAR max_backends_per_se; member
