1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 /* Macros to deal with bit fields. Each bit field must have 3 #defines 24 * associated with it (_SHIFT, _MASK, and _WORD). 25 * EG. For a bit field that is in the 7th bit of the "field4" field of a 26 * structure and is 2 bits in size the following #defines must exist: 27 * struct temp { 28 * uint32_t field1; 29 * uint32_t field2; 30 * uint32_t field3; 31 * uint32_t field4; 32 * #define example_bit_field_SHIFT 7 33 * #define example_bit_field_MASK 0x03 34 * #define example_bit_field_WORD field4 35 * uint32_t field5; 36 * }; 37 * Then the macros below may be used to get or set the value of that field. 38 * EG. To get the value of the bit field from the above example: 39 * struct temp t1; 40 * value = bf_get(example_bit_field, &t1); 41 * And then to set that bit field: 42 * bf_set(example_bit_field, &t1, 2); 43 * Or clear that bit field: 44 * bf_set(example_bit_field, &t1, 0); 45 */ 46 #define bf_get_be32(name, ptr) \ 47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get_le32(name, ptr) \ 49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get(name, ptr) \ 51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 52 #define bf_set_le32(name, ptr, value) \ 53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 55 ~(name##_MASK << name##_SHIFT))))) 56 #define bf_set(name, ptr, value) \ 57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 59 60 struct dma_address { 61 uint32_t addr_lo; 62 uint32_t addr_hi; 63 }; 64 65 struct lpfc_sli_intf { 66 uint32_t word0; 67 #define lpfc_sli_intf_valid_SHIFT 29 68 #define lpfc_sli_intf_valid_MASK 0x00000007 69 #define lpfc_sli_intf_valid_WORD word0 70 #define LPFC_SLI_INTF_VALID 6 71 #define lpfc_sli_intf_sli_hint2_SHIFT 24 72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 73 #define lpfc_sli_intf_sli_hint2_WORD word0 74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 75 #define lpfc_sli_intf_sli_hint1_SHIFT 16 76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 77 #define lpfc_sli_intf_sli_hint1_WORD word0 78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 79 #define LPFC_SLI_INTF_SLI_HINT1_1 1 80 #define LPFC_SLI_INTF_SLI_HINT1_2 2 81 #define lpfc_sli_intf_if_type_SHIFT 12 82 #define lpfc_sli_intf_if_type_MASK 0x0000000F 83 #define lpfc_sli_intf_if_type_WORD word0 84 #define LPFC_SLI_INTF_IF_TYPE_0 0 85 #define LPFC_SLI_INTF_IF_TYPE_1 1 86 #define LPFC_SLI_INTF_IF_TYPE_2 2 87 #define LPFC_SLI_INTF_IF_TYPE_6 6 88 #define lpfc_sli_intf_sli_family_SHIFT 8 89 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 90 #define lpfc_sli_intf_sli_family_WORD word0 91 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 92 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 95 #define lpfc_sli_intf_slirev_SHIFT 4 96 #define lpfc_sli_intf_slirev_MASK 0x0000000F 97 #define lpfc_sli_intf_slirev_WORD word0 98 #define LPFC_SLI_INTF_REV_SLI3 3 99 #define LPFC_SLI_INTF_REV_SLI4 4 100 #define lpfc_sli_intf_func_type_SHIFT 0 101 #define lpfc_sli_intf_func_type_MASK 0x00000001 102 #define lpfc_sli_intf_func_type_WORD word0 103 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 104 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 105 }; 106 107 #define LPFC_SLI4_MBX_EMBED true 108 #define LPFC_SLI4_MBX_NEMBED false 109 110 #define LPFC_SLI4_MB_WORD_COUNT 64 111 #define LPFC_MAX_MQ_PAGE 8 112 #define LPFC_MAX_WQ_PAGE_V0 4 113 #define LPFC_MAX_WQ_PAGE 8 114 #define LPFC_MAX_RQ_PAGE 8 115 #define LPFC_MAX_CQ_PAGE 4 116 #define LPFC_MAX_EQ_PAGE 8 117 118 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 119 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 120 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 121 122 /* Define SLI4 Alignment requirements. */ 123 #define LPFC_ALIGN_16_BYTE 16 124 #define LPFC_ALIGN_64_BYTE 64 125 126 /* Define SLI4 specific definitions. */ 127 #define LPFC_MQ_CQE_BYTE_OFFSET 256 128 #define LPFC_MBX_CMD_HDR_LENGTH 16 129 #define LPFC_MBX_ERROR_RANGE 0x4000 130 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 131 #define LPFC_BMBX_BIT1_ADDR_LO 0 132 #define LPFC_RPI_HDR_COUNT 64 133 #define LPFC_HDR_TEMPLATE_SIZE 4096 134 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 135 #define LPFC_FCF_RECORD_WD_CNT 132 136 #define LPFC_ENTIRE_FCF_DATABASE 0 137 #define LPFC_DFLT_FCF_INDEX 0 138 139 /* Virtual function numbers */ 140 #define LPFC_VF0 0 141 #define LPFC_VF1 1 142 #define LPFC_VF2 2 143 #define LPFC_VF3 3 144 #define LPFC_VF4 4 145 #define LPFC_VF5 5 146 #define LPFC_VF6 6 147 #define LPFC_VF7 7 148 #define LPFC_VF8 8 149 #define LPFC_VF9 9 150 #define LPFC_VF10 10 151 #define LPFC_VF11 11 152 #define LPFC_VF12 12 153 #define LPFC_VF13 13 154 #define LPFC_VF14 14 155 #define LPFC_VF15 15 156 #define LPFC_VF16 16 157 #define LPFC_VF17 17 158 #define LPFC_VF18 18 159 #define LPFC_VF19 19 160 #define LPFC_VF20 20 161 #define LPFC_VF21 21 162 #define LPFC_VF22 22 163 #define LPFC_VF23 23 164 #define LPFC_VF24 24 165 #define LPFC_VF25 25 166 #define LPFC_VF26 26 167 #define LPFC_VF27 27 168 #define LPFC_VF28 28 169 #define LPFC_VF29 29 170 #define LPFC_VF30 30 171 #define LPFC_VF31 31 172 173 /* PCI function numbers */ 174 #define LPFC_PCI_FUNC0 0 175 #define LPFC_PCI_FUNC1 1 176 #define LPFC_PCI_FUNC2 2 177 #define LPFC_PCI_FUNC3 3 178 #define LPFC_PCI_FUNC4 4 179 180 /* SLI4 interface type-2 PDEV_CTL register */ 181 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 182 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 183 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 184 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 185 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 186 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 188 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 189 190 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 191 192 /* Active interrupt test count */ 193 #define LPFC_ACT_INTR_CNT 4 194 195 /* Algrithmns for scheduling FCP commands to WQs */ 196 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 197 #define LPFC_FCP_SCHED_BY_CPU 1 198 199 /* Delay Multiplier constant */ 200 #define LPFC_DMULT_CONST 651042 201 #define LPFC_DMULT_MAX 1023 202 203 /* Configuration of Interrupts / sec for entire HBA port */ 204 #define LPFC_MIN_IMAX 5000 205 #define LPFC_MAX_IMAX 5000000 206 #define LPFC_DEF_IMAX 150000 207 208 #define LPFC_MIN_CPU_MAP 0 209 #define LPFC_MAX_CPU_MAP 2 210 #define LPFC_HBA_CPU_MAP 1 211 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 212 213 /* PORT_CAPABILITIES constants. */ 214 #define LPFC_MAX_SUPPORTED_PAGES 8 215 216 struct ulp_bde64 { 217 union ULP_BDE_TUS { 218 uint32_t w; 219 struct { 220 #ifdef __BIG_ENDIAN_BITFIELD 221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 222 VALUE !! */ 223 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 224 #else /* __LITTLE_ENDIAN_BITFIELD */ 225 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 226 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 227 VALUE !! */ 228 #endif 229 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 230 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 231 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 232 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 233 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 234 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 235 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 236 } f; 237 } tus; 238 uint32_t addrLow; 239 uint32_t addrHigh; 240 }; 241 242 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 243 #define LPFC_MAX_BDE_IMM_SIZE 64 244 245 struct lpfc_sli4_flags { 246 uint32_t word0; 247 #define lpfc_idx_rsrc_rdy_SHIFT 0 248 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 249 #define lpfc_idx_rsrc_rdy_WORD word0 250 #define LPFC_IDX_RSRC_RDY 1 251 #define lpfc_rpi_rsrc_rdy_SHIFT 1 252 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 253 #define lpfc_rpi_rsrc_rdy_WORD word0 254 #define LPFC_RPI_RSRC_RDY 1 255 #define lpfc_vpi_rsrc_rdy_SHIFT 2 256 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 257 #define lpfc_vpi_rsrc_rdy_WORD word0 258 #define LPFC_VPI_RSRC_RDY 1 259 #define lpfc_vfi_rsrc_rdy_SHIFT 3 260 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 261 #define lpfc_vfi_rsrc_rdy_WORD word0 262 #define LPFC_VFI_RSRC_RDY 1 263 }; 264 265 struct sli4_bls_rsp { 266 uint32_t word0_rsvd; /* Word0 must be reserved */ 267 uint32_t word1; 268 #define lpfc_abts_orig_SHIFT 0 269 #define lpfc_abts_orig_MASK 0x00000001 270 #define lpfc_abts_orig_WORD word1 271 #define LPFC_ABTS_UNSOL_RSP 1 272 #define LPFC_ABTS_UNSOL_INT 0 273 uint32_t word2; 274 #define lpfc_abts_rxid_SHIFT 0 275 #define lpfc_abts_rxid_MASK 0x0000FFFF 276 #define lpfc_abts_rxid_WORD word2 277 #define lpfc_abts_oxid_SHIFT 16 278 #define lpfc_abts_oxid_MASK 0x0000FFFF 279 #define lpfc_abts_oxid_WORD word2 280 uint32_t word3; 281 #define lpfc_vndr_code_SHIFT 0 282 #define lpfc_vndr_code_MASK 0x000000FF 283 #define lpfc_vndr_code_WORD word3 284 #define lpfc_rsn_expln_SHIFT 8 285 #define lpfc_rsn_expln_MASK 0x000000FF 286 #define lpfc_rsn_expln_WORD word3 287 #define lpfc_rsn_code_SHIFT 16 288 #define lpfc_rsn_code_MASK 0x000000FF 289 #define lpfc_rsn_code_WORD word3 290 291 uint32_t word4; 292 uint32_t word5_rsvd; /* Word5 must be reserved */ 293 }; 294 295 /* event queue entry structure */ 296 struct lpfc_eqe { 297 uint32_t word0; 298 #define lpfc_eqe_resource_id_SHIFT 16 299 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 300 #define lpfc_eqe_resource_id_WORD word0 301 #define lpfc_eqe_minor_code_SHIFT 4 302 #define lpfc_eqe_minor_code_MASK 0x00000FFF 303 #define lpfc_eqe_minor_code_WORD word0 304 #define lpfc_eqe_major_code_SHIFT 1 305 #define lpfc_eqe_major_code_MASK 0x00000007 306 #define lpfc_eqe_major_code_WORD word0 307 #define lpfc_eqe_valid_SHIFT 0 308 #define lpfc_eqe_valid_MASK 0x00000001 309 #define lpfc_eqe_valid_WORD word0 310 }; 311 312 /* completion queue entry structure (common fields for all cqe types) */ 313 struct lpfc_cqe { 314 uint32_t reserved0; 315 uint32_t reserved1; 316 uint32_t reserved2; 317 uint32_t word3; 318 #define lpfc_cqe_valid_SHIFT 31 319 #define lpfc_cqe_valid_MASK 0x00000001 320 #define lpfc_cqe_valid_WORD word3 321 #define lpfc_cqe_code_SHIFT 16 322 #define lpfc_cqe_code_MASK 0x000000FF 323 #define lpfc_cqe_code_WORD word3 324 }; 325 326 /* Completion Queue Entry Status Codes */ 327 #define CQE_STATUS_SUCCESS 0x0 328 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 329 #define CQE_STATUS_REMOTE_STOP 0x2 330 #define CQE_STATUS_LOCAL_REJECT 0x3 331 #define CQE_STATUS_NPORT_RJT 0x4 332 #define CQE_STATUS_FABRIC_RJT 0x5 333 #define CQE_STATUS_NPORT_BSY 0x6 334 #define CQE_STATUS_FABRIC_BSY 0x7 335 #define CQE_STATUS_INTERMED_RSP 0x8 336 #define CQE_STATUS_LS_RJT 0x9 337 #define CQE_STATUS_CMD_REJECT 0xb 338 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 339 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 340 #define CQE_STATUS_DI_ERROR 0x16 341 342 /* Used when mapping CQE status to IOCB */ 343 #define LPFC_IOCB_STATUS_MASK 0xf 344 345 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 346 #define CQE_HW_STATUS_NO_ERR 0x0 347 #define CQE_HW_STATUS_UNDERRUN 0x1 348 #define CQE_HW_STATUS_OVERRUN 0x2 349 350 /* Completion Queue Entry Codes */ 351 #define CQE_CODE_COMPL_WQE 0x1 352 #define CQE_CODE_RELEASE_WQE 0x2 353 #define CQE_CODE_RECEIVE 0x4 354 #define CQE_CODE_XRI_ABORTED 0x5 355 #define CQE_CODE_RECEIVE_V1 0x9 356 #define CQE_CODE_NVME_ERSP 0xd 357 358 /* 359 * Define mask value for xri_aborted and wcqe completed CQE extended status. 360 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 361 */ 362 #define WCQE_PARAM_MASK 0x1FF 363 364 /* completion queue entry for wqe completions */ 365 struct lpfc_wcqe_complete { 366 uint32_t word0; 367 #define lpfc_wcqe_c_request_tag_SHIFT 16 368 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 369 #define lpfc_wcqe_c_request_tag_WORD word0 370 #define lpfc_wcqe_c_status_SHIFT 8 371 #define lpfc_wcqe_c_status_MASK 0x000000FF 372 #define lpfc_wcqe_c_status_WORD word0 373 #define lpfc_wcqe_c_hw_status_SHIFT 0 374 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 375 #define lpfc_wcqe_c_hw_status_WORD word0 376 #define lpfc_wcqe_c_ersp0_SHIFT 0 377 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 378 #define lpfc_wcqe_c_ersp0_WORD word0 379 uint32_t total_data_placed; 380 uint32_t parameter; 381 #define lpfc_wcqe_c_bg_edir_SHIFT 5 382 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 383 #define lpfc_wcqe_c_bg_edir_WORD parameter 384 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 385 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 386 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 387 #define lpfc_wcqe_c_bg_re_SHIFT 2 388 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 389 #define lpfc_wcqe_c_bg_re_WORD parameter 390 #define lpfc_wcqe_c_bg_ae_SHIFT 1 391 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 392 #define lpfc_wcqe_c_bg_ae_WORD parameter 393 #define lpfc_wcqe_c_bg_ge_SHIFT 0 394 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 395 #define lpfc_wcqe_c_bg_ge_WORD parameter 396 uint32_t word3; 397 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 398 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 399 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 400 #define lpfc_wcqe_c_xb_SHIFT 28 401 #define lpfc_wcqe_c_xb_MASK 0x00000001 402 #define lpfc_wcqe_c_xb_WORD word3 403 #define lpfc_wcqe_c_pv_SHIFT 27 404 #define lpfc_wcqe_c_pv_MASK 0x00000001 405 #define lpfc_wcqe_c_pv_WORD word3 406 #define lpfc_wcqe_c_priority_SHIFT 24 407 #define lpfc_wcqe_c_priority_MASK 0x00000007 408 #define lpfc_wcqe_c_priority_WORD word3 409 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 410 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 411 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 412 #define lpfc_wcqe_c_sqhead_SHIFT 0 413 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 414 #define lpfc_wcqe_c_sqhead_WORD word3 415 }; 416 417 /* completion queue entry for wqe release */ 418 struct lpfc_wcqe_release { 419 uint32_t reserved0; 420 uint32_t reserved1; 421 uint32_t word2; 422 #define lpfc_wcqe_r_wq_id_SHIFT 16 423 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 424 #define lpfc_wcqe_r_wq_id_WORD word2 425 #define lpfc_wcqe_r_wqe_index_SHIFT 0 426 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 427 #define lpfc_wcqe_r_wqe_index_WORD word2 428 uint32_t word3; 429 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 430 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 431 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 432 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 433 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 434 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 435 }; 436 437 struct sli4_wcqe_xri_aborted { 438 uint32_t word0; 439 #define lpfc_wcqe_xa_status_SHIFT 8 440 #define lpfc_wcqe_xa_status_MASK 0x000000FF 441 #define lpfc_wcqe_xa_status_WORD word0 442 uint32_t parameter; 443 uint32_t word2; 444 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 445 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 446 #define lpfc_wcqe_xa_remote_xid_WORD word2 447 #define lpfc_wcqe_xa_xri_SHIFT 0 448 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 449 #define lpfc_wcqe_xa_xri_WORD word2 450 uint32_t word3; 451 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 452 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 453 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 454 #define lpfc_wcqe_xa_ia_SHIFT 30 455 #define lpfc_wcqe_xa_ia_MASK 0x00000001 456 #define lpfc_wcqe_xa_ia_WORD word3 457 #define CQE_XRI_ABORTED_IA_REMOTE 0 458 #define CQE_XRI_ABORTED_IA_LOCAL 1 459 #define lpfc_wcqe_xa_br_SHIFT 29 460 #define lpfc_wcqe_xa_br_MASK 0x00000001 461 #define lpfc_wcqe_xa_br_WORD word3 462 #define CQE_XRI_ABORTED_BR_BA_ACC 0 463 #define CQE_XRI_ABORTED_BR_BA_RJT 1 464 #define lpfc_wcqe_xa_eo_SHIFT 28 465 #define lpfc_wcqe_xa_eo_MASK 0x00000001 466 #define lpfc_wcqe_xa_eo_WORD word3 467 #define CQE_XRI_ABORTED_EO_REMOTE 0 468 #define CQE_XRI_ABORTED_EO_LOCAL 1 469 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 470 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 471 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 472 }; 473 474 /* completion queue entry structure for rqe completion */ 475 struct lpfc_rcqe { 476 uint32_t word0; 477 #define lpfc_rcqe_bindex_SHIFT 16 478 #define lpfc_rcqe_bindex_MASK 0x0000FFF 479 #define lpfc_rcqe_bindex_WORD word0 480 #define lpfc_rcqe_status_SHIFT 8 481 #define lpfc_rcqe_status_MASK 0x000000FF 482 #define lpfc_rcqe_status_WORD word0 483 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 484 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 485 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 486 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 487 uint32_t word1; 488 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 489 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 490 #define lpfc_rcqe_fcf_id_v1_WORD word1 491 uint32_t word2; 492 #define lpfc_rcqe_length_SHIFT 16 493 #define lpfc_rcqe_length_MASK 0x0000FFFF 494 #define lpfc_rcqe_length_WORD word2 495 #define lpfc_rcqe_rq_id_SHIFT 6 496 #define lpfc_rcqe_rq_id_MASK 0x000003FF 497 #define lpfc_rcqe_rq_id_WORD word2 498 #define lpfc_rcqe_fcf_id_SHIFT 0 499 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 500 #define lpfc_rcqe_fcf_id_WORD word2 501 #define lpfc_rcqe_rq_id_v1_SHIFT 0 502 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 503 #define lpfc_rcqe_rq_id_v1_WORD word2 504 uint32_t word3; 505 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 506 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 507 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 508 #define lpfc_rcqe_port_SHIFT 30 509 #define lpfc_rcqe_port_MASK 0x00000001 510 #define lpfc_rcqe_port_WORD word3 511 #define lpfc_rcqe_hdr_length_SHIFT 24 512 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 513 #define lpfc_rcqe_hdr_length_WORD word3 514 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 515 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 516 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 517 #define lpfc_rcqe_eof_SHIFT 8 518 #define lpfc_rcqe_eof_MASK 0x000000FF 519 #define lpfc_rcqe_eof_WORD word3 520 #define FCOE_EOFn 0x41 521 #define FCOE_EOFt 0x42 522 #define FCOE_EOFni 0x49 523 #define FCOE_EOFa 0x50 524 #define lpfc_rcqe_sof_SHIFT 0 525 #define lpfc_rcqe_sof_MASK 0x000000FF 526 #define lpfc_rcqe_sof_WORD word3 527 #define FCOE_SOFi2 0x2d 528 #define FCOE_SOFi3 0x2e 529 #define FCOE_SOFn2 0x35 530 #define FCOE_SOFn3 0x36 531 }; 532 533 struct lpfc_rqe { 534 uint32_t address_hi; 535 uint32_t address_lo; 536 }; 537 538 /* buffer descriptors */ 539 struct lpfc_bde4 { 540 uint32_t addr_hi; 541 uint32_t addr_lo; 542 uint32_t word2; 543 #define lpfc_bde4_last_SHIFT 31 544 #define lpfc_bde4_last_MASK 0x00000001 545 #define lpfc_bde4_last_WORD word2 546 #define lpfc_bde4_sge_offset_SHIFT 0 547 #define lpfc_bde4_sge_offset_MASK 0x000003FF 548 #define lpfc_bde4_sge_offset_WORD word2 549 uint32_t word3; 550 #define lpfc_bde4_length_SHIFT 0 551 #define lpfc_bde4_length_MASK 0x000000FF 552 #define lpfc_bde4_length_WORD word3 553 }; 554 555 struct lpfc_register { 556 uint32_t word0; 557 }; 558 559 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 560 #define LPFC_PORT_SEM_MASK 0xF000 561 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 562 #define LPFC_UERR_STATUS_HI 0x00A4 563 #define LPFC_UERR_STATUS_LO 0x00A0 564 #define LPFC_UE_MASK_HI 0x00AC 565 #define LPFC_UE_MASK_LO 0x00A8 566 567 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 568 #define LPFC_SLI_INTF 0x0058 569 #define LPFC_SLI_ASIC_VER 0x009C 570 571 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 572 #define lpfc_port_smphr_perr_SHIFT 31 573 #define lpfc_port_smphr_perr_MASK 0x1 574 #define lpfc_port_smphr_perr_WORD word0 575 #define lpfc_port_smphr_sfi_SHIFT 30 576 #define lpfc_port_smphr_sfi_MASK 0x1 577 #define lpfc_port_smphr_sfi_WORD word0 578 #define lpfc_port_smphr_nip_SHIFT 29 579 #define lpfc_port_smphr_nip_MASK 0x1 580 #define lpfc_port_smphr_nip_WORD word0 581 #define lpfc_port_smphr_ipc_SHIFT 28 582 #define lpfc_port_smphr_ipc_MASK 0x1 583 #define lpfc_port_smphr_ipc_WORD word0 584 #define lpfc_port_smphr_scr1_SHIFT 27 585 #define lpfc_port_smphr_scr1_MASK 0x1 586 #define lpfc_port_smphr_scr1_WORD word0 587 #define lpfc_port_smphr_scr2_SHIFT 26 588 #define lpfc_port_smphr_scr2_MASK 0x1 589 #define lpfc_port_smphr_scr2_WORD word0 590 #define lpfc_port_smphr_host_scratch_SHIFT 16 591 #define lpfc_port_smphr_host_scratch_MASK 0xFF 592 #define lpfc_port_smphr_host_scratch_WORD word0 593 #define lpfc_port_smphr_port_status_SHIFT 0 594 #define lpfc_port_smphr_port_status_MASK 0xFFFF 595 #define lpfc_port_smphr_port_status_WORD word0 596 597 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 598 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 599 #define LPFC_POST_STAGE_HOST_RDY 0x0002 600 #define LPFC_POST_STAGE_BE_RESET 0x0003 601 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 602 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 603 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 604 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 605 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 606 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 607 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 608 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 609 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 610 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 611 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 612 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 613 #define LPFC_POST_STAGE_ARMFW_START 0x0800 614 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 615 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 616 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 617 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 618 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 619 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 620 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 621 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 622 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 623 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 624 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 625 #define LPFC_POST_STAGE_RC_DONE 0x0B07 626 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 627 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 628 #define LPFC_POST_STAGE_PORT_READY 0xC000 629 #define LPFC_POST_STAGE_PORT_UE 0xF000 630 631 #define LPFC_CTL_PORT_STA_OFFSET 0x404 632 #define lpfc_sliport_status_err_SHIFT 31 633 #define lpfc_sliport_status_err_MASK 0x1 634 #define lpfc_sliport_status_err_WORD word0 635 #define lpfc_sliport_status_end_SHIFT 30 636 #define lpfc_sliport_status_end_MASK 0x1 637 #define lpfc_sliport_status_end_WORD word0 638 #define lpfc_sliport_status_oti_SHIFT 29 639 #define lpfc_sliport_status_oti_MASK 0x1 640 #define lpfc_sliport_status_oti_WORD word0 641 #define lpfc_sliport_status_rn_SHIFT 24 642 #define lpfc_sliport_status_rn_MASK 0x1 643 #define lpfc_sliport_status_rn_WORD word0 644 #define lpfc_sliport_status_rdy_SHIFT 23 645 #define lpfc_sliport_status_rdy_MASK 0x1 646 #define lpfc_sliport_status_rdy_WORD word0 647 #define MAX_IF_TYPE_2_RESETS 6 648 649 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 650 #define lpfc_sliport_ctrl_end_SHIFT 30 651 #define lpfc_sliport_ctrl_end_MASK 0x1 652 #define lpfc_sliport_ctrl_end_WORD word0 653 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 654 #define LPFC_SLIPORT_BIG_ENDIAN 1 655 #define lpfc_sliport_ctrl_ip_SHIFT 27 656 #define lpfc_sliport_ctrl_ip_MASK 0x1 657 #define lpfc_sliport_ctrl_ip_WORD word0 658 #define LPFC_SLIPORT_INIT_PORT 1 659 660 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 661 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 662 663 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 664 #define lpfc_sliport_eqdelay_delay_SHIFT 16 665 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 666 #define lpfc_sliport_eqdelay_delay_WORD word0 667 #define lpfc_sliport_eqdelay_id_SHIFT 0 668 #define lpfc_sliport_eqdelay_id_MASK 0xfff 669 #define lpfc_sliport_eqdelay_id_WORD word0 670 #define LPFC_SEC_TO_USEC 1000000 671 672 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 673 * reside in BAR 2. 674 */ 675 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 676 677 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 678 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 679 680 #define LPFC_HST_ISR0 0x0C18 681 #define LPFC_HST_ISR1 0x0C1C 682 #define LPFC_HST_ISR2 0x0C20 683 #define LPFC_HST_ISR3 0x0C24 684 #define LPFC_HST_ISR4 0x0C28 685 686 #define LPFC_HST_IMR0 0x0C48 687 #define LPFC_HST_IMR1 0x0C4C 688 #define LPFC_HST_IMR2 0x0C50 689 #define LPFC_HST_IMR3 0x0C54 690 #define LPFC_HST_IMR4 0x0C58 691 692 #define LPFC_HST_ISCR0 0x0C78 693 #define LPFC_HST_ISCR1 0x0C7C 694 #define LPFC_HST_ISCR2 0x0C80 695 #define LPFC_HST_ISCR3 0x0C84 696 #define LPFC_HST_ISCR4 0x0C88 697 698 #define LPFC_SLI4_INTR0 BIT0 699 #define LPFC_SLI4_INTR1 BIT1 700 #define LPFC_SLI4_INTR2 BIT2 701 #define LPFC_SLI4_INTR3 BIT3 702 #define LPFC_SLI4_INTR4 BIT4 703 #define LPFC_SLI4_INTR5 BIT5 704 #define LPFC_SLI4_INTR6 BIT6 705 #define LPFC_SLI4_INTR7 BIT7 706 #define LPFC_SLI4_INTR8 BIT8 707 #define LPFC_SLI4_INTR9 BIT9 708 #define LPFC_SLI4_INTR10 BIT10 709 #define LPFC_SLI4_INTR11 BIT11 710 #define LPFC_SLI4_INTR12 BIT12 711 #define LPFC_SLI4_INTR13 BIT13 712 #define LPFC_SLI4_INTR14 BIT14 713 #define LPFC_SLI4_INTR15 BIT15 714 #define LPFC_SLI4_INTR16 BIT16 715 #define LPFC_SLI4_INTR17 BIT17 716 #define LPFC_SLI4_INTR18 BIT18 717 #define LPFC_SLI4_INTR19 BIT19 718 #define LPFC_SLI4_INTR20 BIT20 719 #define LPFC_SLI4_INTR21 BIT21 720 #define LPFC_SLI4_INTR22 BIT22 721 #define LPFC_SLI4_INTR23 BIT23 722 #define LPFC_SLI4_INTR24 BIT24 723 #define LPFC_SLI4_INTR25 BIT25 724 #define LPFC_SLI4_INTR26 BIT26 725 #define LPFC_SLI4_INTR27 BIT27 726 #define LPFC_SLI4_INTR28 BIT28 727 #define LPFC_SLI4_INTR29 BIT29 728 #define LPFC_SLI4_INTR30 BIT30 729 #define LPFC_SLI4_INTR31 BIT31 730 731 /* 732 * The Doorbell registers defined here exist in different BAR 733 * register sets depending on the UCNA Port's reported if_type 734 * value. For UCNA ports running SLI4 and if_type 0, they reside in 735 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 736 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 737 * BAR2. The offsets and base address are different, so the driver 738 * has to compute the register addresses accordingly 739 */ 740 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 741 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 742 #define LPFC_IF6_RQ_DOORBELL 0x0080 743 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 744 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 745 #define lpfc_rq_db_list_fm_num_posted_WORD word0 746 #define lpfc_rq_db_list_fm_index_SHIFT 16 747 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 748 #define lpfc_rq_db_list_fm_index_WORD word0 749 #define lpfc_rq_db_list_fm_id_SHIFT 0 750 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 751 #define lpfc_rq_db_list_fm_id_WORD word0 752 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 753 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 754 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 755 #define lpfc_rq_db_ring_fm_id_SHIFT 0 756 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 757 #define lpfc_rq_db_ring_fm_id_WORD word0 758 759 #define LPFC_ULP0_WQ_DOORBELL 0x0040 760 #define LPFC_ULP1_WQ_DOORBELL 0x0060 761 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 762 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 763 #define lpfc_wq_db_list_fm_num_posted_WORD word0 764 #define lpfc_wq_db_list_fm_index_SHIFT 16 765 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 766 #define lpfc_wq_db_list_fm_index_WORD word0 767 #define lpfc_wq_db_list_fm_id_SHIFT 0 768 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 769 #define lpfc_wq_db_list_fm_id_WORD word0 770 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 771 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 772 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 773 #define lpfc_wq_db_ring_fm_id_SHIFT 0 774 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 775 #define lpfc_wq_db_ring_fm_id_WORD word0 776 777 #define LPFC_IF6_WQ_DOORBELL 0x0040 778 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 779 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 780 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 781 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 782 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 783 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 784 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 785 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 786 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 787 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 788 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 789 #define lpfc_if6_wq_db_list_fm_id_WORD word0 790 791 #define LPFC_EQCQ_DOORBELL 0x0120 792 #define lpfc_eqcq_doorbell_se_SHIFT 31 793 #define lpfc_eqcq_doorbell_se_MASK 0x0001 794 #define lpfc_eqcq_doorbell_se_WORD word0 795 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 796 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 797 #define lpfc_eqcq_doorbell_arm_SHIFT 29 798 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 799 #define lpfc_eqcq_doorbell_arm_WORD word0 800 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 801 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 802 #define lpfc_eqcq_doorbell_num_released_WORD word0 803 #define lpfc_eqcq_doorbell_qt_SHIFT 10 804 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 805 #define lpfc_eqcq_doorbell_qt_WORD word0 806 #define LPFC_QUEUE_TYPE_COMPLETION 0 807 #define LPFC_QUEUE_TYPE_EVENT 1 808 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 809 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 810 #define lpfc_eqcq_doorbell_eqci_WORD word0 811 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 812 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 813 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 814 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 815 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 816 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 817 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 818 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 819 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 820 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 821 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 822 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 823 #define LPFC_CQID_HI_FIELD_SHIFT 10 824 #define LPFC_EQID_HI_FIELD_SHIFT 9 825 826 #define LPFC_IF6_CQ_DOORBELL 0x00C0 827 #define lpfc_if6_cq_doorbell_se_SHIFT 31 828 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 829 #define lpfc_if6_cq_doorbell_se_WORD word0 830 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 831 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 832 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 833 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 834 #define lpfc_if6_cq_doorbell_arm_WORD word0 835 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 836 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 837 #define lpfc_if6_cq_doorbell_num_released_WORD word0 838 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 839 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 840 #define lpfc_if6_cq_doorbell_cqid_WORD word0 841 842 #define LPFC_IF6_EQ_DOORBELL 0x0120 843 #define lpfc_if6_eq_doorbell_io_SHIFT 31 844 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 845 #define lpfc_if6_eq_doorbell_io_WORD word0 846 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 847 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 848 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 849 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 850 #define lpfc_if6_eq_doorbell_arm_WORD word0 851 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 852 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 853 #define lpfc_if6_eq_doorbell_num_released_WORD word0 854 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 855 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 856 #define lpfc_if6_eq_doorbell_eqid_WORD word0 857 858 #define LPFC_BMBX 0x0160 859 #define lpfc_bmbx_addr_SHIFT 2 860 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 861 #define lpfc_bmbx_addr_WORD word0 862 #define lpfc_bmbx_hi_SHIFT 1 863 #define lpfc_bmbx_hi_MASK 0x0001 864 #define lpfc_bmbx_hi_WORD word0 865 #define lpfc_bmbx_rdy_SHIFT 0 866 #define lpfc_bmbx_rdy_MASK 0x0001 867 #define lpfc_bmbx_rdy_WORD word0 868 869 #define LPFC_MQ_DOORBELL 0x0140 870 #define LPFC_IF6_MQ_DOORBELL 0x0160 871 #define lpfc_mq_doorbell_num_posted_SHIFT 16 872 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 873 #define lpfc_mq_doorbell_num_posted_WORD word0 874 #define lpfc_mq_doorbell_id_SHIFT 0 875 #define lpfc_mq_doorbell_id_MASK 0xFFFF 876 #define lpfc_mq_doorbell_id_WORD word0 877 878 struct lpfc_sli4_cfg_mhdr { 879 uint32_t word1; 880 #define lpfc_mbox_hdr_emb_SHIFT 0 881 #define lpfc_mbox_hdr_emb_MASK 0x00000001 882 #define lpfc_mbox_hdr_emb_WORD word1 883 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 884 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 885 #define lpfc_mbox_hdr_sge_cnt_WORD word1 886 uint32_t payload_length; 887 uint32_t tag_lo; 888 uint32_t tag_hi; 889 uint32_t reserved5; 890 }; 891 892 union lpfc_sli4_cfg_shdr { 893 struct { 894 uint32_t word6; 895 #define lpfc_mbox_hdr_opcode_SHIFT 0 896 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 897 #define lpfc_mbox_hdr_opcode_WORD word6 898 #define lpfc_mbox_hdr_subsystem_SHIFT 8 899 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 900 #define lpfc_mbox_hdr_subsystem_WORD word6 901 #define lpfc_mbox_hdr_port_number_SHIFT 16 902 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 903 #define lpfc_mbox_hdr_port_number_WORD word6 904 #define lpfc_mbox_hdr_domain_SHIFT 24 905 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 906 #define lpfc_mbox_hdr_domain_WORD word6 907 uint32_t timeout; 908 uint32_t request_length; 909 uint32_t word9; 910 #define lpfc_mbox_hdr_version_SHIFT 0 911 #define lpfc_mbox_hdr_version_MASK 0x000000FF 912 #define lpfc_mbox_hdr_version_WORD word9 913 #define lpfc_mbox_hdr_pf_num_SHIFT 16 914 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 915 #define lpfc_mbox_hdr_pf_num_WORD word9 916 #define lpfc_mbox_hdr_vh_num_SHIFT 24 917 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 918 #define lpfc_mbox_hdr_vh_num_WORD word9 919 #define LPFC_Q_CREATE_VERSION_2 2 920 #define LPFC_Q_CREATE_VERSION_1 1 921 #define LPFC_Q_CREATE_VERSION_0 0 922 #define LPFC_OPCODE_VERSION_0 0 923 #define LPFC_OPCODE_VERSION_1 1 924 } request; 925 struct { 926 uint32_t word6; 927 #define lpfc_mbox_hdr_opcode_SHIFT 0 928 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 929 #define lpfc_mbox_hdr_opcode_WORD word6 930 #define lpfc_mbox_hdr_subsystem_SHIFT 8 931 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 932 #define lpfc_mbox_hdr_subsystem_WORD word6 933 #define lpfc_mbox_hdr_domain_SHIFT 24 934 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 935 #define lpfc_mbox_hdr_domain_WORD word6 936 uint32_t word7; 937 #define lpfc_mbox_hdr_status_SHIFT 0 938 #define lpfc_mbox_hdr_status_MASK 0x000000FF 939 #define lpfc_mbox_hdr_status_WORD word7 940 #define lpfc_mbox_hdr_add_status_SHIFT 8 941 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 942 #define lpfc_mbox_hdr_add_status_WORD word7 943 uint32_t response_length; 944 uint32_t actual_response_length; 945 } response; 946 }; 947 948 /* Mailbox Header structures. 949 * struct mbox_header is defined for first generation SLI4_CFG mailbox 950 * calls deployed for BE-based ports. 951 * 952 * struct sli4_mbox_header is defined for second generation SLI4 953 * ports that don't deploy the SLI4_CFG mechanism. 954 */ 955 struct mbox_header { 956 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 957 union lpfc_sli4_cfg_shdr cfg_shdr; 958 }; 959 960 #define LPFC_EXTENT_LOCAL 0 961 #define LPFC_TIMEOUT_DEFAULT 0 962 #define LPFC_EXTENT_VERSION_DEFAULT 0 963 964 /* Subsystem Definitions */ 965 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 966 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 967 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 968 969 /* Device Specific Definitions */ 970 971 /* The HOST ENDIAN defines are in Big Endian format. */ 972 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 973 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 974 975 /* Common Opcodes */ 976 #define LPFC_MBOX_OPCODE_NA 0x00 977 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 978 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 979 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 980 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 981 #define LPFC_MBOX_OPCODE_NOP 0x21 982 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 983 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 984 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 985 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 986 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 987 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 988 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 989 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 990 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 991 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 992 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 993 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 994 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 995 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 996 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 997 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 998 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 999 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1000 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1001 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1002 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1003 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1004 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1005 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1006 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1007 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1008 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1009 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1010 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1011 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1012 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1013 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1014 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1015 1016 /* FCoE Opcodes */ 1017 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1018 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1019 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1020 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1021 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1022 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1023 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1024 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1025 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1026 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1027 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1028 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1029 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1030 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1031 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1032 1033 /* Mailbox command structures */ 1034 struct eq_context { 1035 uint32_t word0; 1036 #define lpfc_eq_context_size_SHIFT 31 1037 #define lpfc_eq_context_size_MASK 0x00000001 1038 #define lpfc_eq_context_size_WORD word0 1039 #define LPFC_EQE_SIZE_4 0x0 1040 #define LPFC_EQE_SIZE_16 0x1 1041 #define lpfc_eq_context_valid_SHIFT 29 1042 #define lpfc_eq_context_valid_MASK 0x00000001 1043 #define lpfc_eq_context_valid_WORD word0 1044 #define lpfc_eq_context_autovalid_SHIFT 28 1045 #define lpfc_eq_context_autovalid_MASK 0x00000001 1046 #define lpfc_eq_context_autovalid_WORD word0 1047 uint32_t word1; 1048 #define lpfc_eq_context_count_SHIFT 26 1049 #define lpfc_eq_context_count_MASK 0x00000003 1050 #define lpfc_eq_context_count_WORD word1 1051 #define LPFC_EQ_CNT_256 0x0 1052 #define LPFC_EQ_CNT_512 0x1 1053 #define LPFC_EQ_CNT_1024 0x2 1054 #define LPFC_EQ_CNT_2048 0x3 1055 #define LPFC_EQ_CNT_4096 0x4 1056 uint32_t word2; 1057 #define lpfc_eq_context_delay_multi_SHIFT 13 1058 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1059 #define lpfc_eq_context_delay_multi_WORD word2 1060 uint32_t reserved3; 1061 }; 1062 1063 struct eq_delay_info { 1064 uint32_t eq_id; 1065 uint32_t phase; 1066 uint32_t delay_multi; 1067 }; 1068 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1069 1070 struct sgl_page_pairs { 1071 uint32_t sgl_pg0_addr_lo; 1072 uint32_t sgl_pg0_addr_hi; 1073 uint32_t sgl_pg1_addr_lo; 1074 uint32_t sgl_pg1_addr_hi; 1075 }; 1076 1077 struct lpfc_mbx_post_sgl_pages { 1078 struct mbox_header header; 1079 uint32_t word0; 1080 #define lpfc_post_sgl_pages_xri_SHIFT 0 1081 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1082 #define lpfc_post_sgl_pages_xri_WORD word0 1083 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1084 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1085 #define lpfc_post_sgl_pages_xricnt_WORD word0 1086 struct sgl_page_pairs sgl_pg_pairs[1]; 1087 }; 1088 1089 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1090 struct lpfc_mbx_post_uembed_sgl_page1 { 1091 union lpfc_sli4_cfg_shdr cfg_shdr; 1092 uint32_t word0; 1093 struct sgl_page_pairs sgl_pg_pairs; 1094 }; 1095 1096 struct lpfc_mbx_sge { 1097 uint32_t pa_lo; 1098 uint32_t pa_hi; 1099 uint32_t length; 1100 }; 1101 1102 struct lpfc_mbx_nembed_cmd { 1103 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1104 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1105 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1106 }; 1107 1108 struct lpfc_mbx_nembed_sge_virt { 1109 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1110 }; 1111 1112 struct lpfc_mbx_eq_create { 1113 struct mbox_header header; 1114 union { 1115 struct { 1116 uint32_t word0; 1117 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1118 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1119 #define lpfc_mbx_eq_create_num_pages_WORD word0 1120 struct eq_context context; 1121 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1122 } request; 1123 struct { 1124 uint32_t word0; 1125 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1126 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1127 #define lpfc_mbx_eq_create_q_id_WORD word0 1128 } response; 1129 } u; 1130 }; 1131 1132 struct lpfc_mbx_modify_eq_delay { 1133 struct mbox_header header; 1134 union { 1135 struct { 1136 uint32_t num_eq; 1137 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1138 } request; 1139 struct { 1140 uint32_t word0; 1141 } response; 1142 } u; 1143 }; 1144 1145 struct lpfc_mbx_eq_destroy { 1146 struct mbox_header header; 1147 union { 1148 struct { 1149 uint32_t word0; 1150 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1151 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1152 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1153 } request; 1154 struct { 1155 uint32_t word0; 1156 } response; 1157 } u; 1158 }; 1159 1160 struct lpfc_mbx_nop { 1161 struct mbox_header header; 1162 uint32_t context[2]; 1163 }; 1164 1165 struct cq_context { 1166 uint32_t word0; 1167 #define lpfc_cq_context_event_SHIFT 31 1168 #define lpfc_cq_context_event_MASK 0x00000001 1169 #define lpfc_cq_context_event_WORD word0 1170 #define lpfc_cq_context_valid_SHIFT 29 1171 #define lpfc_cq_context_valid_MASK 0x00000001 1172 #define lpfc_cq_context_valid_WORD word0 1173 #define lpfc_cq_context_count_SHIFT 27 1174 #define lpfc_cq_context_count_MASK 0x00000003 1175 #define lpfc_cq_context_count_WORD word0 1176 #define LPFC_CQ_CNT_256 0x0 1177 #define LPFC_CQ_CNT_512 0x1 1178 #define LPFC_CQ_CNT_1024 0x2 1179 #define LPFC_CQ_CNT_WORD7 0x3 1180 #define lpfc_cq_context_autovalid_SHIFT 15 1181 #define lpfc_cq_context_autovalid_MASK 0x00000001 1182 #define lpfc_cq_context_autovalid_WORD word0 1183 uint32_t word1; 1184 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1185 #define lpfc_cq_eq_id_MASK 0x000000FF 1186 #define lpfc_cq_eq_id_WORD word1 1187 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1188 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1189 #define lpfc_cq_eq_id_2_WORD word1 1190 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1191 uint32_t reserved1; 1192 }; 1193 1194 struct lpfc_mbx_cq_create { 1195 struct mbox_header header; 1196 union { 1197 struct { 1198 uint32_t word0; 1199 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1200 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1201 #define lpfc_mbx_cq_create_page_size_WORD word0 1202 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1203 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1204 #define lpfc_mbx_cq_create_num_pages_WORD word0 1205 struct cq_context context; 1206 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1207 } request; 1208 struct { 1209 uint32_t word0; 1210 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1211 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1212 #define lpfc_mbx_cq_create_q_id_WORD word0 1213 } response; 1214 } u; 1215 }; 1216 1217 struct lpfc_mbx_cq_create_set { 1218 union lpfc_sli4_cfg_shdr cfg_shdr; 1219 union { 1220 struct { 1221 uint32_t word0; 1222 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1223 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1224 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1225 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1226 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1227 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1228 uint32_t word1; 1229 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1230 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1231 #define lpfc_mbx_cq_create_set_evt_WORD word1 1232 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1233 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1234 #define lpfc_mbx_cq_create_set_valid_WORD word1 1235 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1236 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1237 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1238 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1239 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1240 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1241 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1242 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1243 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1244 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1245 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1246 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1247 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1248 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1249 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1250 uint32_t word2; 1251 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1252 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1253 #define lpfc_mbx_cq_create_set_arm_WORD word2 1254 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1255 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1256 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1257 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1258 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1259 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1260 uint32_t word3; 1261 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1262 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1263 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1264 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1265 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1266 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1267 uint32_t word4; 1268 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1269 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1270 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1271 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1272 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1273 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1274 uint32_t word5; 1275 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1276 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1277 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1278 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1279 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1280 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1281 uint32_t word6; 1282 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1283 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1284 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1285 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1286 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1287 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1288 uint32_t word7; 1289 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1290 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1291 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1292 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1293 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1294 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1295 uint32_t word8; 1296 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1297 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1298 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1299 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1300 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1301 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1302 uint32_t word9; 1303 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1304 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1305 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1306 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1307 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1308 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1309 uint32_t word10; 1310 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1311 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1312 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1313 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1314 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1315 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1316 struct dma_address page[1]; 1317 } request; 1318 struct { 1319 uint32_t word0; 1320 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1321 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1322 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1323 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1324 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1325 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1326 } response; 1327 } u; 1328 }; 1329 1330 struct lpfc_mbx_cq_destroy { 1331 struct mbox_header header; 1332 union { 1333 struct { 1334 uint32_t word0; 1335 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1336 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1337 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1338 } request; 1339 struct { 1340 uint32_t word0; 1341 } response; 1342 } u; 1343 }; 1344 1345 struct wq_context { 1346 uint32_t reserved0; 1347 uint32_t reserved1; 1348 uint32_t reserved2; 1349 uint32_t reserved3; 1350 }; 1351 1352 struct lpfc_mbx_wq_create { 1353 struct mbox_header header; 1354 union { 1355 struct { /* Version 0 Request */ 1356 uint32_t word0; 1357 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1358 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1359 #define lpfc_mbx_wq_create_num_pages_WORD word0 1360 #define lpfc_mbx_wq_create_dua_SHIFT 8 1361 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1362 #define lpfc_mbx_wq_create_dua_WORD word0 1363 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1364 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1365 #define lpfc_mbx_wq_create_cq_id_WORD word0 1366 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1367 uint32_t word9; 1368 #define lpfc_mbx_wq_create_bua_SHIFT 0 1369 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1370 #define lpfc_mbx_wq_create_bua_WORD word9 1371 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1372 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1373 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1374 } request; 1375 struct { /* Version 1 Request */ 1376 uint32_t word0; /* Word 0 is the same as in v0 */ 1377 uint32_t word1; 1378 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1379 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1380 #define lpfc_mbx_wq_create_page_size_WORD word1 1381 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1382 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1383 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1384 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1385 #define lpfc_mbx_wq_create_doe_SHIFT 14 1386 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1387 #define lpfc_mbx_wq_create_doe_WORD word1 1388 #define lpfc_mbx_wq_create_toe_SHIFT 13 1389 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1390 #define lpfc_mbx_wq_create_toe_WORD word1 1391 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1392 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1393 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1394 #define LPFC_WQ_WQE_SIZE_64 0x5 1395 #define LPFC_WQ_WQE_SIZE_128 0x6 1396 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1397 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1398 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1399 uint32_t word2; 1400 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1401 } request_1; 1402 struct { 1403 uint32_t word0; 1404 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1405 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1406 #define lpfc_mbx_wq_create_q_id_WORD word0 1407 uint32_t doorbell_offset; 1408 uint32_t word2; 1409 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1410 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1411 #define lpfc_mbx_wq_create_bar_set_WORD word2 1412 #define WQ_PCI_BAR_0_AND_1 0x00 1413 #define WQ_PCI_BAR_2_AND_3 0x01 1414 #define WQ_PCI_BAR_4_AND_5 0x02 1415 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1416 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1417 #define lpfc_mbx_wq_create_db_format_WORD word2 1418 } response; 1419 struct { 1420 uint32_t word0; 1421 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1422 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1423 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1424 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1425 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1426 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1427 uint32_t word1; 1428 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1429 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1430 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1431 uint32_t doorbell_offset; 1432 uint32_t word3; 1433 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1434 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1435 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1436 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1437 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1438 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1439 uint32_t dpp_offset; 1440 } response_1; 1441 } u; 1442 }; 1443 1444 struct lpfc_mbx_wq_destroy { 1445 struct mbox_header header; 1446 union { 1447 struct { 1448 uint32_t word0; 1449 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1450 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1451 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1452 } request; 1453 struct { 1454 uint32_t word0; 1455 } response; 1456 } u; 1457 }; 1458 1459 #define LPFC_HDR_BUF_SIZE 128 1460 #define LPFC_DATA_BUF_SIZE 2048 1461 #define LPFC_NVMET_DATA_BUF_SIZE 128 1462 struct rq_context { 1463 uint32_t word0; 1464 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1465 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1466 #define lpfc_rq_context_rqe_count_WORD word0 1467 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1468 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1469 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1470 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1471 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1472 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1473 #define lpfc_rq_context_rqe_count_1_WORD word0 1474 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1475 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1476 #define lpfc_rq_context_rqe_size_WORD word0 1477 #define LPFC_RQE_SIZE_8 2 1478 #define LPFC_RQE_SIZE_16 3 1479 #define LPFC_RQE_SIZE_32 4 1480 #define LPFC_RQE_SIZE_64 5 1481 #define LPFC_RQE_SIZE_128 6 1482 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1483 #define lpfc_rq_context_page_size_MASK 0x000000FF 1484 #define lpfc_rq_context_page_size_WORD word0 1485 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1486 uint32_t word1; 1487 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1488 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1489 #define lpfc_rq_context_data_size_WORD word1 1490 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1491 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1492 #define lpfc_rq_context_hdr_size_WORD word1 1493 uint32_t word2; 1494 #define lpfc_rq_context_cq_id_SHIFT 16 1495 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1496 #define lpfc_rq_context_cq_id_WORD word2 1497 #define lpfc_rq_context_buf_size_SHIFT 0 1498 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1499 #define lpfc_rq_context_buf_size_WORD word2 1500 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1501 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1502 #define lpfc_rq_context_base_cq_WORD word2 1503 uint32_t buffer_size; /* Version 1 Only */ 1504 }; 1505 1506 struct lpfc_mbx_rq_create { 1507 struct mbox_header header; 1508 union { 1509 struct { 1510 uint32_t word0; 1511 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1512 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1513 #define lpfc_mbx_rq_create_num_pages_WORD word0 1514 #define lpfc_mbx_rq_create_dua_SHIFT 16 1515 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1516 #define lpfc_mbx_rq_create_dua_WORD word0 1517 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1518 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1519 #define lpfc_mbx_rq_create_bqu_WORD word0 1520 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1521 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1522 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1523 struct rq_context context; 1524 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1525 } request; 1526 struct { 1527 uint32_t word0; 1528 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1529 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1530 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1531 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1532 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1533 #define lpfc_mbx_rq_create_q_id_WORD word0 1534 uint32_t doorbell_offset; 1535 uint32_t word2; 1536 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1537 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1538 #define lpfc_mbx_rq_create_bar_set_WORD word2 1539 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1540 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1541 #define lpfc_mbx_rq_create_db_format_WORD word2 1542 } response; 1543 } u; 1544 }; 1545 1546 struct lpfc_mbx_rq_create_v2 { 1547 union lpfc_sli4_cfg_shdr cfg_shdr; 1548 union { 1549 struct { 1550 uint32_t word0; 1551 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1552 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1553 #define lpfc_mbx_rq_create_num_pages_WORD word0 1554 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1555 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1556 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1557 #define lpfc_mbx_rq_create_dua_SHIFT 16 1558 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1559 #define lpfc_mbx_rq_create_dua_WORD word0 1560 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1561 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1562 #define lpfc_mbx_rq_create_bqu_WORD word0 1563 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1564 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1565 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1566 #define lpfc_mbx_rq_create_dim_SHIFT 29 1567 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1568 #define lpfc_mbx_rq_create_dim_WORD word0 1569 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1570 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1571 #define lpfc_mbx_rq_create_dfd_WORD word0 1572 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1573 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1574 #define lpfc_mbx_rq_create_dnb_WORD word0 1575 struct rq_context context; 1576 struct dma_address page[1]; 1577 } request; 1578 struct { 1579 uint32_t word0; 1580 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1581 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1582 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1583 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1584 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1585 #define lpfc_mbx_rq_create_q_id_WORD word0 1586 uint32_t doorbell_offset; 1587 uint32_t word2; 1588 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1589 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1590 #define lpfc_mbx_rq_create_bar_set_WORD word2 1591 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1592 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1593 #define lpfc_mbx_rq_create_db_format_WORD word2 1594 } response; 1595 } u; 1596 }; 1597 1598 struct lpfc_mbx_rq_destroy { 1599 struct mbox_header header; 1600 union { 1601 struct { 1602 uint32_t word0; 1603 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1604 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1605 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1606 } request; 1607 struct { 1608 uint32_t word0; 1609 } response; 1610 } u; 1611 }; 1612 1613 struct mq_context { 1614 uint32_t word0; 1615 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1616 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1617 #define lpfc_mq_context_cq_id_WORD word0 1618 #define lpfc_mq_context_ring_size_SHIFT 16 1619 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1620 #define lpfc_mq_context_ring_size_WORD word0 1621 #define LPFC_MQ_RING_SIZE_16 0x5 1622 #define LPFC_MQ_RING_SIZE_32 0x6 1623 #define LPFC_MQ_RING_SIZE_64 0x7 1624 #define LPFC_MQ_RING_SIZE_128 0x8 1625 uint32_t word1; 1626 #define lpfc_mq_context_valid_SHIFT 31 1627 #define lpfc_mq_context_valid_MASK 0x00000001 1628 #define lpfc_mq_context_valid_WORD word1 1629 uint32_t reserved2; 1630 uint32_t reserved3; 1631 }; 1632 1633 struct lpfc_mbx_mq_create { 1634 struct mbox_header header; 1635 union { 1636 struct { 1637 uint32_t word0; 1638 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1639 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1640 #define lpfc_mbx_mq_create_num_pages_WORD word0 1641 struct mq_context context; 1642 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1643 } request; 1644 struct { 1645 uint32_t word0; 1646 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1647 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1648 #define lpfc_mbx_mq_create_q_id_WORD word0 1649 } response; 1650 } u; 1651 }; 1652 1653 struct lpfc_mbx_mq_create_ext { 1654 struct mbox_header header; 1655 union { 1656 struct { 1657 uint32_t word0; 1658 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1659 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1660 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1661 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1662 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1663 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1664 uint32_t async_evt_bmap; 1665 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1666 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1667 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1668 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1669 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1670 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1671 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1672 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1673 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1674 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1675 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1676 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1677 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1678 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1679 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1680 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1681 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1682 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1683 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1684 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1685 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1686 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1687 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1688 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1689 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1690 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1691 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1692 struct mq_context context; 1693 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1694 } request; 1695 struct { 1696 uint32_t word0; 1697 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1698 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1699 #define lpfc_mbx_mq_create_q_id_WORD word0 1700 } response; 1701 } u; 1702 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1703 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1704 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1705 }; 1706 1707 struct lpfc_mbx_mq_destroy { 1708 struct mbox_header header; 1709 union { 1710 struct { 1711 uint32_t word0; 1712 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1713 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1714 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1715 } request; 1716 struct { 1717 uint32_t word0; 1718 } response; 1719 } u; 1720 }; 1721 1722 /* Start Gen 2 SLI4 Mailbox definitions: */ 1723 1724 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1725 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1726 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1727 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1728 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1729 1730 struct lpfc_mbx_get_rsrc_extent_info { 1731 struct mbox_header header; 1732 union { 1733 struct { 1734 uint32_t word4; 1735 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1736 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1737 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1738 } req; 1739 struct { 1740 uint32_t word4; 1741 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1742 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1743 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1744 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1745 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1746 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1747 } rsp; 1748 } u; 1749 }; 1750 1751 struct lpfc_mbx_query_fw_config { 1752 struct mbox_header header; 1753 struct { 1754 uint32_t config_number; 1755 #define LPFC_FC_FCOE 0x00000007 1756 uint32_t asic_revision; 1757 uint32_t physical_port; 1758 uint32_t function_mode; 1759 #define LPFC_FCOE_INI_MODE 0x00000040 1760 #define LPFC_FCOE_TGT_MODE 0x00000080 1761 #define LPFC_DUA_MODE 0x00000800 1762 uint32_t ulp0_mode; 1763 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1764 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1765 uint32_t ulp0_nap_words[12]; 1766 uint32_t ulp1_mode; 1767 uint32_t ulp1_nap_words[12]; 1768 uint32_t function_capabilities; 1769 uint32_t cqid_base; 1770 uint32_t cqid_tot; 1771 uint32_t eqid_base; 1772 uint32_t eqid_tot; 1773 uint32_t ulp0_nap2_words[2]; 1774 uint32_t ulp1_nap2_words[2]; 1775 } rsp; 1776 }; 1777 1778 struct lpfc_mbx_set_beacon_config { 1779 struct mbox_header header; 1780 uint32_t word4; 1781 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1782 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1783 #define lpfc_mbx_set_beacon_port_num_WORD word4 1784 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1785 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1786 #define lpfc_mbx_set_beacon_port_type_WORD word4 1787 #define lpfc_mbx_set_beacon_state_SHIFT 8 1788 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1789 #define lpfc_mbx_set_beacon_state_WORD word4 1790 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1791 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1792 #define lpfc_mbx_set_beacon_duration_WORD word4 1793 1794 /* COMMON_SET_BEACON_CONFIG_V1 */ 1795 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1796 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1797 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1798 uint32_t word5; /* RESERVED */ 1799 }; 1800 1801 struct lpfc_id_range { 1802 uint32_t word5; 1803 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1804 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1805 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1806 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1807 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1808 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1809 }; 1810 1811 struct lpfc_mbx_set_link_diag_state { 1812 struct mbox_header header; 1813 union { 1814 struct { 1815 uint32_t word0; 1816 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1817 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1818 #define lpfc_mbx_set_diag_state_diag_WORD word0 1819 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1820 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1821 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1822 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1823 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1824 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1825 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1826 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1827 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1828 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1829 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1830 } req; 1831 struct { 1832 uint32_t word0; 1833 } rsp; 1834 } u; 1835 }; 1836 1837 struct lpfc_mbx_set_link_diag_loopback { 1838 struct mbox_header header; 1839 union { 1840 struct { 1841 uint32_t word0; 1842 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1843 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1844 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1845 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1846 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1847 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1848 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1849 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1850 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1851 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1852 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1853 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1854 } req; 1855 struct { 1856 uint32_t word0; 1857 } rsp; 1858 } u; 1859 }; 1860 1861 struct lpfc_mbx_run_link_diag_test { 1862 struct mbox_header header; 1863 union { 1864 struct { 1865 uint32_t word0; 1866 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1867 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1868 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1869 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1870 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1871 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1872 uint32_t word1; 1873 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1874 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1875 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1876 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1877 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1878 #define lpfc_mbx_run_diag_test_loops_WORD word1 1879 uint32_t word2; 1880 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1881 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1882 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1883 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1884 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1885 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1886 } req; 1887 struct { 1888 uint32_t word0; 1889 } rsp; 1890 } u; 1891 }; 1892 1893 /* 1894 * struct lpfc_mbx_alloc_rsrc_extents: 1895 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1896 * 6 words of header + 4 words of shared subcommand header + 1897 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1898 * 1899 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1900 * for extents payload. 1901 * 1902 * 212/2 (bytes per extent) = 106 extents. 1903 * 106/2 (extents per word) = 53 words. 1904 * lpfc_id_range id is statically size to 53. 1905 * 1906 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1907 * extent ranges. For ALLOC, the type and cnt are required. 1908 * For GET_ALLOCATED, only the type is required. 1909 */ 1910 struct lpfc_mbx_alloc_rsrc_extents { 1911 struct mbox_header header; 1912 union { 1913 struct { 1914 uint32_t word4; 1915 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1916 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1917 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1918 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1919 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1920 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1921 } req; 1922 struct { 1923 uint32_t word4; 1924 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1925 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1926 #define lpfc_mbx_rsrc_cnt_WORD word4 1927 struct lpfc_id_range id[53]; 1928 } rsp; 1929 } u; 1930 }; 1931 1932 /* 1933 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1934 * structure shares the same SHIFT/MASK/WORD defines provided in the 1935 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1936 * the structures defined above. This non-embedded structure provides for the 1937 * maximum number of extents supported by the port. 1938 */ 1939 struct lpfc_mbx_nembed_rsrc_extent { 1940 union lpfc_sli4_cfg_shdr cfg_shdr; 1941 uint32_t word4; 1942 struct lpfc_id_range id; 1943 }; 1944 1945 struct lpfc_mbx_dealloc_rsrc_extents { 1946 struct mbox_header header; 1947 struct { 1948 uint32_t word4; 1949 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1950 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1951 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1952 } req; 1953 1954 }; 1955 1956 /* Start SLI4 FCoE specific mbox structures. */ 1957 1958 struct lpfc_mbx_post_hdr_tmpl { 1959 struct mbox_header header; 1960 uint32_t word10; 1961 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1962 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1963 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1964 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1965 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1966 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1967 uint32_t rpi_paddr_lo; 1968 uint32_t rpi_paddr_hi; 1969 }; 1970 1971 struct sli4_sge { /* SLI-4 */ 1972 uint32_t addr_hi; 1973 uint32_t addr_lo; 1974 1975 uint32_t word2; 1976 #define lpfc_sli4_sge_offset_SHIFT 0 1977 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1978 #define lpfc_sli4_sge_offset_WORD word2 1979 #define lpfc_sli4_sge_type_SHIFT 27 1980 #define lpfc_sli4_sge_type_MASK 0x0000000F 1981 #define lpfc_sli4_sge_type_WORD word2 1982 #define LPFC_SGE_TYPE_DATA 0x0 1983 #define LPFC_SGE_TYPE_DIF 0x4 1984 #define LPFC_SGE_TYPE_LSP 0x5 1985 #define LPFC_SGE_TYPE_PEDIF 0x6 1986 #define LPFC_SGE_TYPE_PESEED 0x7 1987 #define LPFC_SGE_TYPE_DISEED 0x8 1988 #define LPFC_SGE_TYPE_ENC 0x9 1989 #define LPFC_SGE_TYPE_ATM 0xA 1990 #define LPFC_SGE_TYPE_SKIP 0xC 1991 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1992 #define lpfc_sli4_sge_last_MASK 0x00000001 1993 #define lpfc_sli4_sge_last_WORD word2 1994 uint32_t sge_len; 1995 }; 1996 1997 struct sli4_sge_diseed { /* SLI-4 */ 1998 uint32_t ref_tag; 1999 uint32_t ref_tag_tran; 2000 2001 uint32_t word2; 2002 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2003 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2004 #define lpfc_sli4_sge_dif_apptran_WORD word2 2005 #define lpfc_sli4_sge_dif_af_SHIFT 24 2006 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2007 #define lpfc_sli4_sge_dif_af_WORD word2 2008 #define lpfc_sli4_sge_dif_na_SHIFT 25 2009 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2010 #define lpfc_sli4_sge_dif_na_WORD word2 2011 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2012 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2013 #define lpfc_sli4_sge_dif_hi_WORD word2 2014 #define lpfc_sli4_sge_dif_type_SHIFT 27 2015 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2016 #define lpfc_sli4_sge_dif_type_WORD word2 2017 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2018 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2019 #define lpfc_sli4_sge_dif_last_WORD word2 2020 uint32_t word3; 2021 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2022 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2023 #define lpfc_sli4_sge_dif_apptag_WORD word3 2024 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2025 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2026 #define lpfc_sli4_sge_dif_bs_WORD word3 2027 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2028 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2029 #define lpfc_sli4_sge_dif_ai_WORD word3 2030 #define lpfc_sli4_sge_dif_me_SHIFT 20 2031 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2032 #define lpfc_sli4_sge_dif_me_WORD word3 2033 #define lpfc_sli4_sge_dif_re_SHIFT 21 2034 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2035 #define lpfc_sli4_sge_dif_re_WORD word3 2036 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2037 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2038 #define lpfc_sli4_sge_dif_ce_WORD word3 2039 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2040 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2041 #define lpfc_sli4_sge_dif_nr_WORD word3 2042 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2043 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2044 #define lpfc_sli4_sge_dif_oprx_WORD word3 2045 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2046 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2047 #define lpfc_sli4_sge_dif_optx_WORD word3 2048 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2049 }; 2050 2051 struct fcf_record { 2052 uint32_t max_rcv_size; 2053 uint32_t fka_adv_period; 2054 uint32_t fip_priority; 2055 uint32_t word3; 2056 #define lpfc_fcf_record_mac_0_SHIFT 0 2057 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2058 #define lpfc_fcf_record_mac_0_WORD word3 2059 #define lpfc_fcf_record_mac_1_SHIFT 8 2060 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2061 #define lpfc_fcf_record_mac_1_WORD word3 2062 #define lpfc_fcf_record_mac_2_SHIFT 16 2063 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2064 #define lpfc_fcf_record_mac_2_WORD word3 2065 #define lpfc_fcf_record_mac_3_SHIFT 24 2066 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2067 #define lpfc_fcf_record_mac_3_WORD word3 2068 uint32_t word4; 2069 #define lpfc_fcf_record_mac_4_SHIFT 0 2070 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2071 #define lpfc_fcf_record_mac_4_WORD word4 2072 #define lpfc_fcf_record_mac_5_SHIFT 8 2073 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2074 #define lpfc_fcf_record_mac_5_WORD word4 2075 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2076 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2077 #define lpfc_fcf_record_fcf_avail_WORD word4 2078 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2079 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2080 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2081 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2082 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2083 uint32_t word5; 2084 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2085 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2086 #define lpfc_fcf_record_fab_name_0_WORD word5 2087 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2088 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2089 #define lpfc_fcf_record_fab_name_1_WORD word5 2090 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2091 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2092 #define lpfc_fcf_record_fab_name_2_WORD word5 2093 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2094 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2095 #define lpfc_fcf_record_fab_name_3_WORD word5 2096 uint32_t word6; 2097 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2098 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2099 #define lpfc_fcf_record_fab_name_4_WORD word6 2100 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2101 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2102 #define lpfc_fcf_record_fab_name_5_WORD word6 2103 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2104 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2105 #define lpfc_fcf_record_fab_name_6_WORD word6 2106 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2107 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2108 #define lpfc_fcf_record_fab_name_7_WORD word6 2109 uint32_t word7; 2110 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2111 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2112 #define lpfc_fcf_record_fc_map_0_WORD word7 2113 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2114 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2115 #define lpfc_fcf_record_fc_map_1_WORD word7 2116 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2117 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2118 #define lpfc_fcf_record_fc_map_2_WORD word7 2119 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2120 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2121 #define lpfc_fcf_record_fcf_valid_WORD word7 2122 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2123 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2124 #define lpfc_fcf_record_fcf_fc_WORD word7 2125 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2126 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2127 #define lpfc_fcf_record_fcf_sol_WORD word7 2128 uint32_t word8; 2129 #define lpfc_fcf_record_fcf_index_SHIFT 0 2130 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2131 #define lpfc_fcf_record_fcf_index_WORD word8 2132 #define lpfc_fcf_record_fcf_state_SHIFT 16 2133 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2134 #define lpfc_fcf_record_fcf_state_WORD word8 2135 uint8_t vlan_bitmap[512]; 2136 uint32_t word137; 2137 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2138 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2139 #define lpfc_fcf_record_switch_name_0_WORD word137 2140 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2141 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2142 #define lpfc_fcf_record_switch_name_1_WORD word137 2143 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2144 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2145 #define lpfc_fcf_record_switch_name_2_WORD word137 2146 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2147 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2148 #define lpfc_fcf_record_switch_name_3_WORD word137 2149 uint32_t word138; 2150 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2151 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2152 #define lpfc_fcf_record_switch_name_4_WORD word138 2153 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2154 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2155 #define lpfc_fcf_record_switch_name_5_WORD word138 2156 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2157 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2158 #define lpfc_fcf_record_switch_name_6_WORD word138 2159 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2160 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2161 #define lpfc_fcf_record_switch_name_7_WORD word138 2162 }; 2163 2164 struct lpfc_mbx_read_fcf_tbl { 2165 union lpfc_sli4_cfg_shdr cfg_shdr; 2166 union { 2167 struct { 2168 uint32_t word10; 2169 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2170 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2171 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2172 } request; 2173 struct { 2174 uint32_t eventag; 2175 } response; 2176 } u; 2177 uint32_t word11; 2178 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2179 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2180 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2181 }; 2182 2183 struct lpfc_mbx_add_fcf_tbl_entry { 2184 union lpfc_sli4_cfg_shdr cfg_shdr; 2185 uint32_t word10; 2186 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2187 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2188 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2189 struct lpfc_mbx_sge fcf_sge; 2190 }; 2191 2192 struct lpfc_mbx_del_fcf_tbl_entry { 2193 struct mbox_header header; 2194 uint32_t word10; 2195 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2196 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2197 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2198 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2199 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2200 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2201 }; 2202 2203 struct lpfc_mbx_redisc_fcf_tbl { 2204 struct mbox_header header; 2205 uint32_t word10; 2206 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2207 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2208 #define lpfc_mbx_redisc_fcf_count_WORD word10 2209 uint32_t resvd; 2210 uint32_t word12; 2211 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2212 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2213 #define lpfc_mbx_redisc_fcf_index_WORD word12 2214 }; 2215 2216 /* Status field for embedded SLI_CONFIG mailbox command */ 2217 #define STATUS_SUCCESS 0x0 2218 #define STATUS_FAILED 0x1 2219 #define STATUS_ILLEGAL_REQUEST 0x2 2220 #define STATUS_ILLEGAL_FIELD 0x3 2221 #define STATUS_INSUFFICIENT_BUFFER 0x4 2222 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2223 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2224 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2225 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2226 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2227 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2228 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2229 #define STATUS_ASSERT_FAILED 0x1e 2230 #define STATUS_INVALID_SESSION 0x1f 2231 #define STATUS_INVALID_CONNECTION 0x20 2232 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2233 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2234 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2235 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2236 #define STATUS_FLASHROM_READ_FAILED 0x27 2237 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2238 #define STATUS_ERROR_ACITMAIN 0x2a 2239 #define STATUS_REBOOT_REQUIRED 0x2c 2240 #define STATUS_FCF_IN_USE 0x3a 2241 #define STATUS_FCF_TABLE_EMPTY 0x43 2242 2243 /* 2244 * Additional status field for embedded SLI_CONFIG mailbox 2245 * command. 2246 */ 2247 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2248 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2249 #define ADD_STATUS_INVALID_REQUEST 0x4B 2250 2251 struct lpfc_mbx_sli4_config { 2252 struct mbox_header header; 2253 }; 2254 2255 struct lpfc_mbx_init_vfi { 2256 uint32_t word1; 2257 #define lpfc_init_vfi_vr_SHIFT 31 2258 #define lpfc_init_vfi_vr_MASK 0x00000001 2259 #define lpfc_init_vfi_vr_WORD word1 2260 #define lpfc_init_vfi_vt_SHIFT 30 2261 #define lpfc_init_vfi_vt_MASK 0x00000001 2262 #define lpfc_init_vfi_vt_WORD word1 2263 #define lpfc_init_vfi_vf_SHIFT 29 2264 #define lpfc_init_vfi_vf_MASK 0x00000001 2265 #define lpfc_init_vfi_vf_WORD word1 2266 #define lpfc_init_vfi_vp_SHIFT 28 2267 #define lpfc_init_vfi_vp_MASK 0x00000001 2268 #define lpfc_init_vfi_vp_WORD word1 2269 #define lpfc_init_vfi_vfi_SHIFT 0 2270 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2271 #define lpfc_init_vfi_vfi_WORD word1 2272 uint32_t word2; 2273 #define lpfc_init_vfi_vpi_SHIFT 16 2274 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2275 #define lpfc_init_vfi_vpi_WORD word2 2276 #define lpfc_init_vfi_fcfi_SHIFT 0 2277 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2278 #define lpfc_init_vfi_fcfi_WORD word2 2279 uint32_t word3; 2280 #define lpfc_init_vfi_pri_SHIFT 13 2281 #define lpfc_init_vfi_pri_MASK 0x00000007 2282 #define lpfc_init_vfi_pri_WORD word3 2283 #define lpfc_init_vfi_vf_id_SHIFT 1 2284 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2285 #define lpfc_init_vfi_vf_id_WORD word3 2286 uint32_t word4; 2287 #define lpfc_init_vfi_hop_count_SHIFT 24 2288 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2289 #define lpfc_init_vfi_hop_count_WORD word4 2290 }; 2291 #define MBX_VFI_IN_USE 0x9F02 2292 2293 2294 struct lpfc_mbx_reg_vfi { 2295 uint32_t word1; 2296 #define lpfc_reg_vfi_upd_SHIFT 29 2297 #define lpfc_reg_vfi_upd_MASK 0x00000001 2298 #define lpfc_reg_vfi_upd_WORD word1 2299 #define lpfc_reg_vfi_vp_SHIFT 28 2300 #define lpfc_reg_vfi_vp_MASK 0x00000001 2301 #define lpfc_reg_vfi_vp_WORD word1 2302 #define lpfc_reg_vfi_vfi_SHIFT 0 2303 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2304 #define lpfc_reg_vfi_vfi_WORD word1 2305 uint32_t word2; 2306 #define lpfc_reg_vfi_vpi_SHIFT 16 2307 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2308 #define lpfc_reg_vfi_vpi_WORD word2 2309 #define lpfc_reg_vfi_fcfi_SHIFT 0 2310 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2311 #define lpfc_reg_vfi_fcfi_WORD word2 2312 uint32_t wwn[2]; 2313 struct ulp_bde64 bde; 2314 uint32_t e_d_tov; 2315 uint32_t r_a_tov; 2316 uint32_t word10; 2317 #define lpfc_reg_vfi_nport_id_SHIFT 0 2318 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2319 #define lpfc_reg_vfi_nport_id_WORD word10 2320 #define lpfc_reg_vfi_bbcr_SHIFT 27 2321 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2322 #define lpfc_reg_vfi_bbcr_WORD word10 2323 #define lpfc_reg_vfi_bbscn_SHIFT 28 2324 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2325 #define lpfc_reg_vfi_bbscn_WORD word10 2326 }; 2327 2328 struct lpfc_mbx_init_vpi { 2329 uint32_t word1; 2330 #define lpfc_init_vpi_vfi_SHIFT 16 2331 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2332 #define lpfc_init_vpi_vfi_WORD word1 2333 #define lpfc_init_vpi_vpi_SHIFT 0 2334 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2335 #define lpfc_init_vpi_vpi_WORD word1 2336 }; 2337 2338 struct lpfc_mbx_read_vpi { 2339 uint32_t word1_rsvd; 2340 uint32_t word2; 2341 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2342 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2343 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2344 uint32_t word3_rsvd; 2345 uint32_t word4; 2346 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2347 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2348 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2349 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2350 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2351 #define lpfc_mbx_read_vpi_pb_WORD word4 2352 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2353 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2354 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2355 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2356 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2357 #define lpfc_mbx_read_vpi_ns_WORD word4 2358 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2359 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2360 #define lpfc_mbx_read_vpi_hl_WORD word4 2361 uint32_t word5_rsvd; 2362 uint32_t word6; 2363 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2364 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2365 #define lpfc_mbx_read_vpi_vpi_WORD word6 2366 uint32_t word7; 2367 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2368 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2369 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2370 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2371 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2372 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2373 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2374 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2375 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2376 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2377 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2378 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2379 uint32_t word8; 2380 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2381 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2382 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2383 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2384 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2385 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2386 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2387 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2388 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2389 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2390 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2391 #define lpfc_mbx_read_vpi_vv_WORD word8 2392 }; 2393 2394 struct lpfc_mbx_unreg_vfi { 2395 uint32_t word1_rsvd; 2396 uint32_t word2; 2397 #define lpfc_unreg_vfi_vfi_SHIFT 0 2398 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2399 #define lpfc_unreg_vfi_vfi_WORD word2 2400 }; 2401 2402 struct lpfc_mbx_resume_rpi { 2403 uint32_t word1; 2404 #define lpfc_resume_rpi_index_SHIFT 0 2405 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2406 #define lpfc_resume_rpi_index_WORD word1 2407 #define lpfc_resume_rpi_ii_SHIFT 30 2408 #define lpfc_resume_rpi_ii_MASK 0x00000003 2409 #define lpfc_resume_rpi_ii_WORD word1 2410 #define RESUME_INDEX_RPI 0 2411 #define RESUME_INDEX_VPI 1 2412 #define RESUME_INDEX_VFI 2 2413 #define RESUME_INDEX_FCFI 3 2414 uint32_t event_tag; 2415 }; 2416 2417 #define REG_FCF_INVALID_QID 0xFFFF 2418 struct lpfc_mbx_reg_fcfi { 2419 uint32_t word1; 2420 #define lpfc_reg_fcfi_info_index_SHIFT 0 2421 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2422 #define lpfc_reg_fcfi_info_index_WORD word1 2423 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2424 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2425 #define lpfc_reg_fcfi_fcfi_WORD word1 2426 uint32_t word2; 2427 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2428 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2429 #define lpfc_reg_fcfi_rq_id1_WORD word2 2430 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2431 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2432 #define lpfc_reg_fcfi_rq_id0_WORD word2 2433 uint32_t word3; 2434 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2435 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2436 #define lpfc_reg_fcfi_rq_id3_WORD word3 2437 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2438 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2439 #define lpfc_reg_fcfi_rq_id2_WORD word3 2440 uint32_t word4; 2441 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2442 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2443 #define lpfc_reg_fcfi_type_match0_WORD word4 2444 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2445 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2446 #define lpfc_reg_fcfi_type_mask0_WORD word4 2447 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2448 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2449 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2450 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2451 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2452 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2453 uint32_t word5; 2454 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2455 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2456 #define lpfc_reg_fcfi_type_match1_WORD word5 2457 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2458 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2459 #define lpfc_reg_fcfi_type_mask1_WORD word5 2460 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2461 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2462 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2463 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2464 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2465 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2466 uint32_t word6; 2467 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2468 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2469 #define lpfc_reg_fcfi_type_match2_WORD word6 2470 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2471 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2472 #define lpfc_reg_fcfi_type_mask2_WORD word6 2473 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2474 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2475 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2476 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2477 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2478 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2479 uint32_t word7; 2480 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2481 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2482 #define lpfc_reg_fcfi_type_match3_WORD word7 2483 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2484 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2485 #define lpfc_reg_fcfi_type_mask3_WORD word7 2486 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2487 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2488 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2489 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2490 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2491 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2492 uint32_t word8; 2493 #define lpfc_reg_fcfi_mam_SHIFT 13 2494 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2495 #define lpfc_reg_fcfi_mam_WORD word8 2496 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2497 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2498 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2499 #define lpfc_reg_fcfi_vv_SHIFT 12 2500 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2501 #define lpfc_reg_fcfi_vv_WORD word8 2502 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2503 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2504 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2505 }; 2506 2507 struct lpfc_mbx_reg_fcfi_mrq { 2508 uint32_t word1; 2509 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2510 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2511 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2512 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2513 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2514 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2515 uint32_t word2; 2516 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2517 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2518 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2519 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2520 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2521 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2522 uint32_t word3; 2523 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2524 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2525 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2526 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2527 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2528 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2529 uint32_t word4; 2530 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2531 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2532 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2533 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2534 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2535 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2536 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2537 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2538 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2539 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2540 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2541 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2542 uint32_t word5; 2543 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2544 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2545 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2546 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2547 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2548 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2549 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2550 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2551 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2552 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2553 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2554 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2555 uint32_t word6; 2556 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2557 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2558 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2559 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2560 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2561 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2562 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2563 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2564 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2565 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2566 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2567 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2568 uint32_t word7; 2569 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2570 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2571 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2572 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2573 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2574 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2575 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2576 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2577 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2578 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2579 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2580 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2581 uint32_t word8; 2582 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2583 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2584 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2585 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2586 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2587 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2588 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2589 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2590 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2591 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2592 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2593 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2594 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2595 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2596 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2597 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2598 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2599 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2600 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2601 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2602 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2603 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2604 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2605 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2606 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2607 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2608 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2609 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2610 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2611 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2612 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2613 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2614 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2615 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2616 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2617 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2618 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2619 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2620 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2621 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2622 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2623 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2624 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2625 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2626 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2627 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2628 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2629 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2630 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2631 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2632 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2633 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2634 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2635 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2636 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2637 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2638 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2639 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2640 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2641 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2642 uint32_t word9; 2643 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2644 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2645 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2646 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2647 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2648 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2649 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2650 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2651 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2652 uint32_t word10; 2653 uint32_t word11; 2654 uint32_t word12; 2655 uint32_t word13; 2656 uint32_t word14; 2657 uint32_t word15; 2658 uint32_t word16; 2659 }; 2660 2661 struct lpfc_mbx_unreg_fcfi { 2662 uint32_t word1_rsv; 2663 uint32_t word2; 2664 #define lpfc_unreg_fcfi_SHIFT 0 2665 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2666 #define lpfc_unreg_fcfi_WORD word2 2667 }; 2668 2669 struct lpfc_mbx_read_rev { 2670 uint32_t word1; 2671 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2672 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2673 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2674 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2675 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2676 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2677 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2678 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2679 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2680 #define LPFC_PREDCBX_CEE_MODE 0 2681 #define LPFC_DCBX_CEE_MODE 1 2682 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2683 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2684 #define lpfc_mbx_rd_rev_vpd_WORD word1 2685 uint32_t first_hw_rev; 2686 #define LPFC_G7_ASIC_1 0xd 2687 uint32_t second_hw_rev; 2688 uint32_t word4_rsvd; 2689 uint32_t third_hw_rev; 2690 uint32_t word6; 2691 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2692 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2693 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2694 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2695 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2696 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2697 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2698 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2699 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2700 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2701 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2702 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2703 uint32_t word7_rsvd; 2704 uint32_t fw_id_rev; 2705 uint8_t fw_name[16]; 2706 uint32_t ulp_fw_id_rev; 2707 uint8_t ulp_fw_name[16]; 2708 uint32_t word18_47_rsvd[30]; 2709 uint32_t word48; 2710 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2711 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2712 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2713 uint32_t vpd_paddr_low; 2714 uint32_t vpd_paddr_high; 2715 uint32_t avail_vpd_len; 2716 uint32_t rsvd_52_63[12]; 2717 }; 2718 2719 struct lpfc_mbx_read_config { 2720 uint32_t word1; 2721 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2722 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2723 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2724 uint32_t word2; 2725 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2726 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2727 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2728 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2729 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2730 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2731 #define LPFC_LNK_TYPE_GE 0 2732 #define LPFC_LNK_TYPE_FC 1 2733 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2734 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2735 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2736 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2737 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2738 #define lpfc_mbx_rd_conf_topology_WORD word2 2739 uint32_t rsvd_3; 2740 uint32_t word4; 2741 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2742 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2743 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2744 uint32_t rsvd_5; 2745 uint32_t word6; 2746 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2747 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2748 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2749 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2750 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2751 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2752 uint32_t rsvd_7; 2753 uint32_t word8; 2754 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2755 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2756 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2757 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2758 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2759 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2760 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2761 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2762 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2763 uint32_t word9; 2764 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2765 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2766 #define lpfc_mbx_rd_conf_lmt_WORD word9 2767 uint32_t rsvd_10; 2768 uint32_t rsvd_11; 2769 uint32_t word12; 2770 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2771 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2772 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2773 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2774 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2775 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2776 uint32_t word13; 2777 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2778 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2779 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2780 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2781 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2782 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2783 uint32_t word14; 2784 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2785 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2786 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2787 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2788 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2789 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2790 uint32_t word15; 2791 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2792 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2793 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2794 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2795 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2796 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2797 uint32_t word16; 2798 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2799 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2800 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2801 uint32_t word17; 2802 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2803 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2804 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2805 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2806 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2807 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2808 uint32_t word18; 2809 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2810 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2811 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2812 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2813 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2814 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2815 }; 2816 2817 struct lpfc_mbx_request_features { 2818 uint32_t word1; 2819 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2820 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2821 #define lpfc_mbx_rq_ftr_qry_WORD word1 2822 uint32_t word2; 2823 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2824 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2825 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2826 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2827 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2828 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2829 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2830 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2831 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2832 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2833 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2834 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2835 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2836 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2837 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2838 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2839 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2840 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2841 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2842 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2843 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2844 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2845 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2846 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2847 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2848 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2849 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2850 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2851 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2852 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2853 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2854 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2855 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2856 uint32_t word3; 2857 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2858 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2859 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2860 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2861 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2862 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2863 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2864 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2865 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2866 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2867 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2868 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2869 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2870 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2871 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2872 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2873 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2874 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2875 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2876 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2877 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2878 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2879 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2880 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2881 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2882 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2883 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2884 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2885 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2886 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2887 }; 2888 2889 struct lpfc_mbx_supp_pages { 2890 uint32_t word1; 2891 #define qs_SHIFT 0 2892 #define qs_MASK 0x00000001 2893 #define qs_WORD word1 2894 #define wr_SHIFT 1 2895 #define wr_MASK 0x00000001 2896 #define wr_WORD word1 2897 #define pf_SHIFT 8 2898 #define pf_MASK 0x000000ff 2899 #define pf_WORD word1 2900 #define cpn_SHIFT 16 2901 #define cpn_MASK 0x000000ff 2902 #define cpn_WORD word1 2903 uint32_t word2; 2904 #define list_offset_SHIFT 0 2905 #define list_offset_MASK 0x000000ff 2906 #define list_offset_WORD word2 2907 #define next_offset_SHIFT 8 2908 #define next_offset_MASK 0x000000ff 2909 #define next_offset_WORD word2 2910 #define elem_cnt_SHIFT 16 2911 #define elem_cnt_MASK 0x000000ff 2912 #define elem_cnt_WORD word2 2913 uint32_t word3; 2914 #define pn_0_SHIFT 24 2915 #define pn_0_MASK 0x000000ff 2916 #define pn_0_WORD word3 2917 #define pn_1_SHIFT 16 2918 #define pn_1_MASK 0x000000ff 2919 #define pn_1_WORD word3 2920 #define pn_2_SHIFT 8 2921 #define pn_2_MASK 0x000000ff 2922 #define pn_2_WORD word3 2923 #define pn_3_SHIFT 0 2924 #define pn_3_MASK 0x000000ff 2925 #define pn_3_WORD word3 2926 uint32_t word4; 2927 #define pn_4_SHIFT 24 2928 #define pn_4_MASK 0x000000ff 2929 #define pn_4_WORD word4 2930 #define pn_5_SHIFT 16 2931 #define pn_5_MASK 0x000000ff 2932 #define pn_5_WORD word4 2933 #define pn_6_SHIFT 8 2934 #define pn_6_MASK 0x000000ff 2935 #define pn_6_WORD word4 2936 #define pn_7_SHIFT 0 2937 #define pn_7_MASK 0x000000ff 2938 #define pn_7_WORD word4 2939 uint32_t rsvd[27]; 2940 #define LPFC_SUPP_PAGES 0 2941 #define LPFC_BLOCK_GUARD_PROFILES 1 2942 #define LPFC_SLI4_PARAMETERS 2 2943 }; 2944 2945 struct lpfc_mbx_memory_dump_type3 { 2946 uint32_t word1; 2947 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2948 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2949 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2950 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2951 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2952 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2953 uint32_t word2; 2954 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2955 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 2956 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 2957 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 2958 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 2959 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 2960 uint32_t word3; 2961 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 2962 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 2963 #define lpfc_mbx_memory_dump_type3_length_WORD word3 2964 uint32_t addr_lo; 2965 uint32_t addr_hi; 2966 uint32_t return_len; 2967 }; 2968 2969 #define DMP_PAGE_A0 0xa0 2970 #define DMP_PAGE_A2 0xa2 2971 #define DMP_SFF_PAGE_A0_SIZE 256 2972 #define DMP_SFF_PAGE_A2_SIZE 256 2973 2974 #define SFP_WAVELENGTH_LC1310 1310 2975 #define SFP_WAVELENGTH_LL1550 1550 2976 2977 2978 /* 2979 * * SFF-8472 TABLE 3.4 2980 * */ 2981 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 2982 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 2983 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 2984 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 2985 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 2986 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 2987 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 2988 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 2989 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 2990 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 2991 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 2992 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 2993 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 2994 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 2995 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 2996 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 2997 2998 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 2999 3000 #define SSF_IDENTIFIER 0 3001 #define SSF_EXT_IDENTIFIER 1 3002 #define SSF_CONNECTOR 2 3003 #define SSF_TRANSCEIVER_CODE_B0 3 3004 #define SSF_TRANSCEIVER_CODE_B1 4 3005 #define SSF_TRANSCEIVER_CODE_B2 5 3006 #define SSF_TRANSCEIVER_CODE_B3 6 3007 #define SSF_TRANSCEIVER_CODE_B4 7 3008 #define SSF_TRANSCEIVER_CODE_B5 8 3009 #define SSF_TRANSCEIVER_CODE_B6 9 3010 #define SSF_TRANSCEIVER_CODE_B7 10 3011 #define SSF_ENCODING 11 3012 #define SSF_BR_NOMINAL 12 3013 #define SSF_RATE_IDENTIFIER 13 3014 #define SSF_LENGTH_9UM_KM 14 3015 #define SSF_LENGTH_9UM 15 3016 #define SSF_LENGTH_50UM_OM2 16 3017 #define SSF_LENGTH_62UM_OM1 17 3018 #define SFF_LENGTH_COPPER 18 3019 #define SSF_LENGTH_50UM_OM3 19 3020 #define SSF_VENDOR_NAME 20 3021 #define SSF_VENDOR_OUI 36 3022 #define SSF_VENDOR_PN 40 3023 #define SSF_VENDOR_REV 56 3024 #define SSF_WAVELENGTH_B1 60 3025 #define SSF_WAVELENGTH_B0 61 3026 #define SSF_CC_BASE 63 3027 #define SSF_OPTIONS_B1 64 3028 #define SSF_OPTIONS_B0 65 3029 #define SSF_BR_MAX 66 3030 #define SSF_BR_MIN 67 3031 #define SSF_VENDOR_SN 68 3032 #define SSF_DATE_CODE 84 3033 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3034 #define SSF_ENHANCED_OPTIONS 93 3035 #define SFF_8472_COMPLIANCE 94 3036 #define SSF_CC_EXT 95 3037 #define SSF_A0_VENDOR_SPECIFIC 96 3038 3039 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3040 3041 #define SSF_TEMP_HIGH_ALARM 0 3042 #define SSF_TEMP_LOW_ALARM 2 3043 #define SSF_TEMP_HIGH_WARNING 4 3044 #define SSF_TEMP_LOW_WARNING 6 3045 #define SSF_VOLTAGE_HIGH_ALARM 8 3046 #define SSF_VOLTAGE_LOW_ALARM 10 3047 #define SSF_VOLTAGE_HIGH_WARNING 12 3048 #define SSF_VOLTAGE_LOW_WARNING 14 3049 #define SSF_BIAS_HIGH_ALARM 16 3050 #define SSF_BIAS_LOW_ALARM 18 3051 #define SSF_BIAS_HIGH_WARNING 20 3052 #define SSF_BIAS_LOW_WARNING 22 3053 #define SSF_TXPOWER_HIGH_ALARM 24 3054 #define SSF_TXPOWER_LOW_ALARM 26 3055 #define SSF_TXPOWER_HIGH_WARNING 28 3056 #define SSF_TXPOWER_LOW_WARNING 30 3057 #define SSF_RXPOWER_HIGH_ALARM 32 3058 #define SSF_RXPOWER_LOW_ALARM 34 3059 #define SSF_RXPOWER_HIGH_WARNING 36 3060 #define SSF_RXPOWER_LOW_WARNING 38 3061 #define SSF_EXT_CAL_CONSTANTS 56 3062 #define SSF_CC_DMI 95 3063 #define SFF_TEMPERATURE_B1 96 3064 #define SFF_TEMPERATURE_B0 97 3065 #define SFF_VCC_B1 98 3066 #define SFF_VCC_B0 99 3067 #define SFF_TX_BIAS_CURRENT_B1 100 3068 #define SFF_TX_BIAS_CURRENT_B0 101 3069 #define SFF_TXPOWER_B1 102 3070 #define SFF_TXPOWER_B0 103 3071 #define SFF_RXPOWER_B1 104 3072 #define SFF_RXPOWER_B0 105 3073 #define SSF_STATUS_CONTROL 110 3074 #define SSF_ALARM_FLAGS 112 3075 #define SSF_WARNING_FLAGS 116 3076 #define SSF_EXT_TATUS_CONTROL_B1 118 3077 #define SSF_EXT_TATUS_CONTROL_B0 119 3078 #define SSF_A2_VENDOR_SPECIFIC 120 3079 #define SSF_USER_EEPROM 128 3080 #define SSF_VENDOR_CONTROL 148 3081 3082 3083 /* 3084 * Tranceiver codes Fibre Channel SFF-8472 3085 * Table 3.5. 3086 */ 3087 3088 struct sff_trasnceiver_codes_byte0 { 3089 uint8_t inifiband:4; 3090 uint8_t teng_ethernet:4; 3091 }; 3092 3093 struct sff_trasnceiver_codes_byte1 { 3094 uint8_t sonet:6; 3095 uint8_t escon:2; 3096 }; 3097 3098 struct sff_trasnceiver_codes_byte2 { 3099 uint8_t soNet:8; 3100 }; 3101 3102 struct sff_trasnceiver_codes_byte3 { 3103 uint8_t ethernet:8; 3104 }; 3105 3106 struct sff_trasnceiver_codes_byte4 { 3107 uint8_t fc_el_lo:1; 3108 uint8_t fc_lw_laser:1; 3109 uint8_t fc_sw_laser:1; 3110 uint8_t fc_md_distance:1; 3111 uint8_t fc_lg_distance:1; 3112 uint8_t fc_int_distance:1; 3113 uint8_t fc_short_distance:1; 3114 uint8_t fc_vld_distance:1; 3115 }; 3116 3117 struct sff_trasnceiver_codes_byte5 { 3118 uint8_t reserved1:1; 3119 uint8_t reserved2:1; 3120 uint8_t fc_sfp_active:1; /* Active cable */ 3121 uint8_t fc_sfp_passive:1; /* Passive cable */ 3122 uint8_t fc_lw_laser:1; /* Longwave laser */ 3123 uint8_t fc_sw_laser_sl:1; 3124 uint8_t fc_sw_laser_sn:1; 3125 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3126 }; 3127 3128 struct sff_trasnceiver_codes_byte6 { 3129 uint8_t fc_tm_sm:1; /* Single Mode */ 3130 uint8_t reserved:1; 3131 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3132 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3133 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3134 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3135 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3136 }; 3137 3138 struct sff_trasnceiver_codes_byte7 { 3139 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3140 uint8_t reserve:1; 3141 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3142 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3143 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3144 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3145 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3146 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3147 }; 3148 3149 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3150 struct user_eeprom { 3151 uint8_t vendor_name[16]; 3152 uint8_t vendor_oui[3]; 3153 uint8_t vendor_pn[816]; 3154 uint8_t vendor_rev[4]; 3155 uint8_t vendor_sn[16]; 3156 uint8_t datecode[6]; 3157 uint8_t lot_code[2]; 3158 uint8_t reserved191[57]; 3159 }; 3160 3161 struct lpfc_mbx_pc_sli4_params { 3162 uint32_t word1; 3163 #define qs_SHIFT 0 3164 #define qs_MASK 0x00000001 3165 #define qs_WORD word1 3166 #define wr_SHIFT 1 3167 #define wr_MASK 0x00000001 3168 #define wr_WORD word1 3169 #define pf_SHIFT 8 3170 #define pf_MASK 0x000000ff 3171 #define pf_WORD word1 3172 #define cpn_SHIFT 16 3173 #define cpn_MASK 0x000000ff 3174 #define cpn_WORD word1 3175 uint32_t word2; 3176 #define if_type_SHIFT 0 3177 #define if_type_MASK 0x00000007 3178 #define if_type_WORD word2 3179 #define sli_rev_SHIFT 4 3180 #define sli_rev_MASK 0x0000000f 3181 #define sli_rev_WORD word2 3182 #define sli_family_SHIFT 8 3183 #define sli_family_MASK 0x000000ff 3184 #define sli_family_WORD word2 3185 #define featurelevel_1_SHIFT 16 3186 #define featurelevel_1_MASK 0x000000ff 3187 #define featurelevel_1_WORD word2 3188 #define featurelevel_2_SHIFT 24 3189 #define featurelevel_2_MASK 0x0000001f 3190 #define featurelevel_2_WORD word2 3191 uint32_t word3; 3192 #define fcoe_SHIFT 0 3193 #define fcoe_MASK 0x00000001 3194 #define fcoe_WORD word3 3195 #define fc_SHIFT 1 3196 #define fc_MASK 0x00000001 3197 #define fc_WORD word3 3198 #define nic_SHIFT 2 3199 #define nic_MASK 0x00000001 3200 #define nic_WORD word3 3201 #define iscsi_SHIFT 3 3202 #define iscsi_MASK 0x00000001 3203 #define iscsi_WORD word3 3204 #define rdma_SHIFT 4 3205 #define rdma_MASK 0x00000001 3206 #define rdma_WORD word3 3207 uint32_t sge_supp_len; 3208 #define SLI4_PAGE_SIZE 4096 3209 uint32_t word5; 3210 #define if_page_sz_SHIFT 0 3211 #define if_page_sz_MASK 0x0000ffff 3212 #define if_page_sz_WORD word5 3213 #define loopbk_scope_SHIFT 24 3214 #define loopbk_scope_MASK 0x0000000f 3215 #define loopbk_scope_WORD word5 3216 #define rq_db_window_SHIFT 28 3217 #define rq_db_window_MASK 0x0000000f 3218 #define rq_db_window_WORD word5 3219 uint32_t word6; 3220 #define eq_pages_SHIFT 0 3221 #define eq_pages_MASK 0x0000000f 3222 #define eq_pages_WORD word6 3223 #define eqe_size_SHIFT 8 3224 #define eqe_size_MASK 0x000000ff 3225 #define eqe_size_WORD word6 3226 uint32_t word7; 3227 #define cq_pages_SHIFT 0 3228 #define cq_pages_MASK 0x0000000f 3229 #define cq_pages_WORD word7 3230 #define cqe_size_SHIFT 8 3231 #define cqe_size_MASK 0x000000ff 3232 #define cqe_size_WORD word7 3233 uint32_t word8; 3234 #define mq_pages_SHIFT 0 3235 #define mq_pages_MASK 0x0000000f 3236 #define mq_pages_WORD word8 3237 #define mqe_size_SHIFT 8 3238 #define mqe_size_MASK 0x000000ff 3239 #define mqe_size_WORD word8 3240 #define mq_elem_cnt_SHIFT 16 3241 #define mq_elem_cnt_MASK 0x000000ff 3242 #define mq_elem_cnt_WORD word8 3243 uint32_t word9; 3244 #define wq_pages_SHIFT 0 3245 #define wq_pages_MASK 0x0000ffff 3246 #define wq_pages_WORD word9 3247 #define wqe_size_SHIFT 8 3248 #define wqe_size_MASK 0x000000ff 3249 #define wqe_size_WORD word9 3250 uint32_t word10; 3251 #define rq_pages_SHIFT 0 3252 #define rq_pages_MASK 0x0000ffff 3253 #define rq_pages_WORD word10 3254 #define rqe_size_SHIFT 8 3255 #define rqe_size_MASK 0x000000ff 3256 #define rqe_size_WORD word10 3257 uint32_t word11; 3258 #define hdr_pages_SHIFT 0 3259 #define hdr_pages_MASK 0x0000000f 3260 #define hdr_pages_WORD word11 3261 #define hdr_size_SHIFT 8 3262 #define hdr_size_MASK 0x0000000f 3263 #define hdr_size_WORD word11 3264 #define hdr_pp_align_SHIFT 16 3265 #define hdr_pp_align_MASK 0x0000ffff 3266 #define hdr_pp_align_WORD word11 3267 uint32_t word12; 3268 #define sgl_pages_SHIFT 0 3269 #define sgl_pages_MASK 0x0000000f 3270 #define sgl_pages_WORD word12 3271 #define sgl_pp_align_SHIFT 16 3272 #define sgl_pp_align_MASK 0x0000ffff 3273 #define sgl_pp_align_WORD word12 3274 uint32_t rsvd_13_63[51]; 3275 }; 3276 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3277 &(~((SLI4_PAGE_SIZE)-1))) 3278 3279 struct lpfc_sli4_parameters { 3280 uint32_t word0; 3281 #define cfg_prot_type_SHIFT 0 3282 #define cfg_prot_type_MASK 0x000000FF 3283 #define cfg_prot_type_WORD word0 3284 uint32_t word1; 3285 #define cfg_ft_SHIFT 0 3286 #define cfg_ft_MASK 0x00000001 3287 #define cfg_ft_WORD word1 3288 #define cfg_sli_rev_SHIFT 4 3289 #define cfg_sli_rev_MASK 0x0000000f 3290 #define cfg_sli_rev_WORD word1 3291 #define cfg_sli_family_SHIFT 8 3292 #define cfg_sli_family_MASK 0x0000000f 3293 #define cfg_sli_family_WORD word1 3294 #define cfg_if_type_SHIFT 12 3295 #define cfg_if_type_MASK 0x0000000f 3296 #define cfg_if_type_WORD word1 3297 #define cfg_sli_hint_1_SHIFT 16 3298 #define cfg_sli_hint_1_MASK 0x000000ff 3299 #define cfg_sli_hint_1_WORD word1 3300 #define cfg_sli_hint_2_SHIFT 24 3301 #define cfg_sli_hint_2_MASK 0x0000001f 3302 #define cfg_sli_hint_2_WORD word1 3303 uint32_t word2; 3304 #define cfg_eqav_SHIFT 31 3305 #define cfg_eqav_MASK 0x00000001 3306 #define cfg_eqav_WORD word2 3307 uint32_t word3; 3308 uint32_t word4; 3309 #define cfg_cqv_SHIFT 14 3310 #define cfg_cqv_MASK 0x00000003 3311 #define cfg_cqv_WORD word4 3312 #define cfg_cqpsize_SHIFT 16 3313 #define cfg_cqpsize_MASK 0x000000ff 3314 #define cfg_cqpsize_WORD word4 3315 #define cfg_cqav_SHIFT 31 3316 #define cfg_cqav_MASK 0x00000001 3317 #define cfg_cqav_WORD word4 3318 uint32_t word5; 3319 uint32_t word6; 3320 #define cfg_mqv_SHIFT 14 3321 #define cfg_mqv_MASK 0x00000003 3322 #define cfg_mqv_WORD word6 3323 uint32_t word7; 3324 uint32_t word8; 3325 #define cfg_wqpcnt_SHIFT 0 3326 #define cfg_wqpcnt_MASK 0x0000000f 3327 #define cfg_wqpcnt_WORD word8 3328 #define cfg_wqsize_SHIFT 8 3329 #define cfg_wqsize_MASK 0x0000000f 3330 #define cfg_wqsize_WORD word8 3331 #define cfg_wqv_SHIFT 14 3332 #define cfg_wqv_MASK 0x00000003 3333 #define cfg_wqv_WORD word8 3334 #define cfg_wqpsize_SHIFT 16 3335 #define cfg_wqpsize_MASK 0x000000ff 3336 #define cfg_wqpsize_WORD word8 3337 uint32_t word9; 3338 uint32_t word10; 3339 #define cfg_rqv_SHIFT 14 3340 #define cfg_rqv_MASK 0x00000003 3341 #define cfg_rqv_WORD word10 3342 uint32_t word11; 3343 #define cfg_rq_db_window_SHIFT 28 3344 #define cfg_rq_db_window_MASK 0x0000000f 3345 #define cfg_rq_db_window_WORD word11 3346 uint32_t word12; 3347 #define cfg_fcoe_SHIFT 0 3348 #define cfg_fcoe_MASK 0x00000001 3349 #define cfg_fcoe_WORD word12 3350 #define cfg_ext_SHIFT 1 3351 #define cfg_ext_MASK 0x00000001 3352 #define cfg_ext_WORD word12 3353 #define cfg_hdrr_SHIFT 2 3354 #define cfg_hdrr_MASK 0x00000001 3355 #define cfg_hdrr_WORD word12 3356 #define cfg_phwq_SHIFT 15 3357 #define cfg_phwq_MASK 0x00000001 3358 #define cfg_phwq_WORD word12 3359 #define cfg_oas_SHIFT 25 3360 #define cfg_oas_MASK 0x00000001 3361 #define cfg_oas_WORD word12 3362 #define cfg_loopbk_scope_SHIFT 28 3363 #define cfg_loopbk_scope_MASK 0x0000000f 3364 #define cfg_loopbk_scope_WORD word12 3365 uint32_t sge_supp_len; 3366 uint32_t word14; 3367 #define cfg_sgl_page_cnt_SHIFT 0 3368 #define cfg_sgl_page_cnt_MASK 0x0000000f 3369 #define cfg_sgl_page_cnt_WORD word14 3370 #define cfg_sgl_page_size_SHIFT 8 3371 #define cfg_sgl_page_size_MASK 0x000000ff 3372 #define cfg_sgl_page_size_WORD word14 3373 #define cfg_sgl_pp_align_SHIFT 16 3374 #define cfg_sgl_pp_align_MASK 0x000000ff 3375 #define cfg_sgl_pp_align_WORD word14 3376 uint32_t word15; 3377 uint32_t word16; 3378 uint32_t word17; 3379 uint32_t word18; 3380 uint32_t word19; 3381 #define cfg_ext_embed_cb_SHIFT 0 3382 #define cfg_ext_embed_cb_MASK 0x00000001 3383 #define cfg_ext_embed_cb_WORD word19 3384 #define cfg_mds_diags_SHIFT 1 3385 #define cfg_mds_diags_MASK 0x00000001 3386 #define cfg_mds_diags_WORD word19 3387 #define cfg_nvme_SHIFT 3 3388 #define cfg_nvme_MASK 0x00000001 3389 #define cfg_nvme_WORD word19 3390 #define cfg_xib_SHIFT 4 3391 #define cfg_xib_MASK 0x00000001 3392 #define cfg_xib_WORD word19 3393 #define cfg_eqdr_SHIFT 8 3394 #define cfg_eqdr_MASK 0x00000001 3395 #define cfg_eqdr_WORD word19 3396 #define cfg_nosr_SHIFT 9 3397 #define cfg_nosr_MASK 0x00000001 3398 #define cfg_nosr_WORD word19 3399 3400 #define cfg_bv1s_SHIFT 10 3401 #define cfg_bv1s_MASK 0x00000001 3402 #define cfg_bv1s_WORD word19 3403 3404 uint32_t word20; 3405 #define cfg_max_tow_xri_SHIFT 0 3406 #define cfg_max_tow_xri_MASK 0x0000ffff 3407 #define cfg_max_tow_xri_WORD word20 3408 3409 uint32_t word21; /* RESERVED */ 3410 uint32_t word22; /* RESERVED */ 3411 uint32_t word23; /* RESERVED */ 3412 3413 uint32_t word24; 3414 #define cfg_frag_field_offset_SHIFT 0 3415 #define cfg_frag_field_offset_MASK 0x0000ffff 3416 #define cfg_frag_field_offset_WORD word24 3417 3418 #define cfg_frag_field_size_SHIFT 16 3419 #define cfg_frag_field_size_MASK 0x0000ffff 3420 #define cfg_frag_field_size_WORD word24 3421 3422 uint32_t word25; 3423 #define cfg_sgl_field_offset_SHIFT 0 3424 #define cfg_sgl_field_offset_MASK 0x0000ffff 3425 #define cfg_sgl_field_offset_WORD word25 3426 3427 #define cfg_sgl_field_size_SHIFT 16 3428 #define cfg_sgl_field_size_MASK 0x0000ffff 3429 #define cfg_sgl_field_size_WORD word25 3430 3431 uint32_t word26; /* Chain SGE initial value LOW */ 3432 uint32_t word27; /* Chain SGE initial value HIGH */ 3433 #define LPFC_NODELAY_MAX_IO 32 3434 }; 3435 3436 #define LPFC_SET_UE_RECOVERY 0x10 3437 #define LPFC_SET_MDS_DIAGS 0x11 3438 struct lpfc_mbx_set_feature { 3439 struct mbox_header header; 3440 uint32_t feature; 3441 uint32_t param_len; 3442 uint32_t word6; 3443 #define lpfc_mbx_set_feature_UER_SHIFT 0 3444 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3445 #define lpfc_mbx_set_feature_UER_WORD word6 3446 #define lpfc_mbx_set_feature_mds_SHIFT 0 3447 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3448 #define lpfc_mbx_set_feature_mds_WORD word6 3449 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3450 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3451 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3452 uint32_t word7; 3453 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3454 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3455 #define lpfc_mbx_set_feature_UERP_WORD word7 3456 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3457 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3458 #define lpfc_mbx_set_feature_UESR_WORD word7 3459 }; 3460 3461 3462 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3463 struct lpfc_mbx_set_host_data { 3464 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3465 struct mbox_header header; 3466 uint32_t param_id; 3467 uint32_t param_len; 3468 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3469 }; 3470 3471 3472 struct lpfc_mbx_get_sli4_parameters { 3473 struct mbox_header header; 3474 struct lpfc_sli4_parameters sli4_parameters; 3475 }; 3476 3477 struct lpfc_rscr_desc_generic { 3478 #define LPFC_RSRC_DESC_WSIZE 22 3479 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3480 }; 3481 3482 struct lpfc_rsrc_desc_pcie { 3483 uint32_t word0; 3484 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3485 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3486 #define lpfc_rsrc_desc_pcie_type_WORD word0 3487 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3488 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3489 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3490 #define lpfc_rsrc_desc_pcie_length_WORD word0 3491 uint32_t word1; 3492 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3493 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3494 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3495 uint32_t reserved; 3496 uint32_t word3; 3497 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3498 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3499 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3500 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3501 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3502 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3503 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3504 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3505 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3506 uint32_t word4; 3507 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3508 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3509 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3510 }; 3511 3512 struct lpfc_rsrc_desc_fcfcoe { 3513 uint32_t word0; 3514 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3515 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3516 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3517 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3518 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3519 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3520 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3521 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3522 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3523 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3524 uint32_t word1; 3525 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3526 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3527 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3528 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3529 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3530 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3531 uint32_t word2; 3532 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3533 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3534 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3535 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3536 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3537 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3538 uint32_t word3; 3539 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3540 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3541 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3542 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3543 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3544 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3545 uint32_t word4; 3546 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3547 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3548 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3549 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3550 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3551 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3552 uint32_t word5; 3553 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3554 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3555 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3556 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3557 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3558 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3559 uint32_t word6; 3560 uint32_t word7; 3561 uint32_t word8; 3562 uint32_t word9; 3563 uint32_t word10; 3564 uint32_t word11; 3565 uint32_t word12; 3566 uint32_t word13; 3567 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3568 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3569 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3570 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3571 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3572 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3573 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3574 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3575 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3576 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3577 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3578 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3579 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3580 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3581 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3582 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3583 uint32_t bw_min; 3584 uint32_t bw_max; 3585 uint32_t iops_min; 3586 uint32_t iops_max; 3587 uint32_t reserved[4]; 3588 }; 3589 3590 struct lpfc_func_cfg { 3591 #define LPFC_RSRC_DESC_MAX_NUM 2 3592 uint32_t rsrc_desc_count; 3593 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3594 }; 3595 3596 struct lpfc_mbx_get_func_cfg { 3597 struct mbox_header header; 3598 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3599 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3600 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3601 struct lpfc_func_cfg func_cfg; 3602 }; 3603 3604 struct lpfc_prof_cfg { 3605 #define LPFC_RSRC_DESC_MAX_NUM 2 3606 uint32_t rsrc_desc_count; 3607 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3608 }; 3609 3610 struct lpfc_mbx_get_prof_cfg { 3611 struct mbox_header header; 3612 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3613 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3614 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3615 union { 3616 struct { 3617 uint32_t word10; 3618 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3619 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3620 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3621 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3622 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3623 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3624 } request; 3625 struct { 3626 struct lpfc_prof_cfg prof_cfg; 3627 } response; 3628 } u; 3629 }; 3630 3631 struct lpfc_controller_attribute { 3632 uint32_t version_string[8]; 3633 uint32_t manufacturer_name[8]; 3634 uint32_t supported_modes; 3635 uint32_t word17; 3636 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3637 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3638 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3639 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3640 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3641 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3642 uint32_t mbx_da_struct_ver; 3643 uint32_t ep_fw_da_struct_ver; 3644 uint32_t ncsi_ver_str[3]; 3645 uint32_t dflt_ext_timeout; 3646 uint32_t model_number[8]; 3647 uint32_t description[16]; 3648 uint32_t serial_number[8]; 3649 uint32_t ip_ver_str[8]; 3650 uint32_t fw_ver_str[8]; 3651 uint32_t bios_ver_str[8]; 3652 uint32_t redboot_ver_str[8]; 3653 uint32_t driver_ver_str[8]; 3654 uint32_t flash_fw_ver_str[8]; 3655 uint32_t functionality; 3656 uint32_t word105; 3657 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3658 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3659 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3660 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3661 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3662 #define lpfc_cntl_attr_asic_rev_WORD word105 3663 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3664 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3665 #define lpfc_cntl_attr_gen_guid0_WORD word105 3666 uint32_t gen_guid1_12[3]; 3667 uint32_t word109; 3668 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3669 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3670 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3671 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3672 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3673 #define lpfc_cntl_attr_gen_guid15_WORD word109 3674 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3675 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3676 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3677 uint32_t word110; 3678 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3679 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3680 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3681 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3682 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3683 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3684 uint32_t word111; 3685 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3686 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3687 #define lpfc_cntl_attr_cache_valid_WORD word111 3688 #define lpfc_cntl_attr_hba_status_SHIFT 8 3689 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3690 #define lpfc_cntl_attr_hba_status_WORD word111 3691 #define lpfc_cntl_attr_max_domain_SHIFT 16 3692 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3693 #define lpfc_cntl_attr_max_domain_WORD word111 3694 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3695 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3696 #define lpfc_cntl_attr_lnk_numb_WORD word111 3697 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3698 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3699 #define lpfc_cntl_attr_lnk_type_WORD word111 3700 uint32_t fw_post_status; 3701 uint32_t hba_mtu[8]; 3702 uint32_t word121; 3703 uint32_t reserved1[3]; 3704 uint32_t word125; 3705 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3706 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3707 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3708 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3709 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3710 #define lpfc_cntl_attr_pci_device_id_WORD word125 3711 uint32_t word126; 3712 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3713 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3714 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3715 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3716 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3717 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3718 uint32_t word127; 3719 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3720 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3721 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3722 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3723 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3724 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3725 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3726 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3727 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3728 #define lpfc_cntl_attr_inf_type_SHIFT 24 3729 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3730 #define lpfc_cntl_attr_inf_type_WORD word127 3731 uint32_t unique_id[2]; 3732 uint32_t word130; 3733 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3734 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3735 #define lpfc_cntl_attr_num_netfil_WORD word130 3736 uint32_t reserved2[4]; 3737 }; 3738 3739 struct lpfc_mbx_get_cntl_attributes { 3740 union lpfc_sli4_cfg_shdr cfg_shdr; 3741 struct lpfc_controller_attribute cntl_attr; 3742 }; 3743 3744 struct lpfc_mbx_get_port_name { 3745 struct mbox_header header; 3746 union { 3747 struct { 3748 uint32_t word4; 3749 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3750 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3751 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3752 } request; 3753 struct { 3754 uint32_t word4; 3755 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3756 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3757 #define lpfc_mbx_get_port_name_name0_WORD word4 3758 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3759 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3760 #define lpfc_mbx_get_port_name_name1_WORD word4 3761 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3762 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3763 #define lpfc_mbx_get_port_name_name2_WORD word4 3764 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3765 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3766 #define lpfc_mbx_get_port_name_name3_WORD word4 3767 #define LPFC_LINK_NUMBER_0 0 3768 #define LPFC_LINK_NUMBER_1 1 3769 #define LPFC_LINK_NUMBER_2 2 3770 #define LPFC_LINK_NUMBER_3 3 3771 } response; 3772 } u; 3773 }; 3774 3775 /* Mailbox Completion Queue Error Messages */ 3776 #define MB_CQE_STATUS_SUCCESS 0x0 3777 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3778 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3779 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3780 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3781 #define MB_CQE_STATUS_DMA_FAILED 0x5 3782 3783 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3784 struct lpfc_mbx_wr_object { 3785 struct mbox_header header; 3786 union { 3787 struct { 3788 uint32_t word4; 3789 #define lpfc_wr_object_eof_SHIFT 31 3790 #define lpfc_wr_object_eof_MASK 0x00000001 3791 #define lpfc_wr_object_eof_WORD word4 3792 #define lpfc_wr_object_write_length_SHIFT 0 3793 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3794 #define lpfc_wr_object_write_length_WORD word4 3795 uint32_t write_offset; 3796 uint32_t object_name[26]; 3797 uint32_t bde_count; 3798 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3799 } request; 3800 struct { 3801 uint32_t actual_write_length; 3802 } response; 3803 } u; 3804 }; 3805 3806 /* mailbox queue entry structure */ 3807 struct lpfc_mqe { 3808 uint32_t word0; 3809 #define lpfc_mqe_status_SHIFT 16 3810 #define lpfc_mqe_status_MASK 0x0000FFFF 3811 #define lpfc_mqe_status_WORD word0 3812 #define lpfc_mqe_command_SHIFT 8 3813 #define lpfc_mqe_command_MASK 0x000000FF 3814 #define lpfc_mqe_command_WORD word0 3815 union { 3816 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3817 /* sli4 mailbox commands */ 3818 struct lpfc_mbx_sli4_config sli4_config; 3819 struct lpfc_mbx_init_vfi init_vfi; 3820 struct lpfc_mbx_reg_vfi reg_vfi; 3821 struct lpfc_mbx_reg_vfi unreg_vfi; 3822 struct lpfc_mbx_init_vpi init_vpi; 3823 struct lpfc_mbx_resume_rpi resume_rpi; 3824 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3825 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3826 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3827 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3828 struct lpfc_mbx_reg_fcfi reg_fcfi; 3829 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3830 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3831 struct lpfc_mbx_mq_create mq_create; 3832 struct lpfc_mbx_mq_create_ext mq_create_ext; 3833 struct lpfc_mbx_eq_create eq_create; 3834 struct lpfc_mbx_modify_eq_delay eq_delay; 3835 struct lpfc_mbx_cq_create cq_create; 3836 struct lpfc_mbx_cq_create_set cq_create_set; 3837 struct lpfc_mbx_wq_create wq_create; 3838 struct lpfc_mbx_rq_create rq_create; 3839 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3840 struct lpfc_mbx_mq_destroy mq_destroy; 3841 struct lpfc_mbx_eq_destroy eq_destroy; 3842 struct lpfc_mbx_cq_destroy cq_destroy; 3843 struct lpfc_mbx_wq_destroy wq_destroy; 3844 struct lpfc_mbx_rq_destroy rq_destroy; 3845 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3846 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3847 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3848 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3849 struct lpfc_mbx_nembed_cmd nembed_cmd; 3850 struct lpfc_mbx_read_rev read_rev; 3851 struct lpfc_mbx_read_vpi read_vpi; 3852 struct lpfc_mbx_read_config rd_config; 3853 struct lpfc_mbx_request_features req_ftrs; 3854 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3855 struct lpfc_mbx_query_fw_config query_fw_cfg; 3856 struct lpfc_mbx_set_beacon_config beacon_config; 3857 struct lpfc_mbx_supp_pages supp_pages; 3858 struct lpfc_mbx_pc_sli4_params sli4_params; 3859 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3860 struct lpfc_mbx_set_link_diag_state link_diag_state; 3861 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3862 struct lpfc_mbx_run_link_diag_test link_diag_test; 3863 struct lpfc_mbx_get_func_cfg get_func_cfg; 3864 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3865 struct lpfc_mbx_wr_object wr_object; 3866 struct lpfc_mbx_get_port_name get_port_name; 3867 struct lpfc_mbx_set_feature set_feature; 3868 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3869 struct lpfc_mbx_set_host_data set_host_data; 3870 struct lpfc_mbx_nop nop; 3871 } un; 3872 }; 3873 3874 struct lpfc_mcqe { 3875 uint32_t word0; 3876 #define lpfc_mcqe_status_SHIFT 0 3877 #define lpfc_mcqe_status_MASK 0x0000FFFF 3878 #define lpfc_mcqe_status_WORD word0 3879 #define lpfc_mcqe_ext_status_SHIFT 16 3880 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3881 #define lpfc_mcqe_ext_status_WORD word0 3882 uint32_t mcqe_tag0; 3883 uint32_t mcqe_tag1; 3884 uint32_t trailer; 3885 #define lpfc_trailer_valid_SHIFT 31 3886 #define lpfc_trailer_valid_MASK 0x00000001 3887 #define lpfc_trailer_valid_WORD trailer 3888 #define lpfc_trailer_async_SHIFT 30 3889 #define lpfc_trailer_async_MASK 0x00000001 3890 #define lpfc_trailer_async_WORD trailer 3891 #define lpfc_trailer_hpi_SHIFT 29 3892 #define lpfc_trailer_hpi_MASK 0x00000001 3893 #define lpfc_trailer_hpi_WORD trailer 3894 #define lpfc_trailer_completed_SHIFT 28 3895 #define lpfc_trailer_completed_MASK 0x00000001 3896 #define lpfc_trailer_completed_WORD trailer 3897 #define lpfc_trailer_consumed_SHIFT 27 3898 #define lpfc_trailer_consumed_MASK 0x00000001 3899 #define lpfc_trailer_consumed_WORD trailer 3900 #define lpfc_trailer_type_SHIFT 16 3901 #define lpfc_trailer_type_MASK 0x000000FF 3902 #define lpfc_trailer_type_WORD trailer 3903 #define lpfc_trailer_code_SHIFT 8 3904 #define lpfc_trailer_code_MASK 0x000000FF 3905 #define lpfc_trailer_code_WORD trailer 3906 #define LPFC_TRAILER_CODE_LINK 0x1 3907 #define LPFC_TRAILER_CODE_FCOE 0x2 3908 #define LPFC_TRAILER_CODE_DCBX 0x3 3909 #define LPFC_TRAILER_CODE_GRP5 0x5 3910 #define LPFC_TRAILER_CODE_FC 0x10 3911 #define LPFC_TRAILER_CODE_SLI 0x11 3912 }; 3913 3914 struct lpfc_acqe_link { 3915 uint32_t word0; 3916 #define lpfc_acqe_link_speed_SHIFT 24 3917 #define lpfc_acqe_link_speed_MASK 0x000000FF 3918 #define lpfc_acqe_link_speed_WORD word0 3919 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3920 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3921 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3922 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3923 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3924 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3925 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3926 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3927 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3928 #define lpfc_acqe_link_duplex_SHIFT 16 3929 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3930 #define lpfc_acqe_link_duplex_WORD word0 3931 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3932 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3933 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3934 #define lpfc_acqe_link_status_SHIFT 8 3935 #define lpfc_acqe_link_status_MASK 0x000000FF 3936 #define lpfc_acqe_link_status_WORD word0 3937 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3938 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3939 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3940 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3941 #define lpfc_acqe_link_type_SHIFT 6 3942 #define lpfc_acqe_link_type_MASK 0x00000003 3943 #define lpfc_acqe_link_type_WORD word0 3944 #define lpfc_acqe_link_number_SHIFT 0 3945 #define lpfc_acqe_link_number_MASK 0x0000003F 3946 #define lpfc_acqe_link_number_WORD word0 3947 uint32_t word1; 3948 #define lpfc_acqe_link_fault_SHIFT 0 3949 #define lpfc_acqe_link_fault_MASK 0x000000FF 3950 #define lpfc_acqe_link_fault_WORD word1 3951 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3952 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3953 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3954 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 3955 #define lpfc_acqe_logical_link_speed_SHIFT 16 3956 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3957 #define lpfc_acqe_logical_link_speed_WORD word1 3958 uint32_t event_tag; 3959 uint32_t trailer; 3960 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3961 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3962 }; 3963 3964 struct lpfc_acqe_fip { 3965 uint32_t index; 3966 uint32_t word1; 3967 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3968 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3969 #define lpfc_acqe_fip_fcf_count_WORD word1 3970 #define lpfc_acqe_fip_event_type_SHIFT 16 3971 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3972 #define lpfc_acqe_fip_event_type_WORD word1 3973 uint32_t event_tag; 3974 uint32_t trailer; 3975 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3976 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3977 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3978 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3979 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3980 }; 3981 3982 struct lpfc_acqe_dcbx { 3983 uint32_t tlv_ttl; 3984 uint32_t reserved; 3985 uint32_t event_tag; 3986 uint32_t trailer; 3987 }; 3988 3989 struct lpfc_acqe_grp5 { 3990 uint32_t word0; 3991 #define lpfc_acqe_grp5_type_SHIFT 6 3992 #define lpfc_acqe_grp5_type_MASK 0x00000003 3993 #define lpfc_acqe_grp5_type_WORD word0 3994 #define lpfc_acqe_grp5_number_SHIFT 0 3995 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3996 #define lpfc_acqe_grp5_number_WORD word0 3997 uint32_t word1; 3998 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3999 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4000 #define lpfc_acqe_grp5_llink_spd_WORD word1 4001 uint32_t event_tag; 4002 uint32_t trailer; 4003 }; 4004 4005 struct lpfc_acqe_fc_la { 4006 uint32_t word0; 4007 #define lpfc_acqe_fc_la_speed_SHIFT 24 4008 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4009 #define lpfc_acqe_fc_la_speed_WORD word0 4010 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4011 #define LPFC_FC_LA_SPEED_1G 0x1 4012 #define LPFC_FC_LA_SPEED_2G 0x2 4013 #define LPFC_FC_LA_SPEED_4G 0x4 4014 #define LPFC_FC_LA_SPEED_8G 0x8 4015 #define LPFC_FC_LA_SPEED_10G 0xA 4016 #define LPFC_FC_LA_SPEED_16G 0x10 4017 #define LPFC_FC_LA_SPEED_32G 0x20 4018 #define LPFC_FC_LA_SPEED_64G 0x21 4019 #define LPFC_FC_LA_SPEED_128G 0x22 4020 #define LPFC_FC_LA_SPEED_256G 0x23 4021 #define lpfc_acqe_fc_la_topology_SHIFT 16 4022 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4023 #define lpfc_acqe_fc_la_topology_WORD word0 4024 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4025 #define LPFC_FC_LA_TOP_P2P 0x1 4026 #define LPFC_FC_LA_TOP_FCAL 0x2 4027 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4028 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4029 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4030 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4031 #define lpfc_acqe_fc_la_att_type_WORD word0 4032 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4033 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4034 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4035 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4036 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4037 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4038 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4039 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4040 #define lpfc_acqe_fc_la_port_type_WORD word0 4041 #define LPFC_LINK_TYPE_ETHERNET 0x0 4042 #define LPFC_LINK_TYPE_FC 0x1 4043 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4044 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4045 #define lpfc_acqe_fc_la_port_number_WORD word0 4046 uint32_t word1; 4047 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4048 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4049 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4050 #define lpfc_acqe_fc_la_fault_SHIFT 0 4051 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4052 #define lpfc_acqe_fc_la_fault_WORD word1 4053 #define LPFC_FC_LA_FAULT_NONE 0x0 4054 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4055 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4056 uint32_t event_tag; 4057 uint32_t trailer; 4058 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4059 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4060 }; 4061 4062 struct lpfc_acqe_misconfigured_event { 4063 struct { 4064 uint32_t word0; 4065 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4066 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4067 #define lpfc_sli_misconfigured_port0_state_WORD word0 4068 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4069 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4070 #define lpfc_sli_misconfigured_port1_state_WORD word0 4071 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4072 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4073 #define lpfc_sli_misconfigured_port2_state_WORD word0 4074 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4075 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4076 #define lpfc_sli_misconfigured_port3_state_WORD word0 4077 uint32_t word1; 4078 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4079 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4080 #define lpfc_sli_misconfigured_port0_op_WORD word1 4081 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4082 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4083 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4084 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4085 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4086 #define lpfc_sli_misconfigured_port1_op_WORD word1 4087 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4088 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4089 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4090 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4091 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4092 #define lpfc_sli_misconfigured_port2_op_WORD word1 4093 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4094 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4095 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4096 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4097 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4098 #define lpfc_sli_misconfigured_port3_op_WORD word1 4099 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4100 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4101 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4102 } theEvent; 4103 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4104 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4105 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4106 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4107 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4108 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4109 }; 4110 4111 struct lpfc_acqe_sli { 4112 uint32_t event_data1; 4113 uint32_t event_data2; 4114 uint32_t reserved; 4115 uint32_t trailer; 4116 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4117 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4118 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4119 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4120 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4121 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4122 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4123 }; 4124 4125 /* 4126 * Define the bootstrap mailbox (bmbx) region used to communicate 4127 * mailbox command between the host and port. The mailbox consists 4128 * of a payload area of 256 bytes and a completion queue of length 4129 * 16 bytes. 4130 */ 4131 struct lpfc_bmbx_create { 4132 struct lpfc_mqe mqe; 4133 struct lpfc_mcqe mcqe; 4134 }; 4135 4136 #define SGL_ALIGN_SZ 64 4137 #define SGL_PAGE_SIZE 4096 4138 /* align SGL addr on a size boundary - adjust address up */ 4139 #define NO_XRI 0xffff 4140 4141 struct wqe_common { 4142 uint32_t word6; 4143 #define wqe_xri_tag_SHIFT 0 4144 #define wqe_xri_tag_MASK 0x0000FFFF 4145 #define wqe_xri_tag_WORD word6 4146 #define wqe_ctxt_tag_SHIFT 16 4147 #define wqe_ctxt_tag_MASK 0x0000FFFF 4148 #define wqe_ctxt_tag_WORD word6 4149 uint32_t word7; 4150 #define wqe_dif_SHIFT 0 4151 #define wqe_dif_MASK 0x00000003 4152 #define wqe_dif_WORD word7 4153 #define LPFC_WQE_DIF_PASSTHRU 1 4154 #define LPFC_WQE_DIF_STRIP 2 4155 #define LPFC_WQE_DIF_INSERT 3 4156 #define wqe_ct_SHIFT 2 4157 #define wqe_ct_MASK 0x00000003 4158 #define wqe_ct_WORD word7 4159 #define wqe_status_SHIFT 4 4160 #define wqe_status_MASK 0x0000000f 4161 #define wqe_status_WORD word7 4162 #define wqe_cmnd_SHIFT 8 4163 #define wqe_cmnd_MASK 0x000000ff 4164 #define wqe_cmnd_WORD word7 4165 #define wqe_class_SHIFT 16 4166 #define wqe_class_MASK 0x00000007 4167 #define wqe_class_WORD word7 4168 #define wqe_ar_SHIFT 19 4169 #define wqe_ar_MASK 0x00000001 4170 #define wqe_ar_WORD word7 4171 #define wqe_ag_SHIFT wqe_ar_SHIFT 4172 #define wqe_ag_MASK wqe_ar_MASK 4173 #define wqe_ag_WORD wqe_ar_WORD 4174 #define wqe_pu_SHIFT 20 4175 #define wqe_pu_MASK 0x00000003 4176 #define wqe_pu_WORD word7 4177 #define wqe_erp_SHIFT 22 4178 #define wqe_erp_MASK 0x00000001 4179 #define wqe_erp_WORD word7 4180 #define wqe_conf_SHIFT wqe_erp_SHIFT 4181 #define wqe_conf_MASK wqe_erp_MASK 4182 #define wqe_conf_WORD wqe_erp_WORD 4183 #define wqe_lnk_SHIFT 23 4184 #define wqe_lnk_MASK 0x00000001 4185 #define wqe_lnk_WORD word7 4186 #define wqe_tmo_SHIFT 24 4187 #define wqe_tmo_MASK 0x000000ff 4188 #define wqe_tmo_WORD word7 4189 uint32_t abort_tag; /* word 8 in WQE */ 4190 uint32_t word9; 4191 #define wqe_reqtag_SHIFT 0 4192 #define wqe_reqtag_MASK 0x0000FFFF 4193 #define wqe_reqtag_WORD word9 4194 #define wqe_temp_rpi_SHIFT 16 4195 #define wqe_temp_rpi_MASK 0x0000FFFF 4196 #define wqe_temp_rpi_WORD word9 4197 #define wqe_rcvoxid_SHIFT 16 4198 #define wqe_rcvoxid_MASK 0x0000FFFF 4199 #define wqe_rcvoxid_WORD word9 4200 uint32_t word10; 4201 #define wqe_ebde_cnt_SHIFT 0 4202 #define wqe_ebde_cnt_MASK 0x0000000f 4203 #define wqe_ebde_cnt_WORD word10 4204 #define wqe_nvme_SHIFT 4 4205 #define wqe_nvme_MASK 0x00000001 4206 #define wqe_nvme_WORD word10 4207 #define wqe_oas_SHIFT 6 4208 #define wqe_oas_MASK 0x00000001 4209 #define wqe_oas_WORD word10 4210 #define wqe_lenloc_SHIFT 7 4211 #define wqe_lenloc_MASK 0x00000003 4212 #define wqe_lenloc_WORD word10 4213 #define LPFC_WQE_LENLOC_NONE 0 4214 #define LPFC_WQE_LENLOC_WORD3 1 4215 #define LPFC_WQE_LENLOC_WORD12 2 4216 #define LPFC_WQE_LENLOC_WORD4 3 4217 #define wqe_qosd_SHIFT 9 4218 #define wqe_qosd_MASK 0x00000001 4219 #define wqe_qosd_WORD word10 4220 #define wqe_xbl_SHIFT 11 4221 #define wqe_xbl_MASK 0x00000001 4222 #define wqe_xbl_WORD word10 4223 #define wqe_iod_SHIFT 13 4224 #define wqe_iod_MASK 0x00000001 4225 #define wqe_iod_WORD word10 4226 #define LPFC_WQE_IOD_NONE 0 4227 #define LPFC_WQE_IOD_WRITE 0 4228 #define LPFC_WQE_IOD_READ 1 4229 #define wqe_dbde_SHIFT 14 4230 #define wqe_dbde_MASK 0x00000001 4231 #define wqe_dbde_WORD word10 4232 #define wqe_wqes_SHIFT 15 4233 #define wqe_wqes_MASK 0x00000001 4234 #define wqe_wqes_WORD word10 4235 /* Note that this field overlaps above fields */ 4236 #define wqe_wqid_SHIFT 1 4237 #define wqe_wqid_MASK 0x00007fff 4238 #define wqe_wqid_WORD word10 4239 #define wqe_pri_SHIFT 16 4240 #define wqe_pri_MASK 0x00000007 4241 #define wqe_pri_WORD word10 4242 #define wqe_pv_SHIFT 19 4243 #define wqe_pv_MASK 0x00000001 4244 #define wqe_pv_WORD word10 4245 #define wqe_xc_SHIFT 21 4246 #define wqe_xc_MASK 0x00000001 4247 #define wqe_xc_WORD word10 4248 #define wqe_sr_SHIFT 22 4249 #define wqe_sr_MASK 0x00000001 4250 #define wqe_sr_WORD word10 4251 #define wqe_ccpe_SHIFT 23 4252 #define wqe_ccpe_MASK 0x00000001 4253 #define wqe_ccpe_WORD word10 4254 #define wqe_ccp_SHIFT 24 4255 #define wqe_ccp_MASK 0x000000ff 4256 #define wqe_ccp_WORD word10 4257 uint32_t word11; 4258 #define wqe_cmd_type_SHIFT 0 4259 #define wqe_cmd_type_MASK 0x0000000f 4260 #define wqe_cmd_type_WORD word11 4261 #define wqe_els_id_SHIFT 4 4262 #define wqe_els_id_MASK 0x00000003 4263 #define wqe_els_id_WORD word11 4264 #define LPFC_ELS_ID_FLOGI 3 4265 #define LPFC_ELS_ID_FDISC 2 4266 #define LPFC_ELS_ID_LOGO 1 4267 #define LPFC_ELS_ID_DEFAULT 0 4268 #define wqe_irsp_SHIFT 4 4269 #define wqe_irsp_MASK 0x00000001 4270 #define wqe_irsp_WORD word11 4271 #define wqe_pbde_SHIFT 5 4272 #define wqe_pbde_MASK 0x00000001 4273 #define wqe_pbde_WORD word11 4274 #define wqe_sup_SHIFT 6 4275 #define wqe_sup_MASK 0x00000001 4276 #define wqe_sup_WORD word11 4277 #define wqe_wqec_SHIFT 7 4278 #define wqe_wqec_MASK 0x00000001 4279 #define wqe_wqec_WORD word11 4280 #define wqe_irsplen_SHIFT 8 4281 #define wqe_irsplen_MASK 0x0000000f 4282 #define wqe_irsplen_WORD word11 4283 #define wqe_cqid_SHIFT 16 4284 #define wqe_cqid_MASK 0x0000ffff 4285 #define wqe_cqid_WORD word11 4286 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4287 }; 4288 4289 struct wqe_did { 4290 uint32_t word5; 4291 #define wqe_els_did_SHIFT 0 4292 #define wqe_els_did_MASK 0x00FFFFFF 4293 #define wqe_els_did_WORD word5 4294 #define wqe_xmit_bls_pt_SHIFT 28 4295 #define wqe_xmit_bls_pt_MASK 0x00000003 4296 #define wqe_xmit_bls_pt_WORD word5 4297 #define wqe_xmit_bls_ar_SHIFT 30 4298 #define wqe_xmit_bls_ar_MASK 0x00000001 4299 #define wqe_xmit_bls_ar_WORD word5 4300 #define wqe_xmit_bls_xo_SHIFT 31 4301 #define wqe_xmit_bls_xo_MASK 0x00000001 4302 #define wqe_xmit_bls_xo_WORD word5 4303 }; 4304 4305 struct lpfc_wqe_generic{ 4306 struct ulp_bde64 bde; 4307 uint32_t word3; 4308 uint32_t word4; 4309 uint32_t word5; 4310 struct wqe_common wqe_com; 4311 uint32_t payload[4]; 4312 }; 4313 4314 struct els_request64_wqe { 4315 struct ulp_bde64 bde; 4316 uint32_t payload_len; 4317 uint32_t word4; 4318 #define els_req64_sid_SHIFT 0 4319 #define els_req64_sid_MASK 0x00FFFFFF 4320 #define els_req64_sid_WORD word4 4321 #define els_req64_sp_SHIFT 24 4322 #define els_req64_sp_MASK 0x00000001 4323 #define els_req64_sp_WORD word4 4324 #define els_req64_vf_SHIFT 25 4325 #define els_req64_vf_MASK 0x00000001 4326 #define els_req64_vf_WORD word4 4327 struct wqe_did wqe_dest; 4328 struct wqe_common wqe_com; /* words 6-11 */ 4329 uint32_t word12; 4330 #define els_req64_vfid_SHIFT 1 4331 #define els_req64_vfid_MASK 0x00000FFF 4332 #define els_req64_vfid_WORD word12 4333 #define els_req64_pri_SHIFT 13 4334 #define els_req64_pri_MASK 0x00000007 4335 #define els_req64_pri_WORD word12 4336 uint32_t word13; 4337 #define els_req64_hopcnt_SHIFT 24 4338 #define els_req64_hopcnt_MASK 0x000000ff 4339 #define els_req64_hopcnt_WORD word13 4340 uint32_t word14; 4341 uint32_t max_response_payload_len; 4342 }; 4343 4344 struct xmit_els_rsp64_wqe { 4345 struct ulp_bde64 bde; 4346 uint32_t response_payload_len; 4347 uint32_t word4; 4348 #define els_rsp64_sid_SHIFT 0 4349 #define els_rsp64_sid_MASK 0x00FFFFFF 4350 #define els_rsp64_sid_WORD word4 4351 #define els_rsp64_sp_SHIFT 24 4352 #define els_rsp64_sp_MASK 0x00000001 4353 #define els_rsp64_sp_WORD word4 4354 struct wqe_did wqe_dest; 4355 struct wqe_common wqe_com; /* words 6-11 */ 4356 uint32_t word12; 4357 #define wqe_rsp_temp_rpi_SHIFT 0 4358 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4359 #define wqe_rsp_temp_rpi_WORD word12 4360 uint32_t rsvd_13_15[3]; 4361 }; 4362 4363 struct xmit_bls_rsp64_wqe { 4364 uint32_t payload0; 4365 /* Payload0 for BA_ACC */ 4366 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4367 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4368 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4369 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4370 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4371 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4372 /* Payload0 for BA_RJT */ 4373 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4374 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4375 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4376 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4377 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4378 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4379 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4380 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4381 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4382 uint32_t word1; 4383 #define xmit_bls_rsp64_rxid_SHIFT 0 4384 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4385 #define xmit_bls_rsp64_rxid_WORD word1 4386 #define xmit_bls_rsp64_oxid_SHIFT 16 4387 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4388 #define xmit_bls_rsp64_oxid_WORD word1 4389 uint32_t word2; 4390 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4391 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4392 #define xmit_bls_rsp64_seqcnthi_WORD word2 4393 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4394 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4395 #define xmit_bls_rsp64_seqcntlo_WORD word2 4396 uint32_t rsrvd3; 4397 uint32_t rsrvd4; 4398 struct wqe_did wqe_dest; 4399 struct wqe_common wqe_com; /* words 6-11 */ 4400 uint32_t word12; 4401 #define xmit_bls_rsp64_temprpi_SHIFT 0 4402 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4403 #define xmit_bls_rsp64_temprpi_WORD word12 4404 uint32_t rsvd_13_15[3]; 4405 }; 4406 4407 struct wqe_rctl_dfctl { 4408 uint32_t word5; 4409 #define wqe_si_SHIFT 2 4410 #define wqe_si_MASK 0x000000001 4411 #define wqe_si_WORD word5 4412 #define wqe_la_SHIFT 3 4413 #define wqe_la_MASK 0x000000001 4414 #define wqe_la_WORD word5 4415 #define wqe_xo_SHIFT 6 4416 #define wqe_xo_MASK 0x000000001 4417 #define wqe_xo_WORD word5 4418 #define wqe_ls_SHIFT 7 4419 #define wqe_ls_MASK 0x000000001 4420 #define wqe_ls_WORD word5 4421 #define wqe_dfctl_SHIFT 8 4422 #define wqe_dfctl_MASK 0x0000000ff 4423 #define wqe_dfctl_WORD word5 4424 #define wqe_type_SHIFT 16 4425 #define wqe_type_MASK 0x0000000ff 4426 #define wqe_type_WORD word5 4427 #define wqe_rctl_SHIFT 24 4428 #define wqe_rctl_MASK 0x0000000ff 4429 #define wqe_rctl_WORD word5 4430 }; 4431 4432 struct xmit_seq64_wqe { 4433 struct ulp_bde64 bde; 4434 uint32_t rsvd3; 4435 uint32_t relative_offset; 4436 struct wqe_rctl_dfctl wge_ctl; 4437 struct wqe_common wqe_com; /* words 6-11 */ 4438 uint32_t xmit_len; 4439 uint32_t rsvd_12_15[3]; 4440 }; 4441 struct xmit_bcast64_wqe { 4442 struct ulp_bde64 bde; 4443 uint32_t seq_payload_len; 4444 uint32_t rsvd4; 4445 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4446 struct wqe_common wqe_com; /* words 6-11 */ 4447 uint32_t rsvd_12_15[4]; 4448 }; 4449 4450 struct gen_req64_wqe { 4451 struct ulp_bde64 bde; 4452 uint32_t request_payload_len; 4453 uint32_t relative_offset; 4454 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4455 struct wqe_common wqe_com; /* words 6-11 */ 4456 uint32_t rsvd_12_14[3]; 4457 uint32_t max_response_payload_len; 4458 }; 4459 4460 /* Define NVME PRLI request to fabric. NVME is a 4461 * fabric-only protocol. 4462 * Updated to red-lined v1.08 on Sept 16, 2016 4463 */ 4464 struct lpfc_nvme_prli { 4465 uint32_t word1; 4466 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4467 #define prli_acc_rsp_code_SHIFT 8 4468 #define prli_acc_rsp_code_MASK 0x0000000f 4469 #define prli_acc_rsp_code_WORD word1 4470 #define prli_estabImagePair_SHIFT 13 4471 #define prli_estabImagePair_MASK 0x00000001 4472 #define prli_estabImagePair_WORD word1 4473 #define prli_type_code_ext_SHIFT 16 4474 #define prli_type_code_ext_MASK 0x000000ff 4475 #define prli_type_code_ext_WORD word1 4476 #define prli_type_code_SHIFT 24 4477 #define prli_type_code_MASK 0x000000ff 4478 #define prli_type_code_WORD word1 4479 uint32_t word_rsvd2; 4480 uint32_t word_rsvd3; 4481 uint32_t word4; 4482 #define prli_fba_SHIFT 0 4483 #define prli_fba_MASK 0x00000001 4484 #define prli_fba_WORD word4 4485 #define prli_disc_SHIFT 3 4486 #define prli_disc_MASK 0x00000001 4487 #define prli_disc_WORD word4 4488 #define prli_tgt_SHIFT 4 4489 #define prli_tgt_MASK 0x00000001 4490 #define prli_tgt_WORD word4 4491 #define prli_init_SHIFT 5 4492 #define prli_init_MASK 0x00000001 4493 #define prli_init_WORD word4 4494 #define prli_conf_SHIFT 7 4495 #define prli_conf_MASK 0x00000001 4496 #define prli_conf_WORD word4 4497 uint32_t word5; 4498 #define prli_fb_sz_SHIFT 0 4499 #define prli_fb_sz_MASK 0x0000ffff 4500 #define prli_fb_sz_WORD word5 4501 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4502 }; 4503 4504 struct create_xri_wqe { 4505 uint32_t rsrvd[5]; /* words 0-4 */ 4506 struct wqe_did wqe_dest; /* word 5 */ 4507 struct wqe_common wqe_com; /* words 6-11 */ 4508 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4509 }; 4510 4511 #define T_REQUEST_TAG 3 4512 #define T_XRI_TAG 1 4513 4514 struct abort_cmd_wqe { 4515 uint32_t rsrvd[3]; 4516 uint32_t word3; 4517 #define abort_cmd_ia_SHIFT 0 4518 #define abort_cmd_ia_MASK 0x000000001 4519 #define abort_cmd_ia_WORD word3 4520 #define abort_cmd_criteria_SHIFT 8 4521 #define abort_cmd_criteria_MASK 0x0000000ff 4522 #define abort_cmd_criteria_WORD word3 4523 uint32_t rsrvd4; 4524 uint32_t rsrvd5; 4525 struct wqe_common wqe_com; /* words 6-11 */ 4526 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4527 }; 4528 4529 struct fcp_iwrite64_wqe { 4530 struct ulp_bde64 bde; 4531 uint32_t word3; 4532 #define cmd_buff_len_SHIFT 16 4533 #define cmd_buff_len_MASK 0x00000ffff 4534 #define cmd_buff_len_WORD word3 4535 #define payload_offset_len_SHIFT 0 4536 #define payload_offset_len_MASK 0x0000ffff 4537 #define payload_offset_len_WORD word3 4538 uint32_t total_xfer_len; 4539 uint32_t initial_xfer_len; 4540 struct wqe_common wqe_com; /* words 6-11 */ 4541 uint32_t rsrvd12; 4542 struct ulp_bde64 ph_bde; /* words 13-15 */ 4543 }; 4544 4545 struct fcp_iread64_wqe { 4546 struct ulp_bde64 bde; 4547 uint32_t word3; 4548 #define cmd_buff_len_SHIFT 16 4549 #define cmd_buff_len_MASK 0x00000ffff 4550 #define cmd_buff_len_WORD word3 4551 #define payload_offset_len_SHIFT 0 4552 #define payload_offset_len_MASK 0x0000ffff 4553 #define payload_offset_len_WORD word3 4554 uint32_t total_xfer_len; /* word 4 */ 4555 uint32_t rsrvd5; /* word 5 */ 4556 struct wqe_common wqe_com; /* words 6-11 */ 4557 uint32_t rsrvd12; 4558 struct ulp_bde64 ph_bde; /* words 13-15 */ 4559 }; 4560 4561 struct fcp_icmnd64_wqe { 4562 struct ulp_bde64 bde; /* words 0-2 */ 4563 uint32_t word3; 4564 #define cmd_buff_len_SHIFT 16 4565 #define cmd_buff_len_MASK 0x00000ffff 4566 #define cmd_buff_len_WORD word3 4567 #define payload_offset_len_SHIFT 0 4568 #define payload_offset_len_MASK 0x0000ffff 4569 #define payload_offset_len_WORD word3 4570 uint32_t rsrvd4; /* word 4 */ 4571 uint32_t rsrvd5; /* word 5 */ 4572 struct wqe_common wqe_com; /* words 6-11 */ 4573 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4574 }; 4575 4576 struct fcp_trsp64_wqe { 4577 struct ulp_bde64 bde; 4578 uint32_t response_len; 4579 uint32_t rsvd_4_5[2]; 4580 struct wqe_common wqe_com; /* words 6-11 */ 4581 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4582 }; 4583 4584 struct fcp_tsend64_wqe { 4585 struct ulp_bde64 bde; 4586 uint32_t payload_offset_len; 4587 uint32_t relative_offset; 4588 uint32_t reserved; 4589 struct wqe_common wqe_com; /* words 6-11 */ 4590 uint32_t fcp_data_len; /* word 12 */ 4591 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4592 }; 4593 4594 struct fcp_treceive64_wqe { 4595 struct ulp_bde64 bde; 4596 uint32_t payload_offset_len; 4597 uint32_t relative_offset; 4598 uint32_t reserved; 4599 struct wqe_common wqe_com; /* words 6-11 */ 4600 uint32_t fcp_data_len; /* word 12 */ 4601 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4602 }; 4603 #define TXRDY_PAYLOAD_LEN 12 4604 4605 #define CMD_SEND_FRAME 0xE1 4606 4607 struct send_frame_wqe { 4608 struct ulp_bde64 bde; /* words 0-2 */ 4609 uint32_t frame_len; /* word 3 */ 4610 uint32_t fc_hdr_wd0; /* word 4 */ 4611 uint32_t fc_hdr_wd1; /* word 5 */ 4612 struct wqe_common wqe_com; /* words 6-11 */ 4613 uint32_t fc_hdr_wd2; /* word 12 */ 4614 uint32_t fc_hdr_wd3; /* word 13 */ 4615 uint32_t fc_hdr_wd4; /* word 14 */ 4616 uint32_t fc_hdr_wd5; /* word 15 */ 4617 }; 4618 4619 union lpfc_wqe { 4620 uint32_t words[16]; 4621 struct lpfc_wqe_generic generic; 4622 struct fcp_icmnd64_wqe fcp_icmd; 4623 struct fcp_iread64_wqe fcp_iread; 4624 struct fcp_iwrite64_wqe fcp_iwrite; 4625 struct abort_cmd_wqe abort_cmd; 4626 struct create_xri_wqe create_xri; 4627 struct xmit_bcast64_wqe xmit_bcast64; 4628 struct xmit_seq64_wqe xmit_sequence; 4629 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4630 struct xmit_els_rsp64_wqe xmit_els_rsp; 4631 struct els_request64_wqe els_req; 4632 struct gen_req64_wqe gen_req; 4633 struct fcp_trsp64_wqe fcp_trsp; 4634 struct fcp_tsend64_wqe fcp_tsend; 4635 struct fcp_treceive64_wqe fcp_treceive; 4636 struct send_frame_wqe send_frame; 4637 }; 4638 4639 union lpfc_wqe128 { 4640 uint32_t words[32]; 4641 struct lpfc_wqe_generic generic; 4642 struct fcp_icmnd64_wqe fcp_icmd; 4643 struct fcp_iread64_wqe fcp_iread; 4644 struct fcp_iwrite64_wqe fcp_iwrite; 4645 struct abort_cmd_wqe abort_cmd; 4646 struct create_xri_wqe create_xri; 4647 struct xmit_bcast64_wqe xmit_bcast64; 4648 struct xmit_seq64_wqe xmit_sequence; 4649 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4650 struct xmit_els_rsp64_wqe xmit_els_rsp; 4651 struct els_request64_wqe els_req; 4652 struct gen_req64_wqe gen_req; 4653 struct fcp_trsp64_wqe fcp_trsp; 4654 struct fcp_tsend64_wqe fcp_tsend; 4655 struct fcp_treceive64_wqe fcp_treceive; 4656 struct send_frame_wqe send_frame; 4657 }; 4658 4659 #define MAGIC_NUMER_G6 0xFEAA0003 4660 #define MAGIC_NUMER_G7 0xFEAA0005 4661 4662 struct lpfc_grp_hdr { 4663 uint32_t size; 4664 uint32_t magic_number; 4665 uint32_t word2; 4666 #define lpfc_grp_hdr_file_type_SHIFT 24 4667 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4668 #define lpfc_grp_hdr_file_type_WORD word2 4669 #define lpfc_grp_hdr_id_SHIFT 16 4670 #define lpfc_grp_hdr_id_MASK 0x000000FF 4671 #define lpfc_grp_hdr_id_WORD word2 4672 uint8_t rev_name[128]; 4673 uint8_t date[12]; 4674 uint8_t revision[32]; 4675 }; 4676 4677 /* Defines for WQE command type */ 4678 #define FCP_COMMAND 0x0 4679 #define NVME_READ_CMD 0x0 4680 #define FCP_COMMAND_DATA_OUT 0x1 4681 #define NVME_WRITE_CMD 0x1 4682 #define FCP_COMMAND_TRECEIVE 0x2 4683 #define FCP_COMMAND_TRSP 0x3 4684 #define FCP_COMMAND_TSEND 0x7 4685 #define OTHER_COMMAND 0x8 4686 #define ELS_COMMAND_NON_FIP 0xC 4687 #define ELS_COMMAND_FIP 0xD 4688 4689 #define LPFC_NVME_EMBED_CMD 0x0 4690 #define LPFC_NVME_EMBED_WRITE 0x1 4691 #define LPFC_NVME_EMBED_READ 0x2 4692 4693 /* WQE Commands */ 4694 #define CMD_ABORT_XRI_WQE 0x0F 4695 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4696 #define CMD_XMIT_BCAST64_WQE 0x84 4697 #define CMD_ELS_REQUEST64_WQE 0x8A 4698 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4699 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4700 #define CMD_FCP_IWRITE64_WQE 0x98 4701 #define CMD_FCP_IREAD64_WQE 0x9A 4702 #define CMD_FCP_ICMND64_WQE 0x9C 4703 #define CMD_FCP_TSEND64_WQE 0x9F 4704 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4705 #define CMD_FCP_TRSP64_WQE 0xA3 4706 #define CMD_GEN_REQUEST64_WQE 0xC2 4707 4708 #define CMD_WQE_MASK 0xff 4709 4710 4711 #define LPFC_FW_DUMP 1 4712 #define LPFC_FW_RESET 2 4713 #define LPFC_DV_RESET 3 4714
