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Searched refs:lower_32_bits (Results 1 – 25 of 354) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue_v9.c93 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
95 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
98 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
102 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
140 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
191 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
197 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
289 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_v9()
291 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_v9()
Dkfd_mqd_manager_vi.c102 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
118 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
120 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
130 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
174 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
177 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
179 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
205 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
359 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
361 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_kernel_queue_vi.c109 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
148 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
173 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
176 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
227 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
233 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
324 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
326 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
Dkfd_mqd_manager_v9.c115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
139 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
179 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
182 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
184 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
207 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
359 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
361 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_cik.c104 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
213 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
215 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
258 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
260 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
354 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd_hiq()
395 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
397 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_hiq()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dsi_dma.c60 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in si_dma_ring_set_wptr()
70 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
156 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
175 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in si_dma_start()
229 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
288 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
340 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
341 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
364 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
367 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
[all …]
Dsdma_v2_4.c223 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_ring_set_wptr()
252 sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); in sdma_v2_4_ring_emit_ib()
257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
308 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
310 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
316 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
452 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
460 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_gfx_resume()
613 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
674 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
[all …]
Dvcn_v1_0.c289 lower_32_bits(adev->vcn.gpu_addr)); in vcn_v1_0_mc_resume()
300 lower_32_bits(adev->vcn.gpu_addr + offset)); in vcn_v1_0_mc_resume()
307 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); in vcn_v1_0_mc_resume()
750 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start()
759 lower_32_bits(ring->wptr)); in vcn_v1_0_start()
765 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start()
766 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start()
772 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start()
773 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start()
781 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start()
[all …]
Dcik_sdma.c196 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in cik_sdma_ring_set_wptr()
227 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); in cik_sdma_ring_emit_ib()
278 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
280 amdgpu_ring_write(ring, lower_32_bits(seq)); in cik_sdma_ring_emit_fence()
286 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
484 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in cik_sdma_gfx_resume()
637 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
698 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
753 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pte()
755 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pte()
[all …]
Dsdma_v3_0.c390 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
391 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
395 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
397 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
427 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); in sdma_v3_0_ring_emit_ib()
432 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
483 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
485 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
491 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
692 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
[all …]
Dsdma_v4_0.c339 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr()
351 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr()
354 …WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << … in sdma_v4_0_ring_set_wptr()
385 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); in sdma_v4_0_ring_emit_ib()
390 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
465 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_0_ring_emit_fence()
467 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v4_0_ring_emit_fence()
475 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_0_ring_emit_fence()
655 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v4_0_gfx_resume()
668 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); in sdma_v4_0_gfx_resume()
[all …]
Dvce_v4_0.c108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
109 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
115 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
118 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
121 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
163 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); in vce_v4_0_mmsch_start()
234 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
337 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
338 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
345 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()
[all …]
Duvd_v7_0.c140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
163 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
166 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
667 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); in uvd_v7_0_mc_resume()
673 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
684 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume()
691 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
721 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in uvd_v7_0_mmsch_start()
[all …]
Dvce_v3_0.c154 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
156 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
158 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
282 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
283 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
289 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
290 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
296 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start()
297 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start()
845 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
[all …]
Dvce_v2_0.c94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
244 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
245 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
251 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_start()
252 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_start()
/Linux-v4.19/drivers/pci/controller/dwc/
Dpcie-designware.c114 lower_32_bits(cpu_addr)); in dw_pcie_prog_outbound_atu_unroll()
118 lower_32_bits(cpu_addr + size - 1)); in dw_pcie_prog_outbound_atu_unroll()
120 lower_32_bits(pci_addr)); in dw_pcie_prog_outbound_atu_unroll()
160 lower_32_bits(cpu_addr)); in dw_pcie_prog_outbound_atu()
164 lower_32_bits(cpu_addr + size - 1)); in dw_pcie_prog_outbound_atu()
166 lower_32_bits(pci_addr)); in dw_pcie_prog_outbound_atu()
209 lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu_unroll()
258 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
/Linux-v4.19/include/linux/
Dgoldfish.h16 writel(lower_32_bits(addr), portl); in gf_write_ptr()
26 writel(lower_32_bits(addr), portl); in gf_write_dma_addr()
/Linux-v4.19/drivers/media/pci/pt3/
Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/Linux-v4.19/drivers/pci/controller/
Dpci-xgene.c294 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
298 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
391 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
393 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
395 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
403 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
456 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
459 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
522 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
528 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
/Linux-v4.19/arch/x86/include/asm/
Dmshyperv.h154 u32 input_address_lo = lower_32_bits(input_address); in hv_do_hypercall()
156 u32 output_address_lo = lower_32_bits(output_address); in hv_do_hypercall()
189 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall8()
222 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall16()
224 u32 input2_lo = lower_32_bits(input2); in hv_do_fast_hypercall16()
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_lrc_reg.h53 (reg_state__)[CTX_PDP ## n ## _LDW + 1] = lower_32_bits(addr__); \
60 (reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \
/Linux-v4.19/drivers/gpu/drm/nouveau/
Dnvc0_fence.c38 OUT_RING (chan, lower_32_bits(virtual)); in nvc0_fence_emit32()
54 OUT_RING (chan, lower_32_bits(virtual)); in nvc0_fence_sync32()
/Linux-v4.19/drivers/gpu/drm/radeon/
Dsi_dma.c81 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pages()
82 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pages()
264 radeon_ring_write(ring, lower_32_bits(dst_offset)); in si_copy_dma()
265 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c154 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
155 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
185 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
186 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
/Linux-v4.19/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgv100.c39 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user)); in gv100_fifo_runlist_chan()
41 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid); in gv100_fifo_runlist_chan()

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