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Searched refs:lio_pci_readq (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/net/ethernet/cavium/liquidio/
Dcn68xx_device.c37 lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL)); in lio_cn68xx_set_dpi_regs()
47 lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i))); in lio_cn68xx_set_dpi_regs()
56 lio_pci_readq(oct, CN6XXX_DPI_CTL)); in lio_cn68xx_set_dpi_regs()
119 u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG); in lio_is_210nv()
Dcn66xx_device.c38 lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST); in lio_cn6xxx_soft_reset()
92 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
120 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
130 return ((lio_pci_readq(oct, CN6XXX_MIO_RST_BOOT) >> 24) & 0x3f) * 50; in lio_cn6xxx_coprocessor_clock()
423 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
426 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
436 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
448 return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_read()
Dcn23xx_pf_device.c54 lio_pci_readq(oct, CN23XX_RST_SOFT_RST)); in cn23xx_dump_pf_initialized_regs()
59 lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL)); in cn23xx_dump_pf_initialized_regs()
65 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i))); in cn23xx_dump_pf_initialized_regs()
69 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i))); in cn23xx_dump_pf_initialized_regs()
73 CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL)); in cn23xx_dump_pf_initialized_regs()
84 lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))); in cn23xx_dump_pf_initialized_regs()
218 lio_pci_readq(oct, CN23XX_RST_SOFT_RST); in cn23xx_pf_soft_reset()
276 return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50); in cn23xx_coprocessor_clock()
1049 reg_adr = lio_pci_readq( in cn23xx_bar1_idx_setup()
1054 reg_adr = lio_pci_readq( in cn23xx_bar1_idx_setup()
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Docteon_device.c1327 u64 lio_pci_readq(struct octeon_device *oct, u64 addr) in lio_pci_readq() function
1386 lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL); in octeon_mem_access_ok()
1390 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL); in octeon_mem_access_ok()
Docteon_device.h730 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
Dlio_main.c1608 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP); in liquidio_ptp_adjfreq()
1650 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI); in liquidio_ptp_gettime()
1742 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG); in liquidio_ptp_init()
Dlio_ethtool.c3045 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); in cn6xxx_read_csr_reg()