Searched refs:irq_ena (Results 1 – 4 of 4) sorted by relevance
103 void __iomem *irq_ena; /* irq enable */ member284 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; in __omap_dm_timer_init_regs()291 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; in __omap_dm_timer_init_regs()378 writel_relaxed(value, timer->irq_ena); in __omap_dm_timer_int_enable()
156 if (dcrtc->irq_ena & mask) { in armada_drm_crtc_disable_irq()157 dcrtc->irq_ena &= ~mask; in armada_drm_crtc_disable_irq()158 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_disable_irq()164 if ((dcrtc->irq_ena & mask) != mask) { in armada_drm_crtc_enable_irq()165 dcrtc->irq_ena |= mask; in armada_drm_crtc_enable_irq()166 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_enable_irq()200 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { in armada_drm_crtc_irq()246 v = stat & dcrtc->irq_ena; in armada_drm_irq()750 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; in armada_drm_crtc_create()762 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_create()
64 uint32_t irq_ena; member
107 writel_relaxed(timer->context.tier, timer->irq_ena); in omap_timer_restore_context()717 l = readl_relaxed(timer->irq_ena) & ~mask; in omap_dm_timer_set_int_disable()
