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Searched refs:io_p2v (Results 1 – 25 of 28) sorted by relevance

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/Linux-v4.19/arch/arm/mach-pxa/include/mach/
Dregs-ost.h11 #define OSMR0 io_p2v(0x40A00000) /* */
12 #define OSMR1 io_p2v(0x40A00004) /* */
13 #define OSMR2 io_p2v(0x40A00008) /* */
14 #define OSMR3 io_p2v(0x40A0000C) /* */
15 #define OSMR4 io_p2v(0x40A00080) /* */
16 #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
17 #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
18 #define OMCR4 io_p2v(0x40A000C0) /* */
19 #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
20 #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
[all …]
Dpxa2xx-regs.h137 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
138 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
139 #define CKEN io_p2v(0x41300004) /* Clock Enable Register */
140 #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
Dmtd-xip.h22 #define ICIP io_p2v(0x40d00000)
23 #define ICMR io_p2v(0x40d00004)
Dhardware.h40 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) macro
43 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
54 # define __REG(x) io_p2v(x)
Ddma.h18 #define DMAC_REGS_VIRT io_p2v(0x40000000)
Dpxa3xx-regs.h21 #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
/Linux-v4.19/arch/arm/mach-lpc32xx/include/mach/
Dplatform.h130 #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
585 #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
586 #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
587 #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
588 #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
589 #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
590 #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
595 #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
596 #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
597 #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
[all …]
Dhardware.h31 #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) macro
/Linux-v4.19/arch/arm/mach-sa1100/include/mach/
Dhardware.h35 #define io_p2v( x ) \ macro
40 #define __MREG(x) IOMEM(io_p2v(x))
44 # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
49 # define __REG(x) io_p2v(x)
DSA-1100.h834 #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
835 #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
836 #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
837 #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
838 #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
839 #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
840 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
841 #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
/Linux-v4.19/arch/unicore32/include/mach/
DPKUnity.h34 #define PKUNITY_PCI_BASE io_p2v(0x80000000) /* 0x80000000 - 0xBFFFFFFF 1GB */
46 #define PKUNITY_AHB_BASE io_p2v(0xC0000000)
71 #define PKUNITY_APB_BASE io_p2v(0xEE000000)
Dhardware.h21 #define io_p2v(x) (void __iomem *)((x) - PKUNITY_MMIO_BASE) macro
24 #define io_p2v(x) ((x) - PKUNITY_MMIO_BASE) macro
/Linux-v4.19/arch/arm/mach-netx/
Dxc.c110 writel(val, (void __iomem *)io_p2v(adr)); in xc_patch()
163 memcpy((void *)io_p2v(dst), src, size); in xc_request_firmware()
207 x->xpec_base = (void * __iomem)io_p2v(NETX_PA_XPEC(xcno)); in request_xc()
208 x->xmac_base = (void * __iomem)io_p2v(NETX_PA_XMAC(xcno)); in request_xc()
Dgeneric.c171 vic_init(io_p2v(NETX_PA_VIC), NETX_IRQ_VIC_START, ~0, 0); in netx_init_irq()
/Linux-v4.19/arch/arm/mach-lpc32xx/
Dcommon.c50 iramptr1 = io_p2v(LPC32XX_IRAM_BASE); in lpc32xx_return_iram_size()
51 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE); in lpc32xx_return_iram_size()
Dpm.c132 #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
/Linux-v4.19/arch/arm/mach-netx/include/mach/
Dhardware.h36 #define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT) macro
/Linux-v4.19/arch/arm/mach-pxa/
Dgeneric.c57 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); in pxa_timer_init()
Dirq.c175 pxa_irq_base = io_p2v(0x40d00000); in pxa_init_irq()
260 pxa_irq_base = io_p2v(res.start); in pxa_dt_irq_init()
Dpxa300.c89 mfp_init_base(io_p2v(MFPR_BASE)); in pxa300_init()
Dpxa320.c83 mfp_init_base(io_p2v(MFPR_BASE)); in pxa320_init()
Dpxa27x-udc.h178 #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
Dpxa930.c205 mfp_init_base(io_p2v(MFPR_BASE)); in pxa930_init()
/Linux-v4.19/drivers/tty/serial/
Dnetx-serial.c477 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
490 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
503 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
/Linux-v4.19/arch/arm/mach-ux500/
Ddb8500-regs.h192 #define io_p2v(n) __io_address(n) macro

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