| /Linux-v4.19/arch/arm/mm/ |
| D | cache-fa.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
[all …]
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| D | cache-v6.S | 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
[all …]
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| D | proc-arm926.S | 83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-arm925.S | 123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-mohawk.S | 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-arm920.S | 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | cache-v4wt.S | 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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| D | proc-arm922.S | 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-fa526.S | 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
[all …]
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| D | proc-arm1022.S | 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | proc-arm1026.S | 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | proc-arm946.S | 87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-arm1020e.S | 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
252 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
281 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | tlb-v7.S | 50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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| D | tlb-v6.S | 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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| D | proc-arm1020.S | 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
198 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
258 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
292 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | proc-feroceon.S | 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
191 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
194 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-xsc3.S | 71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
205 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
[all …]
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| D | cache-v4wb.S | 62 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
81 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
168 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
173 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
195 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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| D | tlb-v4wb.S | 41 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
44 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
64 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
65 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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| D | tlb-v4wbi.S | 43 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
44 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
55 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
56 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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| D | cache-v7.S | 78 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
79 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
158 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
191 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
192 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
209 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
210 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
291 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
296 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
297 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
[all …]
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| D | proc-sa1100.S | 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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| D | proc-sa110.S | 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
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| D | proc-v6.S | 156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
208 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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