Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance
86 } interrupt_status_offsets[6] = { { variable3007 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()3013 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()3024 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()3128 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()3129 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
87 } interrupt_status_offsets[6] = { { variable2912 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()2918 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()2929 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()3033 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()3034 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
88 } interrupt_status_offsets[] = { { variable3321 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()3327 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()3339 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()3368 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()3369 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
86 } interrupt_status_offsets[] = { { variable3195 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()3200 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()3212 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()3241 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()3242 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
