| /Linux-v4.19/drivers/irqchip/ |
| D | irq-bcm6345-l1.c | 93 static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, in reg_enable() argument
97 return (1 * intc->n_words - word - 1) * sizeof(u32); in reg_enable()
99 return (0 * intc->n_words + word) * sizeof(u32); in reg_enable()
103 static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, in reg_status() argument
107 return (2 * intc->n_words - word - 1) * sizeof(u32); in reg_status()
109 return (1 * intc->n_words + word) * sizeof(u32); in reg_status()
113 static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, in cpu_for_irq() argument
116 return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); in cpu_for_irq()
121 struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm6345_l1_irq_handle() local
127 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm6345_l1_irq_handle()
[all …]
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| D | irq-bcm7038-l1.c | 77 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc, in reg_status() argument
80 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
83 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc, in reg_mask_status() argument
86 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
89 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc, in reg_mask_set() argument
92 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
95 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc, in reg_mask_clr() argument
98 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
119 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc); in bcm7038_l1_irq_handle() local
125 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
[all …]
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| D | irq-s3c24xx.c | 55 struct s3c_irq_intc *intc; member
89 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask() local
90 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
95 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
97 writel_relaxed(mask, intc->reg_mask); in s3c_irq_mask()
117 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_unmask() local
118 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_unmask()
122 mask = readl_relaxed(intc->reg_mask); in s3c_irq_unmask()
124 writel_relaxed(mask, intc->reg_mask); in s3c_irq_unmask()
136 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_ack() local
[all …]
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| D | irq-bcm2836.c | 31 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
37 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
46 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
73 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); in bcm2836_arm_irqchip_mask_pmu_irq()
78 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET); in bcm2836_arm_irqchip_unmask_pmu_irq()
138 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu); in bcm2836_arm_irqchip_handle_irq()
141 void __iomem *mailbox0 = (intc.base + in bcm2836_arm_irqchip_handle_irq()
152 handle_domain_irq(intc.domain, hwirq, regs); in bcm2836_arm_irqchip_handle_irq()
161 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0; in bcm2836_arm_irqchip_send_ipi()
219 writel(0, intc.base + LOCAL_CONTROL); in bcm2835_init_local_timer_frequency()
[all …]
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| D | irq-ingenic.c | 46 struct ingenic_intc_data *intc = irq_get_handler_data(irq); in intc_cascade() local
50 for (i = 0; i < intc->num_chips; i++) { in intc_cascade()
51 irq_reg = readl(intc->base + (i * CHIP_SIZE) + in intc_cascade()
90 struct ingenic_intc_data *intc; in ingenic_intc_of_init() local
97 intc = kzalloc(sizeof(*intc), GFP_KERNEL); in ingenic_intc_of_init()
98 if (!intc) { in ingenic_intc_of_init()
109 err = irq_set_handler_data(parent_irq, intc); in ingenic_intc_of_init()
113 intc->num_chips = num_chips; in ingenic_intc_of_init()
114 intc->base = of_iomap(node, 0); in ingenic_intc_of_init()
115 if (!intc->base) { in ingenic_intc_of_init()
[all …]
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| D | irq-bcm2835.c | 95 static struct armctrl_ic intc __read_mostly;
102 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
107 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
152 intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), in armctrl_of_init()
154 if (!intc.domain) in armctrl_of_init()
158 intc.pending[b] = base + reg_pending[b]; in armctrl_of_init()
159 intc.enable[b] = base + reg_enable[b]; in armctrl_of_init()
160 intc.disable[b] = base + reg_disable[b]; in armctrl_of_init()
163 irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i)); in armctrl_of_init()
207 u32 stat = readl_relaxed(intc.pending[bank]); in armctrl_translate_bank()
[all …]
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
[all …]
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| D | arm-realview-eb-mp.dtsi | 41 intc: interrupt-controller@1f000100 { label
58 interrupt-parent = <&intc>;
65 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
101 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
[all …]
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| D | mmp2.dtsi | 27 interrupt-parent = <&intc>;
42 intc: interrupt-controller@d4282000 { label
43 compatible = "mrvl,mmp2-intc";
47 mrvl,intc-nr-irqs = <64>;
51 compatible = "mrvl,mmp2-mux-intc";
57 mrvl,intc-nr-irqs = <2>;
61 compatible = "mrvl,mmp2-mux-intc";
67 mrvl,intc-nr-irqs = <2>;
72 compatible = "mrvl,mmp2-mux-intc";
78 mrvl,intc-nr-irqs = <3>;
[all …]
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| D | zynq-7000.dtsi | 48 interrupt-parent = <&intc>;
66 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
84 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
117 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
135 intc: interrupt-controller@f8f01000 { label
180 interrupt-parent = <&intc>;
[all …]
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| /Linux-v4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mrvl,intc.txt | 4 - compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
5 "mrvl,mmp2-mux-intc"
7 If the interrupt controller is intc, address and length means the range
8 of the whold interrupt controller. If the interrupt controller is mux-intc,
9 address and length means one register. Since address of mux-intc is in the
10 range of intc. mux-intc is secondary interrupt controller.
12 only required in mux-intc interrupt controller.
14 only required in mux-intc interrupt controller.
18 - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
24 intc: interrupt-controller@d4282000 {
[all …]
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| D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
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| D | ingenic,intc.txt | 5 - compatible : should be "ingenic,<socname>-intc". Valid strings are:
6 ingenic,jz4740-intc
7 ingenic,jz4725b-intc
8 ingenic,jz4770-intc
9 ingenic,jz4775-intc
10 ingenic,jz4780-intc
19 intc: interrupt-controller@10001000 {
20 compatible = "ingenic,jz4740-intc";
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| D | qca,ath79-misc-intc.txt | 7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
37 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
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| D | ti,omap2-intc.txt | 9 "ti,omap2-intc"
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
16 - reg: physical base address and size of the intc registers map.
20 intc: interrupt-controller@1 {
21 compatible = "ti,omap2-intc";
24 ti,intc-size = <96>;
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| D | amlogic,meson-gpio-intc.txt | 12 - compatible : must have "amlogic,meson8-gpio-intc" and either
13 "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
14 "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
15 "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
16 "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
17 "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
28 compatible = "amlogic,meson-gxbb-gpio-intc",
29 "amlogic,meson-gpio-intc";
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| D | ti,cp-intc.txt | 10 "ti,cp-intc"
16 - ti,intc-size: Number of interrupts handled by the interrupt controller.
17 - reg: physical base address and size of the intc registers map.
21 intc: interrupt-controller@1 {
22 compatible = "ti,cp-intc";
25 ti,intc-size = <101>;
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| /Linux-v4.19/arch/m68k/coldfire/ |
| D | Makefile | 19 obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o
20 obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o
21 obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o
22 obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o
23 obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o
24 obj-$(CONFIG_M525x) += m525x.o timers.o intc.o intc-525x.o reset.o
25 obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o
26 obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o
27 obj-$(CONFIG_M528x) += m528x.o pit.o intc-2.o reset.o
28 obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
[all …]
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| /Linux-v4.19/arch/mips/boot/dts/ingenic/ |
| D | jz4770.dtsi | 17 intc: interrupt-controller@10001000 { label
18 compatible = "ingenic,jz4770-intc";
67 interrupt-parent = <&intc>;
82 interrupt-parent = <&intc>;
97 interrupt-parent = <&intc>;
112 interrupt-parent = <&intc>;
127 interrupt-parent = <&intc>;
142 interrupt-parent = <&intc>;
154 interrupt-parent = <&intc>;
167 interrupt-parent = <&intc>;
[all …]
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| D | jz4780.dtsi | 17 intc: interrupt-controller@10001000 { label
18 compatible = "ingenic,jz4780-intc";
53 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
93 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
153 interrupt-parent = <&intc>;
181 interrupt-parent = <&intc>;
[all …]
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| D | jz4740.dtsi | 16 intc: interrupt-controller@10001000 { label
17 compatible = "ingenic,jz4740-intc";
60 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
115 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
139 interrupt-parent = <&intc>;
150 interrupt-parent = <&intc>;
165 interrupt-parent = <&intc>;
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| /Linux-v4.19/arch/mips/boot/dts/ralink/ |
| D | mt7628a.dtsi | 42 intc: interrupt-controller@200 { label
43 compatible = "ralink,rt2880-intc";
50 reset-names = "intc";
55 ralink,intc-registers = <0x9c 0xa0
72 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
98 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
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| D | rt3050.dtsi | 33 intc: intc@200 { label
34 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
53 interrupt-parent = <&intc>;
64 interrupt-parent = <&intc>;
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