Searched refs:input_clk (Results 1 – 10 of 10) sorted by relevance
| /Linux-v4.19/drivers/i2c/busses/ |
| D | i2c-cadence.c | 160 unsigned long input_clk; member
673 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument
681 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()
692 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()
698 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
785 unsigned long input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb() local
790 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); in cdns_i2c_clk_notifier_cb()
804 id->input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb()
939 id->input_clk = clk_get_rate(id->clk); in cdns_i2c_probe()
949 ret = cdns_i2c_setclk(id->input_clk, id); in cdns_i2c_probe()
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| /Linux-v4.19/Documentation/devicetree/bindings/clock/ |
| D | snps,hsdk-pll-clock.txt | 17 input_clk: input-clk {
27 clocks = <&input_clk>;
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| /Linux-v4.19/drivers/gpu/drm/nouveau/ |
| D | nouveau_led.c | 60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness() local
64 div = input_clk / freq; in nouveau_led_set_brightness()
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| /Linux-v4.19/arch/arc/boot/dts/ |
| D | axc003_idu.dtsi | 27 input_clk: input-clk { label
37 clocks = <&input_clk>;
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| D | axc003.dtsi | 27 input_clk: input-clk { label
37 clocks = <&input_clk>;
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| D | hsdk.dts | 65 input_clk: input-clk { label
120 clocks = <&input_clk>;
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| /Linux-v4.19/drivers/iio/adc/ |
| D | imx7d_adc.c | 280 u32 input_clk = 24000000; in imx7d_adc_get_sample_rate() local
285 analogue_core_clk = input_clk / info->pre_div_num; in imx7d_adc_get_sample_rate()
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| /Linux-v4.19/drivers/media/i2c/ |
| D | ov5670.c | 2446 u32 input_clk = 0; in ov5670_probe() local
2449 device_property_read_u32(&client->dev, "clock-frequency", &input_clk); in ov5670_probe()
2450 if (input_clk != 19200000) in ov5670_probe()
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| /Linux-v4.19/drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 4808 uint32_t input_clk; in smu7_odn_edit_dpm_table() local
4849 input_clk = input[i+1] * 100; in smu7_odn_edit_dpm_table()
4852 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in smu7_odn_edit_dpm_table()
4853 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
4854 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
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| D | vega10_hwmgr.c | 4804 uint32_t input_clk; in vega10_odn_edit_dpm_table() local
4842 input_clk = input[i+1] * 100; in vega10_odn_edit_dpm_table()
4845 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
4846 dpm_table->dpm_levels[input_level].value = input_clk; in vega10_odn_edit_dpm_table()
4847 podn_vdd_dep_table->entries[input_level].clk = input_clk; in vega10_odn_edit_dpm_table()
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