Searched refs:imx_readl (Results 1 – 14 of 14) sorted by relevance
67 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; in tzic_set_irq_fiq()91 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()137 stat = imx_readl(tzic_base + TZIC_HIPND(i)) & in tzic_handle_irq()138 imx_readl(tzic_base + TZIC_INTSEC0(i)); in tzic_handle_irq()166 i = imx_readl(tzic_base + TZIC_INTCNTL); in tzic_init_dt()218 if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0)) in tzic_enable_wake()222 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()
72 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); in avic_set_irq_fiq()76 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); in avic_set_irq_fiq()100 avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); in avic_irq_suspend()165 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; in avic_handle_irq()
60 l = imx_readl(reg); in mxc_iomux_mode()85 l = imx_readl(reg); in mxc_iomux_set_pad()166 l = imx_readl(IOMUXGPR); in mxc_iomux_set_gpr()
156 plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & in mx5_cpu_lp_set()158 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()160 arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & in mx5_cpu_lp_set()162 empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & in mx5_cpu_lp_set()164 empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & in mx5_cpu_lp_set()
23 rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); in mx35_read_cpu_rev()
42 val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); in mx27_read_cpu_rev()
22 cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); in mx27_suspend_enter()
139 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); in imx31_idle()231 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); in imx35_idle()
107 #define imx_readl readl_relaxed macro
47 imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); in imx51_ipu_mipi_setup()
42 srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); in mx31_read_cpu_rev()
59 reg = imx_readl(base + 0x50) & 0x00FFFFFF; in imx_set_aips()
41 return imx_readl(imx_iomuxv1_baseaddr + offset); in imx_iomuxv1_readl()
516 imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30), in armadillo5x0_init()
