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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 26) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/i915/
Di915_perf.c1642 i915_mmio_reg_offset(EU_PERF_CNTL0), in gen8_update_reg_state_unlocked()
1643 i915_mmio_reg_offset(EU_PERF_CNTL1), in gen8_update_reg_state_unlocked()
1644 i915_mmio_reg_offset(EU_PERF_CNTL2), in gen8_update_reg_state_unlocked()
1645 i915_mmio_reg_offset(EU_PERF_CNTL3), in gen8_update_reg_state_unlocked()
1646 i915_mmio_reg_offset(EU_PERF_CNTL4), in gen8_update_reg_state_unlocked()
1647 i915_mmio_reg_offset(EU_PERF_CNTL5), in gen8_update_reg_state_unlocked()
1648 i915_mmio_reg_offset(EU_PERF_CNTL6), in gen8_update_reg_state_unlocked()
1652 reg_state[ctx_oactxctrl] = i915_mmio_reg_offset(GEN8_OACTXCONTROL); in gen8_update_reg_state_unlocked()
1674 if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { in gen8_update_reg_state_unlocked()
1696 i915_mmio_reg_offset(EU_PERF_CNTL0), in gen8_emit_oa_config()
[all …]
Dintel_mocs.c296 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); in emit_mocs_control_table()
309 *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); in emit_mocs_control_table()
354 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); in emit_mocs_l3cc_table()
360 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); in emit_mocs_l3cc_table()
371 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); in emit_mocs_l3cc_table()
Dintel_uncore.h215 readl(base + i915_mmio_reg_offset(reg))
217 writel(value, base + i915_mmio_reg_offset(reg))
Dintel_lrc_reg.h45 (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \
Dintel_lrc.c1429 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1434 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1443 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1510 *batch++ = i915_mmio_reg_offset(lri->reg); in emit_lri()
2008 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); in intel_logical_ring_emit_pdps()
2010 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); in intel_logical_ring_emit_pdps()
2405 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine)); in logical_ring_init()
2407 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine)); in logical_ring_init()
2410 i915_mmio_reg_offset(RING_ELSP(engine)); in logical_ring_init()
2423 i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); in logical_ring_init()
[all …]
Dintel_ringbuffer.c684 *cs++ = i915_mmio_reg_offset(mbox_reg); in gen6_signal()
1494 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); in load_pd_dir()
1498 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); in load_pd_dir()
1517 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); in flush_pd_dir()
1571 *cs++ = i915_mmio_reg_offset( in mi_set_context()
1619 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
1626 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
1657 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3()
Dintel_workarounds.c56 unsigned int addr = i915_mmio_reg_offset(reg); in wa_add()
1022 w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base)); in whitelist_build()
1064 i915_mmio_reg_offset(w->reg[i])); in whitelist_apply()
Dintel_uncore.c928 u32 offset = i915_mmio_reg_offset(*reg); in mmio_reg_cmp()
1083 i915_mmio_reg_offset(reg))) in __unclaimed_reg_debug()
1141 u32 offset = i915_mmio_reg_offset(reg); \
1253 u32 offset = i915_mmio_reg_offset(reg); \
1670 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
2260 u32 offset = i915_mmio_reg_offset(reg); in intel_uncore_forcewake_for_read()
2283 u32 offset = i915_mmio_reg_offset(reg); in intel_uncore_forcewake_for_write()
Dintel_i2c.c296 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); in intel_gpio_setup()
829 i915_mmio_reg_offset(PCH_GPIOA) - in intel_setup_gmbus()
830 i915_mmio_reg_offset(GPIOA); in intel_setup_gmbus()
Di915_cmd_parser.c755 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); in check_sorted()
1018 int ret = addr - i915_mmio_reg_offset(table[mid].addr); in __find_reg()
Dintel_guc.c54 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); in intel_guc_init_send_regs()
Di915_trace.h873 __entry->reg = i915_mmio_reg_offset(reg);
Di915_drv.h3581 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3588 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
Di915_irq.c177 i915_mmio_reg_offset(reg), val); in gen3_assert_iir_is_zero()
193 i915_mmio_reg_offset(reg), val); in gen2_assert_iir_is_zero()
Di915_gem_execbuffer.c1887 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); in i915_reset_gen7_sol_offsets()
Di915_reg.h127 static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg) in i915_mmio_reg_offset() function
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); in i915_mmio_reg_equal()
/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dinterrupt.c154 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
329 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
331 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
357 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
363 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
365 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
411 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
469 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
480 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
486 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
Dedid.c356 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
358 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
381 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
383 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
385 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
387 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
Dscheduler.c87 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
88 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
89 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
90 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
91 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
92 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
109 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
213 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); in save_ring_hw_state()
[all …]
Dmmio_context.c220 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
251 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
278 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
530 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
Dgvt.h445 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
449 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
453 (*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg)))
Dhandlers.c165 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
168 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
523 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { in force_nonpriv_write()
542 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
624 end = i915_mmio_reg_offset(i915_end); in calc_index()
1637 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || in mmio_read_from_hw()
1638 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { in mmio_read_from_hw()
1765 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
3246 if (offset >= i915_mmio_reg_offset(block->offset) && in find_mmio_block()
3247 offset < i915_mmio_reg_offset(block->offset) + block->size) in find_mmio_block()
[all …]
Dcmd_parser.c834 nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); in force_nonpriv_reg_handler()
893 if (offset == i915_mmio_reg_offset(DERRMR) || in cmd_reg_handler()
894 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { in cmd_reg_handler()
949 i915_mmio_reg_offset(DERRMR)) in cmd_handler_lri()
/Linux-v4.19/drivers/gpu/drm/i915/selftests/
Dintel_workarounds.c69 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
94 return i < w->count ? i915_mmio_reg_offset(w->reg[i]) : w->nopid; in get_whitelist_reg()
Dintel_uncore.c78 u32 offset = i915_mmio_reg_offset(*reg); in intel_shadow_table_check()

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