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/Linux-v4.19/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h265 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W() argument
267 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG() argument
287 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R() argument
289 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG() argument
319 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC() argument
321 …ine uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_I… in REG_MDP5_IGC_LUT() argument
323 …uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_I… in REG_MDP5_IGC_LUT_REG() argument
360 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL() argument
374 …atic inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER() argument
376 … inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_REG() argument
[all …]
/Linux-v4.19/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument
321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument
323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument
337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument
339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument
341 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE() argument
353 …tic inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE() argument
355 … inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_OP() argument
375 …e uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_O… in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
377 …e uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_O… in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
[all …]
/Linux-v4.19/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h357 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK() argument
359 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA() argument
571 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN() argument
573 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument
575 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument
577 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2() argument
579 …nline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument
581 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument
583 …c inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument
800 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN() argument
[all …]
Dmmss_cc.xml.h64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0);… in REG_MMSS_CC_CLK() argument
66 …tic inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_CC() argument
83 …tic inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_MD() argument
97 …tic inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0)… in REG_MMSS_CC_CLK_NS() argument
/Linux-v4.19/drivers/gpu/drm/etnaviv/
Dstate.xml.h73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) argument
192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) argument
196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) argument
198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) argument
200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) argument
204 #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) argument
206 #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) argument
208 #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) argument
210 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) argument
214 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) argument
[all …]
/Linux-v4.19/arch/arm64/crypto/
Daes-ce.S50 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3
51 aes\de \i0\().16b, \k\().16b
52 aes\mc \i0\().16b, \i0\().16b
66 .macro round_Nx, enc, k, i0, i1, i2, i3
68 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3
70 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3
75 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3
76 aes\de \i0\().16b, \k\().16b
84 eor \i0\().16b, \i0\().16b, \k2\().16b
95 .macro do_block_Nx, enc, rounds, i0, i1, i2, i3
[all …]
/Linux-v4.19/arch/sparc/lib/
Ddivdi3.S26 cmp %i0,0
33 sub %g0,%i0,%o0
35 mov %o4,%i0
54 cmp %o4,%i0
58 subcc %i0,%o4,%g0
61 sub %i0,%o4,%i0 ! this kills msb of n
62 addx %i0,%i0,%i0 ! so this cannot give carry
65 subcc %i0,%o4,%g0
69 sub %i0,%o4,%i0 ! this kills msb of n
70 4: sub %i0,%o4,%i0
[all …]
Dudivdi3.S29 cmp %o3,%i0
34 subcc %i0,%o3,%g0
37 sub %i0,%o3,%i0 ! this kills msb of n
38 addx %i0,%i0,%i0 ! so this cannot give carry
41 subcc %i0,%o3,%g0
45 sub %i0,%o3,%i0 ! this kills msb of n
46 4: sub %i0,%o3,%i0
47 5: addxcc %i0,%i0,%i0
53 sub %i0,%o3,%i0
61 mov %i0,%o2
[all …]
Dxor.S262 sub %i0, 64, %i0
305 subcc %i0, 64, %i0
364 srlx %i0, 6, %g1
365 mov %i1, %i0
372 ldda [%i0 + 0x00] %asi, %o0 /* %o0/%o1 = dest + 0x00 */
373 ldda [%i0 + 0x10] %asi, %o2 /* %o2/%o3 = dest + 0x10 */
374 ldda [%i0 + 0x20] %asi, %o4 /* %o4/%o5 = dest + 0x20 */
375 ldda [%i0 + 0x30] %asi, %l2 /* %l2/%l3 = dest + 0x30 */
376 prefetch [%i0 + 0x40], #n_writes
379 stxa %o0, [%i0 + 0x00] %asi
[all …]
DNGpage.S33 stxa %o2, [%i0 + 0x00] %asi
34 stxa %o3, [%i0 + 0x08] %asi
35 stxa %o4, [%i0 + 0x10] %asi
36 stxa %o5, [%i0 + 0x18] %asi
37 stxa %l2, [%i0 + 0x20] %asi
38 stxa %l3, [%i0 + 0x28] %asi
39 stxa %l4, [%i0 + 0x30] %asi
40 stxa %l5, [%i0 + 0x38] %asi
45 stxa %o2, [%i0 + 0x40] %asi
46 stxa %o3, [%i0 + 0x48] %asi
[all …]
Dmemcpy.S297 andcc %i0, 3, %g0
299 andcc %i0, 1, %g0
301 andcc %i0, 2, %g0
305 stb %g5, [%i0]
308 add %i0, 1, %i0
312 stb %g3, [%i0]
315 add %i0, 2, %i0
316 stb %g3, [%i0 - 1]
334 add %i0, -8, %i0
340 add %i0, -12, %i0
[all …]
DNGmemcpy.S88 add %i2, %i5, %i0
92 add %i2, %g1, %i0
97 add %i2, %g1, %i0
102 add %i2, %g1, %i0
107 add %i2, %g1, %i0
112 add %i2, %g1, %i0
117 add %i2, %g1, %i0
122 add %i2, %g1, %i0
127 add %i2, %g1, %i0
131 add %i2, %i4, %i0
[all …]
Dmuldi3.S70 mov %i0, %o0
74 mov %l2, %i0
75 add %l2, %l0, %i0
/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da4xx.xml.h968 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT() argument
970 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL() argument
988 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } in REG_A4XX_RB_MRT_BUF_INFO() argument
1021 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE() argument
1023 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL3() argument
1031 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } in REG_A4XX_RB_MRT_BLEND_CONTROL() argument
1534 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP() argument
1536 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MIN() argument
1538 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MAX() argument
1544 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP() argument
[all …]
Da6xx.xml.h385 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH() argument
387 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG() argument
389 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT() argument
391 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG() argument
2157 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } in REG_A6XX_VSC_PIPE_CONFIG() argument
2159 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } in REG_A6XX_VSC_PIPE_CONFIG_REG() argument
2197 static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } in REG_A6XX_VSC_SIZE() argument
2199 static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } in REG_A6XX_VSC_SIZE_REG() argument
2764 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } in REG_A6XX_RB_MRT() argument
2766 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } in REG_A6XX_RB_MRT_CONTROL() argument
[all …]
Da5xx.xml.h1036 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH() argument
1038 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } in REG_A5XX_CP_SCRATCH_REG() argument
1040 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT() argument
1042 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } in REG_A5XX_CP_PROTECT_REG() argument
1977 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } in REG_A5XX_VSC_PIPE_CONFIG() argument
1979 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } in REG_A5XX_VSC_PIPE_CONFIG_REG() argument
2005 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } in REG_A5XX_VSC_PIPE_DATA_ADDRESS() argument
2007 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0;… in REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO() argument
2009 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0;… in REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI() argument
2011 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } in REG_A5XX_VSC_PIPE_DATA_LENGTH() argument
[all …]
Da3xx.xml.h917 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT() argument
919 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } in REG_A3XX_CP_PROTECT_REG() argument
1218 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT() argument
1220 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } in REG_A3XX_RB_MRT_CONTROL() argument
1243 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_INFO() argument
1270 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } in REG_A3XX_RB_MRT_BUF_BASE() argument
1278 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } in REG_A3XX_RB_MRT_BLEND_CONTROL() argument
1859 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK() argument
1861 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0;… in REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE() argument
1863 …ic inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } in REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET() argument
[all …]
Dadreno_pm4.xml.h836 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE_() argument
838 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__0() argument
862 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__1() argument
870 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_CP_SET_DRAW_STATE__2() argument
1516 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A2XX_CP_SET_PSEUDO_REG_() argument
1518 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } in REG_A2XX_CP_SET_PSEUDO_REG__0() argument
1526 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } in REG_A2XX_CP_SET_PSEUDO_REG__1() argument
1534 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } in REG_A2XX_CP_SET_PSEUDO_REG__2() argument
/Linux-v4.19/fs/jffs2/
Dcompr_rubin.c105 long i0, i1; in encode() local
119 i0 = A * rs->p / (A + B); in encode()
120 if (i0 <= 0) in encode()
121 i0 = 1; in encode()
123 if (i0 >= rs->p) in encode()
124 i0 = rs->p - 1; in encode()
126 i1 = rs->p - i0; in encode()
129 rs->p = i0; in encode()
132 rs->q += i0; in encode()
203 long i0, threshold; in decode() local
[all …]
/Linux-v4.19/tools/testing/selftests/proc/
Dproc-uptime-001.c28 uint64_t start, u0, u1, i0, i1; in main() local
34 proc_uptime(fd, &u0, &i0); in main()
39 assert(i1 >= i0); in main()
41 i0 = i1; in main()
Dproc-uptime-002.c48 uint64_t u0, u1, i0, i1; in main() local
63 proc_uptime(fd, &u0, &i0); in main()
73 assert(i1 >= i0); in main()
75 i0 = i1; in main()
/Linux-v4.19/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h171 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } in REG_HDMI_AVI_INFO() argument
175 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } in REG_HDMI_GENERIC0() argument
179 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } in REG_HDMI_GENERIC1() argument
181 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR() argument
183 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } in REG_HDMI_ACR_0() argument
191 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } in REG_HDMI_ACR_1() argument
388 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION() argument
390 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } in REG_HDMI_I2C_TRANSACTION_REG() argument
/Linux-v4.19/arch/sparc/kernel/
Dsyscalls.S157 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
170 srl %i0, 0, %o0
187 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
200 mov %i0, %o0
216 srl %i0, 0, %o0 ! IEU0
227 mov %i0, %l5 ! IEU1
240 mov %i0, %o0 ! IEU0
251 mov %i0, %l5 ! IEU0
/Linux-v4.19/drivers/gpu/drm/msm/edp/
Dedp.xml.h276 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } in REG_EDP_PHY_LN() argument
278 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } in REG_EDP_PHY_LN_PD_CTL() argument
/Linux-v4.19/arch/sparc/include/asm/
Dwinmacro.h21 std %i0, [%reg + RW_I0]; \
32 ldd [%reg + RW_I0], %i0; \
39 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
66 std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \

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