Searched refs:h_addressable (Results 1 – 20 of 20) sorted by relevance
296 uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset; in dce110_timing_generator_program_timing_generator()311 bp_params.h_addressable = in dce110_timing_generator_program_timing_generator()312 patched_crtc_timing.h_addressable; in dce110_timing_generator_program_timing_generator()606 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_program_blanking()665 tmp = tmp + timing->h_addressable + in dce110_timing_generator_program_blanking()1125 h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_validate_timing()1144 h_blank = (timing->h_total - timing->h_addressable - in dce110_timing_generator_validate_timing()1155 timing->h_addressable - in dce110_timing_generator_validate_timing()
252 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()289 tmp = tmp + timing->h_addressable + in dce110_timing_generator_v_program_blanking()
718 timing->h_addressable in dce110_enable_stream()1152 stream->timing.h_addressable in build_audio_output()1864 params.source_view_width = pipe_ctx->stream->timing.h_addressable; in enable_fbc()
828 context->streams[0]->timing.h_addressable, in dce110_validate_bandwidth()
382 params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable); in set_crtc_using_dtd_timing_v3()386 bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()399 bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()
1756 params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable)); in set_crtc_timing_v1()1829 params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable); in set_crtc_using_dtd_timing_v3()1832 cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()1842 cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable)); in set_crtc_using_dtd_timing_v3()
107 vesa_sync_start = patched_crtc_timing.h_addressable + in get_start_vline()215 vesa_sync_start = patched_crtc_timing.h_addressable + in optc1_program_timing()226 patched_crtc_timing.h_addressable + in optc1_program_timing()548 h_blank = (timing->h_total - timing->h_addressable - in optc1_validate_timing()
306 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; in opp1_program_stereo()
425 crtc_timing->h_addressable - crtc_timing->h_border_right; in enc1_stream_encoder_dp_set_stream_attribute()457 crtc_timing->h_addressable + crtc_timing->h_border_right, in enc1_stream_encoder_dp_set_stream_attribute()
163 uint32_t h_addressable; member
725 uint32_t h_addressable; member
440 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce120_timing_generator_program_blanking()468 tmp2 = tmp1 + timing->h_addressable + in dce120_timing_generator_program_blanking()
271 param.windowa_x_end = pipe->stream->timing.h_addressable; in dc_stream_configure_crc()275 param.windowb_x_end = pipe->stream->timing.h_addressable; in dc_stream_configure_crc()949 context->streams[i]->timing.h_addressable, in dc_commit_state_no_check()
339 if (stream1->timing.h_addressable in resource_are_streams_timing_synchronizable()340 != stream2->timing.h_addressable) in resource_are_streams_timing_synchronizable()1077 …pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_… in resource_build_scaling_params()
1816 bool is_vga_mode = (stream->timing.h_addressable == 640) in enable_link_hdmi()
1465 timing->h_addressable == (uint32_t) 640 && in dp_validate_mode_timing()
465 crtc_timing->h_addressable - crtc_timing->h_border_right; in dce110_stream_encoder_dp_set_stream_attribute()501 crtc_timing->h_addressable + crtc_timing->h_border_right, in dce110_stream_encoder_dp_set_stream_attribute()
409 - pipe->stream->timing.h_addressable in pipe_ctx_to_e2e_pipe_params()855 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; in dcn_validate_bandwidth()857 v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable; in dcn_validate_bandwidth()
2955 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable); in populate_initial_data()
2174 dst.width = stream->timing.h_addressable; in update_stream_scaling_settings()2194 dst.x = (stream->timing.h_addressable - dst.width) / 2; in update_stream_scaling_settings()2365 timing_out->h_addressable = mode_in->crtc_hdisplay; in fill_stream_properties_from_drm_display_mode()
