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Searched refs:gvt (Results 1 – 25 of 36) sorted by relevance

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/Linux-v4.19/drivers/gpu/drm/i915/gvt/
Dgvt.c49 static struct intel_vgpu_type *intel_gvt_find_vgpu_type(struct intel_gvt *gvt, in intel_gvt_find_vgpu_type() argument
55 &gvt->dev_priv->drm.pdev->dev); in intel_gvt_find_vgpu_type()
57 for (i = 0; i < gvt->num_types; i++) { in intel_gvt_find_vgpu_type()
58 t = &gvt->types[i]; in intel_gvt_find_vgpu_type()
72 void *gvt = kdev_to_i915(dev)->gvt; in available_instances_show() local
74 type = intel_gvt_find_vgpu_type(gvt, kobject_name(kobj)); in available_instances_show()
93 void *gvt = kdev_to_i915(dev)->gvt; in description_show() local
95 type = intel_gvt_find_vgpu_type(gvt, kobject_name(kobj)); in description_show()
131 static bool intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt) in intel_gvt_init_vgpu_type_groups() argument
137 for (i = 0; i < gvt->num_types; i++) { in intel_gvt_init_vgpu_type_groups()
[all …]
Dvgpu.c106 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) in intel_gvt_init_vgpu_types() argument
124 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in intel_gvt_init_vgpu_types()
125 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in intel_gvt_init_vgpu_types()
128 gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type), in intel_gvt_init_vgpu_types()
130 if (!gvt->types) in intel_gvt_init_vgpu_types()
138 gvt->types[i].low_gm_size = vgpu_types[i].low_mm; in intel_gvt_init_vgpu_types()
139 gvt->types[i].high_gm_size = vgpu_types[i].high_mm; in intel_gvt_init_vgpu_types()
140 gvt->types[i].fence = vgpu_types[i].fence; in intel_gvt_init_vgpu_types()
146 gvt->types[i].weight = vgpu_types[i].weight; in intel_gvt_init_vgpu_types()
147 gvt->types[i].resolution = vgpu_types[i].edid; in intel_gvt_init_vgpu_types()
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Dsched_policy.c42 for_each_engine(engine, vgpu->gvt->dev_priv, i) { in vgpu_has_pending_workload()
68 struct intel_gvt *gvt; member
80 if (!vgpu || vgpu == vgpu->gvt->idle_vgpu) in vgpu_update_timeslice()
132 static void try_to_schedule_next_vgpu(struct intel_gvt *gvt) in try_to_schedule_next_vgpu() argument
134 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in try_to_schedule_next_vgpu()
155 for_each_engine(engine, gvt->dev_priv, i) { in try_to_schedule_next_vgpu()
172 for_each_engine(engine, gvt->dev_priv, i) in try_to_schedule_next_vgpu()
213 struct intel_gvt *gvt = sched_data->gvt; in tbs_sched_func() local
214 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in tbs_sched_func()
233 scheduler->next_vgpu = gvt->idle_vgpu; in tbs_sched_func()
[all …]
Dgvt.h172 struct intel_gvt *gvt; member
347 return i915->gvt; in to_gvt()
360 static inline void intel_gvt_request_service(struct intel_gvt *gvt, in intel_gvt_request_service() argument
363 set_bit(service, (void *)&gvt->service_request); in intel_gvt_request_service()
364 wake_up(&gvt->service_thread_wq); in intel_gvt_request_service()
367 void intel_gvt_free_firmware(struct intel_gvt *gvt);
368 int intel_gvt_load_firmware(struct intel_gvt *gvt);
379 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) argument
380 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start) argument
382 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.vm.total) argument
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Daperture_gm.c42 struct intel_gvt *gvt = vgpu->gvt; in alloc_gm() local
43 struct drm_i915_private *dev_priv = gvt->dev_priv; in alloc_gm()
52 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
53 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
58 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
59 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
78 struct intel_gvt *gvt = vgpu->gvt; in alloc_vgpu_gm() local
79 struct drm_i915_private *dev_priv = gvt->dev_priv; in alloc_vgpu_gm()
106 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in free_vgpu_gm()
127 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_write_fence() local
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Dmmio.c52 #define reg_is_mmio(gvt, reg) \ argument
53 (reg >= 0 && reg < gvt->device_info.mmio_size)
55 #define reg_is_gtt(gvt, reg) \ argument
56 (reg >= gvt->device_info.gtt_start_offset \
57 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
62 struct intel_gvt *gvt = NULL; in failsafe_emulate_mmio_rw() local
69 gvt = vgpu->gvt; in failsafe_emulate_mmio_rw()
72 if (reg_is_mmio(gvt, offset)) { in failsafe_emulate_mmio_rw()
79 } else if (reg_is_gtt(gvt, offset)) { in failsafe_emulate_mmio_rw()
80 offset -= gvt->device_info.gtt_start_offset; in failsafe_emulate_mmio_rw()
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Ddebugfs.c58 static inline int mmio_diff_handler(struct intel_gvt *gvt, in mmio_diff_handler() argument
61 struct drm_i915_private *dev_priv = gvt->dev_priv; in mmio_diff_handler()
88 struct intel_gvt *gvt = vgpu->gvt; in vgpu_mmio_diff_show() local
98 mutex_lock(&gvt->lock); in vgpu_mmio_diff_show()
99 spin_lock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
101 mmio_hw_access_pre(gvt->dev_priv); in vgpu_mmio_diff_show()
103 intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, &param); in vgpu_mmio_diff_show()
104 mmio_hw_access_post(gvt->dev_priv); in vgpu_mmio_diff_show()
106 spin_unlock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
107 mutex_unlock(&gvt->lock); in vgpu_mmio_diff_show()
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Dfirmware.c69 static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data) in mmio_snapshot_handler() argument
71 struct drm_i915_private *dev_priv = gvt->dev_priv; in mmio_snapshot_handler()
77 static int expose_firmware_sysfs(struct intel_gvt *gvt) in expose_firmware_sysfs() argument
79 struct intel_gvt_device_info *info = &gvt->device_info; in expose_firmware_sysfs()
80 struct pci_dev *pdev = gvt->dev_priv->drm.pdev; in expose_firmware_sysfs()
106 memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size); in expose_firmware_sysfs()
111 intel_gvt_for_each_tracked_mmio(gvt, mmio_snapshot_handler, p); in expose_firmware_sysfs()
113 memcpy(gvt->firmware.mmio, p, info->mmio_size); in expose_firmware_sysfs()
129 static void clean_firmware_sysfs(struct intel_gvt *gvt) in clean_firmware_sysfs() argument
131 struct pci_dev *pdev = gvt->dev_priv->drm.pdev; in clean_firmware_sysfs()
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Dgtt.c84 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr), in intel_gvt_ggtt_gmadr_h2g()
88 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr)) in intel_gvt_ggtt_gmadr_h2g()
90 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt)); in intel_gvt_ggtt_gmadr_h2g()
93 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt)); in intel_gvt_ggtt_gmadr_h2g()
299 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in gtt_get_entry64()
312 e->val64 = read_pte64(vgpu->gvt->dev_priv, index); in gtt_get_entry64()
324 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in gtt_set_entry64()
337 write_pte64(vgpu->gvt->dev_priv, index, e->val64); in gtt_set_entry64()
547 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in _ppgtt_get_root_entry()
574 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in _ppgtt_set_root_entry()
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Dscheduler.c82 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; in sr_oa_regs()
125 struct intel_gvt *gvt = vgpu->gvt; in populate_shadow_context() local
138 context_page_num = gvt->dev_priv->engine[ring_id]->context_size; in populate_shadow_context()
142 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) in populate_shadow_context()
208 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in save_ring_hw_state()
224 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, in shadow_context_status_change() local
226 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in shadow_context_status_change()
348 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in intel_gvt_scan_and_shadow_workload()
417 struct intel_gvt *gvt = workload->vgpu->gvt; in prepare_shadow_batch_buffer() local
418 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; in prepare_shadow_batch_buffer()
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Dinterrupt.c147 struct intel_gvt *gvt, in regbase_to_irq_info() argument
150 struct intel_gvt_irq *irq = &gvt->irq; in regbase_to_irq_info()
178 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_imr_handler() local
179 struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_imr_handler()
208 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_master_irq_handler() local
209 struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_master_irq_handler()
247 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_reg_ier_handler() local
248 struct intel_gvt_irq_ops *ops = gvt->irq.ops; in intel_vgpu_reg_ier_handler()
257 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); in intel_vgpu_reg_ier_handler()
285 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, in intel_vgpu_reg_iir_handler()
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Dmmio.h69 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
71 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
72 bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
74 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
75 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
76 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
77 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
96 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
Dsched_policy.h38 int (*init)(struct intel_gvt *gvt);
39 void (*clean)(struct intel_gvt *gvt);
46 void intel_gvt_schedule(struct intel_gvt *gvt);
48 int intel_gvt_init_sched_policy(struct intel_gvt *gvt);
50 void intel_gvt_clean_sched_policy(struct intel_gvt *gvt);
60 void intel_gvt_kick_schedule(struct intel_gvt *gvt);
Ddisplay.c60 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in edp_pipe_is_enabled()
72 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in pipe_is_enabled()
171 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in emulate_monitor_status_change()
358 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) in intel_gvt_check_vblank_emulation() argument
360 struct intel_gvt_irq *irq = &gvt->irq; in intel_gvt_check_vblank_emulation()
365 mutex_lock(&gvt->lock); in intel_gvt_check_vblank_emulation()
366 for_each_active_vgpu(gvt, vgpu, id) { in intel_gvt_check_vblank_emulation()
384 mutex_unlock(&gvt->lock); in intel_gvt_check_vblank_emulation()
389 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in emulate_vblank_on_pipe()
422 for_each_pipe(vgpu->gvt->dev_priv, pipe) in emulate_vblank()
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Dmmio_context.c198 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit() local
200 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
214 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
340 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in handle_tlb_pending_event()
401 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; in switch_mocs()
470 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; in switch_mmio()
476 for (mmio = dev_priv->gvt->engine_mmio_list.mmio; in switch_mmio()
558 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; in intel_gvt_switch_mmio()
575 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) in intel_gvt_init_engine_mmio_context() argument
579 if (IS_SKYLAKE(gvt->dev_priv) || in intel_gvt_init_engine_mmio_context()
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Dcfg_space.c104 if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_read()
293 if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size)) in intel_vgpu_emulate_cfg_write()
349 struct intel_gvt *gvt = vgpu->gvt; in intel_vgpu_init_cfg_space() local
350 const struct intel_gvt_device_info *info = &gvt->device_info; in intel_vgpu_init_cfg_space()
353 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, in intel_vgpu_init_cfg_space()
368 gvt_aperture_pa_base(gvt), true); in intel_vgpu_init_cfg_space()
382 pci_resource_len(gvt->dev_priv->drm.pdev, 0); in intel_vgpu_init_cfg_space()
384 pci_resource_len(gvt->dev_priv->drm.pdev, 2); in intel_vgpu_init_cfg_space()
Dcmd_parser.c483 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
628 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, in find_cmd_entry() argument
633 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { in find_cmd_entry()
641 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt, in get_cmd_info() argument
650 return find_cmd_entry(gvt, opcode, ring_id); in get_cmd_info()
819 struct intel_gvt *gvt = s->vgpu->gvt; in force_nonpriv_reg_handler() local
823 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; in force_nonpriv_reg_handler()
836 if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) && in force_nonpriv_reg_handler()
865 struct intel_gvt *gvt = vgpu->gvt; in cmd_reg_handler() local
868 if (offset + 4 > gvt->device_info.mmio_size) { in cmd_reg_handler()
[all …]
Dhandlers.c50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) in intel_gvt_get_device_type() argument
52 if (IS_BROADWELL(gvt->dev_priv)) in intel_gvt_get_device_type()
54 else if (IS_SKYLAKE(gvt->dev_priv)) in intel_gvt_get_device_type()
56 else if (IS_KABYLAKE(gvt->dev_priv)) in intel_gvt_get_device_type()
58 else if (IS_BROXTON(gvt->dev_priv)) in intel_gvt_get_device_type()
64 bool intel_gvt_match_device(struct intel_gvt *gvt, in intel_gvt_match_device() argument
67 return intel_gvt_get_device_type(gvt) & device; in intel_gvt_match_device()
82 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, in find_mmio_info() argument
87 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { in find_mmio_info()
94 static int new_mmio_info(struct intel_gvt *gvt, in new_mmio_info() argument
[all …]
Dmpt.h53 void *gvt, const void *ops) in intel_gvt_hypervisor_host_init() argument
59 return intel_gvt_host.mpt->host_init(dev, gvt, ops); in intel_gvt_hypervisor_host_init()
66 void *gvt) in intel_gvt_hypervisor_host_exit() argument
72 intel_gvt_host.mpt->host_exit(dev, gvt); in intel_gvt_hypervisor_host_exit()
120 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; in intel_gvt_hypervisor_inject_msi()
Dcmd_parser.h41 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
43 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
Dexeclist.c42 #define execlist_ring_mmio(gvt, ring_id, offset) \ argument
43 (gvt->dev_priv->engine[ring_id]->mmio_base + (offset))
98 u32 status_reg = execlist_ring_mmio(vgpu->gvt, in emulate_execlist_status()
137 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in emulate_csb_update()
139 ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id, in emulate_csb_update()
141 ctx_status_buf_reg = execlist_ring_mmio(vgpu->gvt, ring_id, in emulate_csb_update()
266 u32 status_reg = execlist_ring_mmio(vgpu->gvt, ring_id, in get_next_execlist_slot()
522 ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id, in init_vgpu_execlist()
533 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in clean_execlist()
547 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; in reset_execlist()
DMakefile2 GVT_DIR := gvt
3 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
Dhypercall.h41 int (*host_init)(struct device *dev, void *gvt, const void *ops);
42 void (*host_exit)(struct device *dev, void *gvt);
Dkvmgt.c183 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; in gvt_dma_map_page()
206 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; in gvt_dma_unmap_page()
509 void *gvt; in intel_vgpu_create() local
513 gvt = kdev_to_i915(pdev)->gvt; in intel_vgpu_create()
515 type = intel_gvt_ops->gvt_find_vgpu_type(gvt, kobject_name(kobj)); in intel_vgpu_create()
523 vgpu = intel_gvt_ops->vgpu_create(gvt, type); in intel_vgpu_create()
765 aperture_va = io_mapping_map_wc(&vgpu->gvt->dev_priv->ggtt.iomap, in intel_vgpu_aperture_rw()
834 struct intel_gvt *gvt = vgpu->gvt; in gtt_entry() local
844 return (offset >= gvt->device_info.gtt_start_offset && in gtt_entry()
845 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? in gtt_entry()
[all …]
Ddisplay.h175 void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
176 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);

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