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Searched refs:gpu_write (Results 1 – 15 of 15) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/msm/adreno/
Da3xx_gpu.c84 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
85 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
86 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
87 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
88 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
89 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
90 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
92 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
94 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
96 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
[all …]
Da4xx_gpu.c46 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
48 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
50 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
52 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
54 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
56 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
58 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104); in a4xx_enable_hwcg()
60 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081); in a4xx_enable_hwcg()
61 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); in a4xx_enable_hwcg()
62 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222); in a4xx_enable_hwcg()
[all …]
Da5xx_power.c127 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a5xx_lm_setup()
131 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a5xx_lm_setup()
132 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a5xx_lm_setup()
133 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a5xx_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a5xx_lm_setup()
138 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a5xx_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); in a5xx_lm_setup()
143 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a5xx_lm_setup()
144 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1); in a5xx_lm_setup()
147 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a5xx_lm_setup()
[all …]
Da6xx_gpu.c65 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
245 gpu_write(gpu, a6xx_hwcg[i].offset, in a6xx_set_hwcg()
251 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0); in a6xx_set_hwcg()
330 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); in a6xx_hw_init()
339 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a6xx_hw_init()
345 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a6xx_hw_init()
346 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); in a6xx_hw_init()
349 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); in a6xx_hw_init()
352 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); in a6xx_hw_init()
353 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); in a6xx_hw_init()
[all …]
Da5xx_gpu.c144 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
416 gpu_write(gpu, a5xx_hwcg[i].offset, in a5xx_set_hwcg()
419 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
420 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
611 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
614 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
617 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
625 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11, in a5xx_hw_init()
627 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12, in a5xx_hw_init()
629 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13, in a5xx_hw_init()
[all …]
Da5xx_debugfs.c28 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
43 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
56 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
71 gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); in roq_print()
Da5xx_preempt.c61 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
165 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
Dadreno_gpu.h334 gpu_write(&gpu->base, reg - 1, data); in adreno_gpu_write()
/Linux-v4.19/drivers/gpu/drm/etnaviv/
Detnaviv_iommu.c132 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base); in etnaviv_iommuv1_restore()
133 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base); in etnaviv_iommuv1_restore()
134 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base); in etnaviv_iommuv1_restore()
135 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base); in etnaviv_iommuv1_restore()
136 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base); in etnaviv_iommuv1_restore()
141 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
142 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
143 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
144 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
145 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
Detnaviv_iommu_v2.c245 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
258 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
260 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
262 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
264 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
266 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
268 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
283 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
Detnaviv_gpu.c431 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
433 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
471 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
474 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
487 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
491 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
514 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
551 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
582 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
[all …]
Detnaviv_perfmon.c49 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
65 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read()
66 gpu_write(gpu, domain->profile_config, signal->data); in pipe_reg_read()
73 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read()
Detnaviv_gpu.h154 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/Linux-v4.19/drivers/gpu/drm/msm/
Dmsm_gpu.h216 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function
231 gpu_write(gpu, reg, val | or); in gpu_rmw()
/Linux-v4.19/drivers/gpu/drm/i915/selftests/
Dhuge_pages.c964 static int gpu_write(struct i915_vma *vma, in gpu_write() function
1084 err = gpu_write(vma, ctx, engine, dword, val); in __igt_write_huge()
1522 err = gpu_write(vma, ctx, dev_priv->engine[RCS], 0, 0xdeadbeaf); in igt_ppgtt_pin_update()
1640 err = gpu_write(vma, ctx, i915->engine[RCS], 0, 0xdeadbeaf); in igt_shrink_thp()