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/Linux-v4.19/drivers/clk/tegra/
Dclk-periph-gate.c30 #define read_enb(gate) \ argument
31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
32 #define write_enb_set(val, gate) \ argument
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
34 #define write_enb_clr(val, gate) \ argument
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
37 #define read_rst(gate) \ argument
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39 #define write_rst_clr(val, gate) \ argument
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
[all …]
/Linux-v4.19/drivers/clk/mmp/
Dclk-gate.c29 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); in mmp_clk_gate_enable() local
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
43 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
45 if (gate->flags & MMP_CLK_GATE_NEED_DELAY) { in mmp_clk_gate_enable()
[all …]
/Linux-v4.19/drivers/clk/imx/
Dclk-gate2.c44 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_enable() local
48 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
50 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
53 reg = readl(gate->reg); in clk_gate2_enable()
54 reg &= ~(3 << gate->bit_idx); in clk_gate2_enable()
55 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
56 writel(reg, gate->reg); in clk_gate2_enable()
59 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
66 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_disable() local
70 spin_lock_irqsave(gate->lock, flags); in clk_gate2_disable()
[all …]
Dclk-gate-exclusive.c28 struct clk_gate gate; member
34 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_exclusive_enable() local
35 struct clk_gate_exclusive *exgate = container_of(gate, in clk_gate_exclusive_enable()
36 struct clk_gate_exclusive, gate); in clk_gate_exclusive_enable()
37 u32 val = readl(gate->reg); in clk_gate_exclusive_enable()
65 struct clk_gate *gate; in imx_clk_gate_exclusive() local
75 gate = &exgate->gate; in imx_clk_gate_exclusive()
83 gate->reg = reg; in imx_clk_gate_exclusive()
84 gate->bit_idx = shift; in imx_clk_gate_exclusive()
85 gate->lock = &imx_ccm_lock; in imx_clk_gate_exclusive()
[all …]
/Linux-v4.19/drivers/clk/
Dclk-gate.c44 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_endisable() local
45 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_gate_endisable()
51 if (gate->lock) in clk_gate_endisable()
52 spin_lock_irqsave(gate->lock, flags); in clk_gate_endisable()
54 __acquire(gate->lock); in clk_gate_endisable()
56 if (gate->flags & CLK_GATE_HIWORD_MASK) { in clk_gate_endisable()
57 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
59 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
61 reg = clk_readl(gate->reg); in clk_gate_endisable()
64 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
[all …]
Dclk-aspeed.c213 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_is_enabled() local
214 u32 clk = BIT(gate->clock_idx); in aspeed_clk_is_enabled()
215 u32 rst = BIT(gate->reset_idx); in aspeed_clk_is_enabled()
216 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; in aspeed_clk_is_enabled()
225 if (gate->reset_idx >= 0) { in aspeed_clk_is_enabled()
226 regmap_read(gate->map, ASPEED_RESET_CTRL, &reg); in aspeed_clk_is_enabled()
231 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg); in aspeed_clk_is_enabled()
238 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); in aspeed_clk_enable() local
240 u32 clk = BIT(gate->clock_idx); in aspeed_clk_enable()
241 u32 rst = BIT(gate->reset_idx); in aspeed_clk_enable()
[all …]
/Linux-v4.19/drivers/staging/sm750fb/
Dddk750_power.c75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
94 gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
96 sm750_set_current_gate(gate); in sm750_enable_2d_engine()
101 u32 gate; in sm750_enable_dma() local
104 gate = peek32(CURRENT_GATE); in sm750_enable_dma()
[all …]
/Linux-v4.19/arch/ia64/kernel/
DMakefile.gate4 targets += gate.so gate.lds gate.o gate-dummy.o
6 obj-y += gate-syms.o
13 GATECFLAGS_gate.so = -shared -s -Wl,-soname=linux-gate.so.1 \
15 $(obj)/gate.so: $(obj)/gate.lds $(obj)/gate.o FORCE
16 $(call if_changed,gate)
19 $(obj)/gate-dummy.o: $(obj)/gate.lds $(obj)/gate.o FORCE
20 $(call if_changed,gate)
23 $(obj)/gate-syms.o: $(obj)/gate-dummy.o FORCE
29 $(obj)/gate-data.o: $(obj)/gate.so
/Linux-v4.19/drivers/clk/uniphier/
Dclk-uniphier-gate.c34 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_endisable() local
36 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), in uniphier_clk_gate_endisable()
37 enable ? BIT(gate->bit) : 0); in uniphier_clk_gate_endisable()
53 struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); in uniphier_clk_gate_is_enabled() local
56 if (regmap_read(gate->regmap, gate->reg, &val) < 0) in uniphier_clk_gate_is_enabled()
59 return !!(val & BIT(gate->bit)); in uniphier_clk_gate_is_enabled()
73 struct uniphier_clk_gate *gate; in uniphier_clk_register_gate() local
77 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in uniphier_clk_register_gate()
78 if (!gate) in uniphier_clk_register_gate()
87 gate->regmap = regmap; in uniphier_clk_register_gate()
[all …]
/Linux-v4.19/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
6 quite much similar to the basic gate-clock [2], however,
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
23 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
26 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
28 "ti,composite-gate-clock" - composite gate clock, to be part of composite
[all …]
/Linux-v4.19/drivers/clk/ingenic/
Djz4780-cgu.c348 .gate = { CGU_REG_CLKGR1, 2 },
390 .gate = { CGU_REG_CLKGR0, 3 },
397 .gate = { CGU_REG_CLKGR0, 11 },
404 .gate = { CGU_REG_CLKGR0, 12 },
413 .gate = { CGU_REG_CLKGR0, 24 },
448 .gate = { CGU_REG_CLKGR1, 3 },
457 .gate = { CGU_REG_CLKGR1, 4 },
466 .gate = { CGU_REG_CLKGR1, 9 },
475 .gate = { CGU_REG_CLKGR0, 1 },
483 .gate = { CGU_REG_CLKGR0, 0 },
[all …]
Djz4770-cgu.c157 .gate = { CGU_REG_CLKGR1, 7 },
168 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
183 .gate = { CGU_REG_MSC0CDR, 31 },
190 .gate = { CGU_REG_MSC1CDR, 31 },
197 .gate = { CGU_REG_MSC2CDR, 31 },
204 .gate = { CGU_REG_CLKGR0, 26 },
211 .gate = { CGU_REG_CLKGR0, 24 },
218 .gate = { CGU_REG_CLKGR1, 9 },
225 .gate = { CGU_REG_CLKGR0, 1 },
232 .gate = { CGU_REG_CLKGR0, 28 },
[all …]
/Linux-v4.19/drivers/clk/bcm/
Dclk-kona.c357 __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __is_clk_gate_enabled() argument
363 if (!gate_exists(gate)) in __is_clk_gate_enabled()
366 bit_mask = 1 << gate->status_bit; in __is_clk_gate_enabled()
367 reg_val = __ccu_read(ccu, gate->offset); in __is_clk_gate_enabled()
374 is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in is_clk_gate_enabled() argument
380 if (!gate_exists(gate)) in is_clk_gate_enabled()
384 ret = __is_clk_gate_enabled(ccu, gate); in is_clk_gate_enabled()
395 __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __gate_commit() argument
401 BUG_ON(!gate_exists(gate)); in __gate_commit()
402 if (!gate_is_sw_controllable(gate)) in __gate_commit()
[all …]
Dclk-bcm281xx.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
42 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
51 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
84 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
103 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
115 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
127 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
139 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
151 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
162 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
Dclk-bcm21664.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
41 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
66 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
78 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
90 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
102 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
115 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
120 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
125 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
130 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
/Linux-v4.19/drivers/clk/mediatek/
Dclk-mtk.c123 const struct mtk_gate *gate = &clks[i]; in mtk_clk_register_gates() local
125 if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) in mtk_clk_register_gates()
128 clk = mtk_clk_register_gate(gate->name, gate->parent_name, in mtk_clk_register_gates()
130 gate->regs->set_ofs, in mtk_clk_register_gates()
131 gate->regs->clr_ofs, in mtk_clk_register_gates()
132 gate->regs->sta_ofs, in mtk_clk_register_gates()
133 gate->shift, gate->ops); in mtk_clk_register_gates()
137 gate->name, PTR_ERR(clk)); in mtk_clk_register_gates()
141 clk_data->clks[gate->id] = clk; in mtk_clk_register_gates()
152 struct clk_gate *gate = NULL; in mtk_clk_register_composite() local
[all …]
/Linux-v4.19/drivers/clk/ti/
Dgate.c133 struct clk_hw_omap *gate; in ti_clk_build_component_gate() local
140 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in ti_clk_build_component_gate()
141 if (!gate) in ti_clk_build_component_gate()
144 reg = (struct clk_omap_reg *)&gate->enable_reg; in ti_clk_build_component_gate()
148 gate->enable_bit = setup->bit_shift; in ti_clk_build_component_gate()
156 gate->ops = ops; in ti_clk_build_component_gate()
158 return &gate->hw; in ti_clk_build_component_gate()
205 struct clk_hw_omap *gate; in _of_ti_composite_gate_clk_setup() local
208 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in _of_ti_composite_gate_clk_setup()
209 if (!gate) in _of_ti_composite_gate_clk_setup()
[all …]
/Linux-v4.19/drivers/clk/sunxi/
Dclk-a10-mod1.c33 struct clk_gate *gate; in sun4i_mod1_clk_setup() local
47 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_mod1_clk_setup()
48 if (!gate) in sun4i_mod1_clk_setup()
54 gate->reg = reg; in sun4i_mod1_clk_setup()
55 gate->bit_idx = SUN4I_MOD1_ENABLE; in sun4i_mod1_clk_setup()
56 gate->lock = &mod1_lock; in sun4i_mod1_clk_setup()
65 &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT); in sun4i_mod1_clk_setup()
74 kfree(gate); in sun4i_mod1_clk_setup()
Dclk-a10-hosc.c30 struct clk_gate *gate; in sun4i_osc_clk_setup() local
41 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_osc_clk_setup()
42 if (!gate) in sun4i_osc_clk_setup()
48 gate->reg = of_iomap(node, 0); in sun4i_osc_clk_setup()
49 gate->bit_idx = SUNXI_OSC24M_GATE; in sun4i_osc_clk_setup()
50 gate->lock = &hosc_lock; in sun4i_osc_clk_setup()
57 &gate->hw, &clk_gate_ops, 0); in sun4i_osc_clk_setup()
67 kfree(gate); in sun4i_osc_clk_setup()
Dclk-sun4i-pll3.c33 struct clk_gate *gate; in sun4i_a10_pll3_setup() local
48 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_a10_pll3_setup()
49 if (!gate) in sun4i_a10_pll3_setup()
52 gate->reg = reg; in sun4i_a10_pll3_setup()
53 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup()
54 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
69 &gate->hw, &clk_gate_ops, in sun4i_a10_pll3_setup()
90 kfree(gate); in sun4i_a10_pll3_setup()
Dclk-a20-gmac.c64 struct clk_gate *gate; in sun7i_a20_gmac_clk_setup() local
77 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun7i_a20_gmac_clk_setup()
78 if (!gate) in sun7i_a20_gmac_clk_setup()
90 gate->reg = reg; in sun7i_a20_gmac_clk_setup()
91 gate->bit_idx = SUN7I_A20_GMAC_GPIT; in sun7i_a20_gmac_clk_setup()
92 gate->lock = &gmac_lock; in sun7i_a20_gmac_clk_setup()
102 &gate->hw, &clk_gate_ops, in sun7i_a20_gmac_clk_setup()
115 kfree(gate); in sun7i_a20_gmac_clk_setup()
/Linux-v4.19/drivers/clk/renesas/
Drcar-gen2-cpg.c170 struct clk_gate *gate; in cpg_rcan_clk_register() local
180 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in cpg_rcan_clk_register()
181 if (!gate) { in cpg_rcan_clk_register()
186 gate->reg = base + CPG_RCANCKCR; in cpg_rcan_clk_register()
187 gate->bit_idx = 8; in cpg_rcan_clk_register()
188 gate->flags = CLK_GATE_SET_TO_DISABLE; in cpg_rcan_clk_register()
189 gate->lock = &cpg_lock; in cpg_rcan_clk_register()
193 &gate->hw, &clk_gate_ops, 0); in cpg_rcan_clk_register()
195 kfree(gate); in cpg_rcan_clk_register()
214 struct clk_gate *gate; in cpg_adsp_clk_register() local
[all …]
/Linux-v4.19/drivers/clk/actions/
Dowl-gate.c36 struct owl_gate *gate = hw_to_owl_gate(hw); in owl_gate_disable() local
37 struct owl_clk_common *common = &gate->common; in owl_gate_disable()
39 owl_gate_set(common, &gate->gate_hw, false); in owl_gate_disable()
44 struct owl_gate *gate = hw_to_owl_gate(hw); in owl_gate_enable() local
45 struct owl_clk_common *common = &gate->common; in owl_gate_enable()
47 owl_gate_set(common, &gate->gate_hw, true); in owl_gate_enable()
67 struct owl_gate *gate = hw_to_owl_gate(hw); in owl_gate_is_enabled() local
68 struct owl_clk_common *common = &gate->common; in owl_gate_is_enabled()
70 return owl_gate_clk_is_enabled(common, &gate->gate_hw); in owl_gate_is_enabled()
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
20 - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
[all …]
/Linux-v4.19/arch/arm/boot/dts/
Dsocfpga.dtsi314 compatible = "altr,socfpga-gate-clk";
316 clk-gate = <0x60 0>;
328 compatible = "altr,socfpga-gate-clk";
331 clk-gate = <0x60 1>;
336 compatible = "altr,socfpga-gate-clk";
343 compatible = "altr,socfpga-gate-clk";
346 clk-gate = <0x60 2>;
351 compatible = "altr,socfpga-gate-clk";
354 clk-gate = <0x60 3>;
359 compatible = "altr,socfpga-gate-clk";
[all …]

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