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Searched refs:gart (Results 1 – 25 of 33) sorted by relevance

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/Linux-v4.19/drivers/iommu/
Dtegra-gart.c70 struct gart_device *gart; /* link to gart device */ member
90 #define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG)) argument
92 #define for_each_gart_pte(gart, iova) \ argument
93 for (iova = gart->iovmm_base; \
94 iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
97 static inline void gart_set_pte(struct gart_device *gart, in gart_set_pte() argument
100 writel(offs, gart->regs + GART_ENTRY_ADDR); in gart_set_pte()
101 writel(pte, gart->regs + GART_ENTRY_DATA); in gart_set_pte()
103 dev_dbg(gart->dev, "%s %08lx:%08x\n", in gart_set_pte()
107 static inline unsigned long gart_read_pte(struct gart_device *gart, in gart_read_pte() argument
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DMakefile28 obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
/Linux-v4.19/drivers/gpu/drm/radeon/
Dradeon_gart.c72 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, in radeon_gart_table_ram_alloc()
73 &rdev->gart.table_addr); in radeon_gart_table_ram_alloc()
81 rdev->gart.table_size >> PAGE_SHIFT); in radeon_gart_table_ram_alloc()
84 rdev->gart.ptr = ptr; in radeon_gart_table_ram_alloc()
85 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size); in radeon_gart_table_ram_alloc()
100 if (rdev->gart.ptr == NULL) { in radeon_gart_table_ram_free()
106 set_memory_wb((unsigned long)rdev->gart.ptr, in radeon_gart_table_ram_free()
107 rdev->gart.table_size >> PAGE_SHIFT); in radeon_gart_table_ram_free()
110 pci_free_consistent(rdev->pdev, rdev->gart.table_size, in radeon_gart_table_ram_free()
111 (void *)rdev->gart.ptr, in radeon_gart_table_ram_free()
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Drs400.c80 if (rdev->gart.ptr) { in rs400_gart_init()
103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
161 tmp = (u32)rdev->gart.table_addr & 0xfffff000; in rs400_gart_enable()
162 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; in rs400_gart_enable()
189 (unsigned long long)rdev->gart.table_addr); in rs400_gart_enable()
190 rdev->gart.ready = true; in rs400_gart_enable()
233 u32 *gtt = rdev->gart.ptr; in rs400_gart_set_page()
Dradeon_asic.c165 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
166 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
167 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
171 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
172 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
173 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
207 .gart = {
275 .gart = {
371 .gart = {
439 .gart = {
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Drs600.c538 if (rdev->gart.robj) { in rs600_gart_init()
547 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
556 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
593 rdev->gart.table_addr); in rs600_gart_enable()
610 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
611 rdev->gart.ready = true; in rs600_gart_enable()
651 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
Dr300.c117 void __iomem *ptr = rdev->gart.ptr; in rv370_pcie_gart_set_page()
129 if (rdev->gart.robj) { in rv370_pcie_gart_init()
140 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
141 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in rv370_pcie_gart_init()
142 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in rv370_pcie_gart_init()
143 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in rv370_pcie_gart_init()
153 if (rdev->gart.robj == NULL) { in rv370_pcie_gart_enable()
168 table_addr = rdev->gart.table_addr; in rv370_pcie_gart_enable()
183 rdev->gart.ready = true; in rv370_pcie_gart_enable()
Drv770.c898 if (rdev->gart.robj == NULL) { in rv770_pcie_gart_enable()
927 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
938 (unsigned long long)rdev->gart.table_addr); in rv770_pcie_gart_enable()
939 rdev->gart.ready = true; in rv770_pcie_gart_enable()
Dr100.c639 if (rdev->gart.ptr) { in r100_pci_gart_init()
647 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
648 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
649 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
650 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
665 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
671 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
672 rdev->gart.ready = true; in r100_pci_gart_enable()
695 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
Dradeon_ttm.c1097 if (p >= rdev->gart.num_cpu_pages) in radeon_ttm_gtt_read()
1100 page = rdev->gart.pages[p]; in radeon_ttm_gtt_read()
1106 kunmap(rdev->gart.pages[p]); in radeon_ttm_gtt_read()
Dradeon_vm.c368 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8; in radeon_vm_set_pages()
600 result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT]; in radeon_vm_map_gart()
Dni.c1275 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1304 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1350 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1351 rdev->gart.ready = true; in cayman_pcie_gart_enable()
/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gart.c115 if (adev->gart.robj == NULL) { in amdgpu_gart_table_vram_alloc()
119 bp.size = adev->gart.table_size; in amdgpu_gart_table_vram_alloc()
126 r = amdgpu_bo_create(adev, &bp, &adev->gart.robj); in amdgpu_gart_table_vram_alloc()
148 r = amdgpu_bo_reserve(adev->gart.robj, false); in amdgpu_gart_table_vram_pin()
151 r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gart_table_vram_pin()
153 amdgpu_bo_unreserve(adev->gart.robj); in amdgpu_gart_table_vram_pin()
156 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); in amdgpu_gart_table_vram_pin()
158 amdgpu_bo_unpin(adev->gart.robj); in amdgpu_gart_table_vram_pin()
159 amdgpu_bo_unreserve(adev->gart.robj); in amdgpu_gart_table_vram_pin()
160 adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj); in amdgpu_gart_table_vram_pin()
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Dgmc_v6_0.c499 if (adev->gart.robj == NULL) { in gmc_v6_0_gart_enable()
534 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v6_0_gart_enable()
558 adev->gart.table_addr >> 12); in gmc_v6_0_gart_enable()
561 adev->gart.table_addr >> 12); in gmc_v6_0_gart_enable()
581 (unsigned long long)adev->gart.table_addr); in gmc_v6_0_gart_enable()
582 adev->gart.ready = true; in gmc_v6_0_gart_enable()
590 if (adev->gart.robj) { in gmc_v6_0_gart_init()
597 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v6_0_gart_init()
598 adev->gart.gart_pte_flags = 0; in gmc_v6_0_gart_init()
Dgmc_v7_0.c607 if (adev->gart.robj == NULL) { in gmc_v7_0_gart_enable()
645 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
669 adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
672 adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
699 (unsigned long long)adev->gart.table_addr); in gmc_v7_0_gart_enable()
700 adev->gart.ready = true; in gmc_v7_0_gart_enable()
708 if (adev->gart.robj) { in gmc_v7_0_gart_init()
716 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v7_0_gart_init()
717 adev->gart.gart_pte_flags = 0; in gmc_v7_0_gart_init()
Dgmc_v9_0.c784 if (adev->gart.robj) { in gmc_v9_0_gart_init()
792 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v9_0_gart_init()
793 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | in gmc_v9_0_gart_init()
1010 if (adev->gart.robj == NULL) { in gmc_v9_0_gart_enable()
1054 (unsigned long long)adev->gart.table_addr); in gmc_v9_0_gart_enable()
1055 adev->gart.ready = true; in gmc_v9_0_gart_enable()
Dgmc_v8_0.c812 if (adev->gart.robj == NULL) { in gmc_v8_0_gart_enable()
866 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
890 adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
893 adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
921 (unsigned long long)adev->gart.table_addr); in gmc_v8_0_gart_enable()
922 adev->gart.ready = true; in gmc_v8_0_gart_enable()
930 if (adev->gart.robj) { in gmc_v8_0_gart_init()
938 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v8_0_gart_init()
939 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; in gmc_v8_0_gart_init()
Dgfxhub_v1_0.c42 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); in gfxhub_v1_0_init_gart_pt_regs()
43 value = adev->gart.table_addr - adev->gmc.vram_start in gfxhub_v1_0_init_gart_pt_regs()
Damdgpu_gtt_mgr.c133 lpfn = adev->gart.num_cpu_pages; in amdgpu_gtt_mgr_alloc()
Damdgpu_job.c86 (*job)->vm_pd_addr = adev->gart.table_addr; in amdgpu_job_alloc_with_ib()
Dmmhub_v1_0.c52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); in mmhub_v1_0_init_gart_pt_regs()
53 value = adev->gart.table_addr - adev->gmc.vram_start + in mmhub_v1_0_init_gart_pt_regs()
Damdgpu_ttm.c1450 flags |= adev->gart.gart_pte_flags; in amdgpu_ttm_tt_pte_flags()
1990 dst_addr = adev->gart.table_addr; in amdgpu_map_buffer()
2322 if (p >= adev->gart.num_cpu_pages) in amdgpu_ttm_gtt_read()
2325 page = adev->gart.pages[p]; in amdgpu_ttm_gtt_read()
2331 kunmap(adev->gart.pages[p]); in amdgpu_ttm_gtt_read()
/Linux-v4.19/Documentation/devicetree/bindings/iommu/
Dnvidia,tegra20-gart.txt4 - compatible: "nvidia,tegra20-gart"
10 gart {
11 compatible = "nvidia,tegra20-gart";
/Linux-v4.19/drivers/gpu/drm/nouveau/
Dnouveau_chan.h15 struct nvif_object gart; member
Dnouveau_chan.c98 nvif_object_fini(&chan->gart); in nouveau_channel_del()
330 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) in nouveau_channel_init() argument
391 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, in nouveau_channel_init()
392 &args, sizeof(args), &chan->gart); in nouveau_channel_init()

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