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Searched refs:fb_swap (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/radeon/
Datombios_crtc.c1154 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); in dce4_crtc_do_set_base() local
1203 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); in dce4_crtc_do_set_base()
1211 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); in dce4_crtc_do_set_base()
1219 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); in dce4_crtc_do_set_base()
1226 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); in dce4_crtc_do_set_base()
1234 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); in dce4_crtc_do_set_base()
1242 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); in dce4_crtc_do_set_base()
1252 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); in dce4_crtc_do_set_base()
1392 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1465 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; in avivo_crtc_do_set_base() local
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/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Ddce_v11_0.c1875 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); in dce_v11_0_crtc_do_set_base() local
1926 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
1935 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
1944 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
1981 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v11_0_crtc_do_set_base()
2040 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v11_0_crtc_do_set_base()
Ddce_v10_0.c1833 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); in dce_v10_0_crtc_do_set_base() local
1884 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1893 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1902 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1910 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1919 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1928 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1939 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, in dce_v10_0_crtc_do_set_base()
1998 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v10_0_crtc_do_set_base()
Ddce_v8_0.c1762 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base() local
1813 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1821 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1829 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1836 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1844 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1852 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1862 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); in dce_v8_0_crtc_do_set_base()
1911 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v8_0_crtc_do_set_base()
Ddce_v6_0.c1788 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); in dce_v6_0_crtc_do_set_base() local
1836 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); in dce_v6_0_crtc_do_set_base()
1844 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); in dce_v6_0_crtc_do_set_base()
1852 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); in dce_v6_0_crtc_do_set_base()
1859 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); in dce_v6_0_crtc_do_set_base()
1867 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); in dce_v6_0_crtc_do_set_base()
1875 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); in dce_v6_0_crtc_do_set_base()
1885 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); in dce_v6_0_crtc_do_set_base()
1934 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()