Searched refs:engineClock (Results 1 – 11 of 11) sorted by relevance
254 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; in init_powerplay_table_information()256 …hwmgr->platform_descriptor.overdriveLimit.engineClock = powerplay_table->ODSettingsMax[ATOM_VEGA12… in init_powerplay_table_information()266 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_powerplay_table_information()
417 data->boot_power_level.engineClock = in smu8_construct_boot_state()1310 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()1312 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()1346 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()1563 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()1567 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()1568 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()1591 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()1592 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1]… in smu8_get_current_shallow_sleep_clocks()
100 uint32_t engineClock; member
885 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()1320 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()1321 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()1523 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()3144 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()3175 minimum_clocks.engineClock = stable_pstate_sclk; in vega10_apply_state_adjust_rules()3196 if (sclk < minimum_clocks.engineClock) in vega10_apply_state_adjust_rules()3197 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in vega10_apply_state_adjust_rules()3198 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()4301 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_print_clock_levels()[all …]
796 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in smu7_setup_dpm_tables_v1()797 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()2586 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()2919 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()2942 minimum_clocks.engineClock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()2965 if (sclk < minimum_clocks.engineClock) in smu7_apply_state_adjust_rules()2966 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()2967 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()4477 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in smu7_print_clock_levels()4778 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in smu7_check_clk_voltage_valid()[all …]
993 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()1031 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()1051 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
505 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu10_hwmgr_backend_init()
864 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
261 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
411 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
325 uint32_t engineClock; member
