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Searched refs:dsi_phy_write (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm_8960.c22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_9, in dsi_28nm_dphy_set_timing()
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Ddsi_phy_28nm.c22 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, in dsi_28nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7, in dsi_28nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8, in dsi_28nm_dphy_set_timing()
41 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9, in dsi_28nm_dphy_set_timing()
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Ddsi_phy_20nm.c22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
29 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
31 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
33 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7, in dsi_20nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8, in dsi_20nm_dphy_set_timing()
41 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9, in dsi_20nm_dphy_set_timing()
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Ddsi_phy_10nm.c32 dsi_phy_write(lane_base + in dsi_phy_hw_v3_0_config_lpcdrx()
35 dsi_phy_write(lane_base + in dsi_phy_hw_v3_0_config_lpcdrx()
47 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i), in dsi_phy_hw_v3_0_lane_settings()
54 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0); in dsi_phy_hw_v3_0_lane_settings()
55 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
56 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i), in dsi_phy_hw_v3_0_lane_settings()
64 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
65 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
66 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0); in dsi_phy_hw_v3_0_lane_settings()
67 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i), in dsi_phy_hw_v3_0_lane_settings()
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Ddsi_phy_14nm.c33 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx), in dsi_14nm_dphy_set_timing()
35 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx), in dsi_14nm_dphy_set_timing()
37 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx), in dsi_14nm_dphy_set_timing()
39 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx), in dsi_14nm_dphy_set_timing()
41 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx), in dsi_14nm_dphy_set_timing()
43 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx), in dsi_14nm_dphy_set_timing()
45 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx), in dsi_14nm_dphy_set_timing()
47 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx), in dsi_14nm_dphy_set_timing()
50 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx), in dsi_14nm_dphy_set_timing()
52 dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx), in dsi_14nm_dphy_set_timing()
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Ddsi_phy.h22 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) macro
Ddsi_phy.c389 dsi_phy_write(phy->base + reg, val | bit_mask); in msm_dsi_phy_set_src_pll()
391 dsi_phy_write(phy->base + reg, val & (~bit_mask)); in msm_dsi_phy_set_src_pll()