1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * OWL S900 Pinctrl driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10 */
11
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include "pinctrl-owl.h"
17
18 /* Pinctrl registers offset */
19 #define MFCTL0 (0x0040)
20 #define MFCTL1 (0x0044)
21 #define MFCTL2 (0x0048)
22 #define MFCTL3 (0x004C)
23 #define PAD_PULLCTL0 (0x0060)
24 #define PAD_PULLCTL1 (0x0064)
25 #define PAD_PULLCTL2 (0x0068)
26 #define PAD_ST0 (0x006C)
27 #define PAD_ST1 (0x0070)
28 #define PAD_CTL (0x0074)
29 #define PAD_DRV0 (0x0080)
30 #define PAD_DRV1 (0x0084)
31 #define PAD_DRV2 (0x0088)
32 #define PAD_SR0 (0x0270)
33 #define PAD_SR1 (0x0274)
34 #define PAD_SR2 (0x0278)
35
36 #define OWL_GPIO_PORT_A 0
37 #define OWL_GPIO_PORT_B 1
38 #define OWL_GPIO_PORT_C 2
39 #define OWL_GPIO_PORT_D 3
40 #define OWL_GPIO_PORT_E 4
41 #define OWL_GPIO_PORT_F 5
42
43 #define _GPIOA(offset) (offset)
44 #define _GPIOB(offset) (32 + (offset))
45 #define _GPIOC(offset) (64 + (offset))
46 #define _GPIOD(offset) (76 + (offset))
47 #define _GPIOE(offset) (106 + (offset))
48 #define _GPIOF(offset) (138 + (offset))
49
50 #define NUM_GPIOS (_GPIOF(7) + 1)
51 #define _PIN(offset) (NUM_GPIOS + (offset))
52
53 #define ETH_TXD0 _GPIOA(0)
54 #define ETH_TXD1 _GPIOA(1)
55 #define ETH_TXEN _GPIOA(2)
56 #define ETH_RXER _GPIOA(3)
57 #define ETH_CRS_DV _GPIOA(4)
58 #define ETH_RXD1 _GPIOA(5)
59 #define ETH_RXD0 _GPIOA(6)
60 #define ETH_REF_CLK _GPIOA(7)
61 #define ETH_MDC _GPIOA(8)
62 #define ETH_MDIO _GPIOA(9)
63 #define SIRQ0 _GPIOA(10)
64 #define SIRQ1 _GPIOA(11)
65 #define SIRQ2 _GPIOA(12)
66 #define I2S_D0 _GPIOA(13)
67 #define I2S_BCLK0 _GPIOA(14)
68 #define I2S_LRCLK0 _GPIOA(15)
69 #define I2S_MCLK0 _GPIOA(16)
70 #define I2S_D1 _GPIOA(17)
71 #define I2S_BCLK1 _GPIOA(18)
72 #define I2S_LRCLK1 _GPIOA(19)
73 #define I2S_MCLK1 _GPIOA(20)
74 #define ERAM_A5 _GPIOA(21)
75 #define ERAM_A6 _GPIOA(22)
76 #define ERAM_A7 _GPIOA(23)
77 #define ERAM_A8 _GPIOA(24)
78 #define ERAM_A9 _GPIOA(25)
79 #define ERAM_A10 _GPIOA(26)
80 #define ERAM_A11 _GPIOA(27)
81 #define SD0_D0 _GPIOA(28)
82 #define SD0_D1 _GPIOA(29)
83 #define SD0_D2 _GPIOA(30)
84 #define SD0_D3 _GPIOA(31)
85
86 #define SD1_D0 _GPIOB(0)
87 #define SD1_D1 _GPIOB(1)
88 #define SD1_D2 _GPIOB(2)
89 #define SD1_D3 _GPIOB(3)
90 #define SD0_CMD _GPIOB(4)
91 #define SD0_CLK _GPIOB(5)
92 #define SD1_CMD _GPIOB(6)
93 #define SD1_CLK _GPIOB(7)
94 #define SPI0_SCLK _GPIOB(8)
95 #define SPI0_SS _GPIOB(9)
96 #define SPI0_MISO _GPIOB(10)
97 #define SPI0_MOSI _GPIOB(11)
98 #define UART0_RX _GPIOB(12)
99 #define UART0_TX _GPIOB(13)
100 #define UART2_RX _GPIOB(14)
101 #define UART2_TX _GPIOB(15)
102 #define UART2_RTSB _GPIOB(16)
103 #define UART2_CTSB _GPIOB(17)
104 #define UART4_RX _GPIOB(18)
105 #define UART4_TX _GPIOB(19)
106 #define I2C0_SCLK _GPIOB(20)
107 #define I2C0_SDATA _GPIOB(21)
108 #define I2C1_SCLK _GPIOB(22)
109 #define I2C1_SDATA _GPIOB(23)
110 #define I2C2_SCLK _GPIOB(24)
111 #define I2C2_SDATA _GPIOB(25)
112 #define CSI0_DN0 _GPIOB(26)
113 #define CSI0_DP0 _GPIOB(27)
114 #define CSI0_DN1 _GPIOB(28)
115 #define CSI0_DP1 _GPIOB(29)
116 #define CSI0_CN _GPIOB(30)
117 #define CSI0_CP _GPIOB(31)
118
119 #define CSI0_DN2 _GPIOC(0)
120 #define CSI0_DP2 _GPIOC(1)
121 #define CSI0_DN3 _GPIOC(2)
122 #define CSI0_DP3 _GPIOC(3)
123 #define SENSOR0_PCLK _GPIOC(4)
124 #define CSI1_DN0 _GPIOC(5)
125 #define CSI1_DP0 _GPIOC(6)
126 #define CSI1_DN1 _GPIOC(7)
127 #define CSI1_DP1 _GPIOC(8)
128 #define CSI1_CN _GPIOC(9)
129 #define CSI1_CP _GPIOC(10)
130 #define SENSOR0_CKOUT _GPIOC(11)
131
132 #define LVDS_OEP _GPIOD(0)
133 #define LVDS_OEN _GPIOD(1)
134 #define LVDS_ODP _GPIOD(2)
135 #define LVDS_ODN _GPIOD(3)
136 #define LVDS_OCP _GPIOD(4)
137 #define LVDS_OCN _GPIOD(5)
138 #define LVDS_OBP _GPIOD(6)
139 #define LVDS_OBN _GPIOD(7)
140 #define LVDS_OAP _GPIOD(8)
141 #define LVDS_OAN _GPIOD(9)
142 #define LVDS_EEP _GPIOD(10)
143 #define LVDS_EEN _GPIOD(11)
144 #define LVDS_EDP _GPIOD(12)
145 #define LVDS_EDN _GPIOD(13)
146 #define LVDS_ECP _GPIOD(14)
147 #define LVDS_ECN _GPIOD(15)
148 #define LVDS_EBP _GPIOD(16)
149 #define LVDS_EBN _GPIOD(17)
150 #define LVDS_EAP _GPIOD(18)
151 #define LVDS_EAN _GPIOD(19)
152 #define DSI_DP3 _GPIOD(20)
153 #define DSI_DN3 _GPIOD(21)
154 #define DSI_DP1 _GPIOD(22)
155 #define DSI_DN1 _GPIOD(23)
156 #define DSI_CP _GPIOD(24)
157 #define DSI_CN _GPIOD(25)
158 #define DSI_DP0 _GPIOD(26)
159 #define DSI_DN0 _GPIOD(27)
160 #define DSI_DP2 _GPIOD(28)
161 #define DSI_DN2 _GPIOD(29)
162
163 #define NAND0_D0 _GPIOE(0)
164 #define NAND0_D1 _GPIOE(1)
165 #define NAND0_D2 _GPIOE(2)
166 #define NAND0_D3 _GPIOE(3)
167 #define NAND0_D4 _GPIOE(4)
168 #define NAND0_D5 _GPIOE(5)
169 #define NAND0_D6 _GPIOE(6)
170 #define NAND0_D7 _GPIOE(7)
171 #define NAND0_DQS _GPIOE(8)
172 #define NAND0_DQSN _GPIOE(9)
173 #define NAND0_ALE _GPIOE(10)
174 #define NAND0_CLE _GPIOE(11)
175 #define NAND0_CEB0 _GPIOE(12)
176 #define NAND0_CEB1 _GPIOE(13)
177 #define NAND0_CEB2 _GPIOE(14)
178 #define NAND0_CEB3 _GPIOE(15)
179 #define NAND1_D0 _GPIOE(16)
180 #define NAND1_D1 _GPIOE(17)
181 #define NAND1_D2 _GPIOE(18)
182 #define NAND1_D3 _GPIOE(19)
183 #define NAND1_D4 _GPIOE(20)
184 #define NAND1_D5 _GPIOE(21)
185 #define NAND1_D6 _GPIOE(22)
186 #define NAND1_D7 _GPIOE(23)
187 #define NAND1_DQS _GPIOE(24)
188 #define NAND1_DQSN _GPIOE(25)
189 #define NAND1_ALE _GPIOE(26)
190 #define NAND1_CLE _GPIOE(27)
191 #define NAND1_CEB0 _GPIOE(28)
192 #define NAND1_CEB1 _GPIOE(29)
193 #define NAND1_CEB2 _GPIOE(30)
194 #define NAND1_CEB3 _GPIOE(31)
195
196 #define PCM1_IN _GPIOF(0)
197 #define PCM1_CLK _GPIOF(1)
198 #define PCM1_SYNC _GPIOF(2)
199 #define PCM1_OUT _GPIOF(3)
200 #define UART3_RX _GPIOF(4)
201 #define UART3_TX _GPIOF(5)
202 #define UART3_RTSB _GPIOF(6)
203 #define UART3_CTSB _GPIOF(7)
204
205 /* System */
206 #define SGPIO0 _PIN(0)
207 #define SGPIO1 _PIN(1)
208 #define SGPIO2 _PIN(2)
209 #define SGPIO3 _PIN(3)
210
211 #define NUM_PADS (_PIN(3) + 1)
212
213 /* Pad names as specified in datasheet */
214 static const struct pinctrl_pin_desc s900_pads[] = {
215 PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
216 PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
217 PINCTRL_PIN(ETH_TXEN, "eth_txen"),
218 PINCTRL_PIN(ETH_RXER, "eth_rxer"),
219 PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
220 PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
221 PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
222 PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
223 PINCTRL_PIN(ETH_MDC, "eth_mdc"),
224 PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
225 PINCTRL_PIN(SIRQ0, "sirq0"),
226 PINCTRL_PIN(SIRQ1, "sirq1"),
227 PINCTRL_PIN(SIRQ2, "sirq2"),
228 PINCTRL_PIN(I2S_D0, "i2s_d0"),
229 PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
230 PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
231 PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
232 PINCTRL_PIN(I2S_D1, "i2s_d1"),
233 PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
234 PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
235 PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
236 PINCTRL_PIN(PCM1_IN, "pcm1_in"),
237 PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
238 PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
239 PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
240 PINCTRL_PIN(ERAM_A5, "eram_a5"),
241 PINCTRL_PIN(ERAM_A6, "eram_a6"),
242 PINCTRL_PIN(ERAM_A7, "eram_a7"),
243 PINCTRL_PIN(ERAM_A8, "eram_a8"),
244 PINCTRL_PIN(ERAM_A9, "eram_a9"),
245 PINCTRL_PIN(ERAM_A10, "eram_a10"),
246 PINCTRL_PIN(ERAM_A11, "eram_a11"),
247 PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
248 PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
249 PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
250 PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
251 PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
252 PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
253 PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
254 PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
255 PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
256 PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
257 PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
258 PINCTRL_PIN(LVDS_EEN, "lvds_een"),
259 PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
260 PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
261 PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
262 PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
263 PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
264 PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
265 PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
266 PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
267 PINCTRL_PIN(SD0_D0, "sd0_d0"),
268 PINCTRL_PIN(SD0_D1, "sd0_d1"),
269 PINCTRL_PIN(SD0_D2, "sd0_d2"),
270 PINCTRL_PIN(SD0_D3, "sd0_d3"),
271 PINCTRL_PIN(SD1_D0, "sd1_d0"),
272 PINCTRL_PIN(SD1_D1, "sd1_d1"),
273 PINCTRL_PIN(SD1_D2, "sd1_d2"),
274 PINCTRL_PIN(SD1_D3, "sd1_d3"),
275 PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
276 PINCTRL_PIN(SD0_CLK, "sd0_clk"),
277 PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
278 PINCTRL_PIN(SD1_CLK, "sd1_clk"),
279 PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
280 PINCTRL_PIN(SPI0_SS, "spi0_ss"),
281 PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
282 PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
283 PINCTRL_PIN(UART0_RX, "uart0_rx"),
284 PINCTRL_PIN(UART0_TX, "uart0_tx"),
285 PINCTRL_PIN(UART2_RX, "uart2_rx"),
286 PINCTRL_PIN(UART2_TX, "uart2_tx"),
287 PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
288 PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
289 PINCTRL_PIN(UART3_RX, "uart3_rx"),
290 PINCTRL_PIN(UART3_TX, "uart3_tx"),
291 PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
292 PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
293 PINCTRL_PIN(UART4_RX, "uart4_rx"),
294 PINCTRL_PIN(UART4_TX, "uart4_tx"),
295 PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
296 PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
297 PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
298 PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
299 PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
300 PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
301 PINCTRL_PIN(CSI0_DN0, "csi0_dn0"),
302 PINCTRL_PIN(CSI0_DP0, "csi0_dp0"),
303 PINCTRL_PIN(CSI0_DN1, "csi0_dn1"),
304 PINCTRL_PIN(CSI0_DP1, "csi0_dp1"),
305 PINCTRL_PIN(CSI0_CN, "csi0_cn"),
306 PINCTRL_PIN(CSI0_CP, "csi0_cp"),
307 PINCTRL_PIN(CSI0_DN2, "csi0_dn2"),
308 PINCTRL_PIN(CSI0_DP2, "csi0_dp2"),
309 PINCTRL_PIN(CSI0_DN3, "csi0_dn3"),
310 PINCTRL_PIN(CSI0_DP3, "csi0_dp3"),
311 PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
312 PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
313 PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
314 PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
315 PINCTRL_PIN(DSI_CP, "dsi_cp"),
316 PINCTRL_PIN(DSI_CN, "dsi_cn"),
317 PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
318 PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
319 PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
320 PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
321 PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
322 PINCTRL_PIN(CSI1_DN0, "csi1_dn0"),
323 PINCTRL_PIN(CSI1_DP0, "csi1_dp0"),
324 PINCTRL_PIN(CSI1_DN1, "csi1_dn1"),
325 PINCTRL_PIN(CSI1_DP1, "csi1_dp1"),
326 PINCTRL_PIN(CSI1_CN, "csi1_cn"),
327 PINCTRL_PIN(CSI1_CP, "csi1_cp"),
328 PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
329 PINCTRL_PIN(NAND0_D0, "nand0_d0"),
330 PINCTRL_PIN(NAND0_D1, "nand0_d1"),
331 PINCTRL_PIN(NAND0_D2, "nand0_d2"),
332 PINCTRL_PIN(NAND0_D3, "nand0_d3"),
333 PINCTRL_PIN(NAND0_D4, "nand0_d4"),
334 PINCTRL_PIN(NAND0_D5, "nand0_d5"),
335 PINCTRL_PIN(NAND0_D6, "nand0_d6"),
336 PINCTRL_PIN(NAND0_D7, "nand0_d7"),
337 PINCTRL_PIN(NAND0_DQS, "nand0_dqs"),
338 PINCTRL_PIN(NAND0_DQSN, "nand0_dqsn"),
339 PINCTRL_PIN(NAND0_ALE, "nand0_ale"),
340 PINCTRL_PIN(NAND0_CLE, "nand0_cle"),
341 PINCTRL_PIN(NAND0_CEB0, "nand0_ceb0"),
342 PINCTRL_PIN(NAND0_CEB1, "nand0_ceb1"),
343 PINCTRL_PIN(NAND0_CEB2, "nand0_ceb2"),
344 PINCTRL_PIN(NAND0_CEB3, "nand0_ceb3"),
345 PINCTRL_PIN(NAND1_D0, "nand1_d0"),
346 PINCTRL_PIN(NAND1_D1, "nand1_d1"),
347 PINCTRL_PIN(NAND1_D2, "nand1_d2"),
348 PINCTRL_PIN(NAND1_D3, "nand1_d3"),
349 PINCTRL_PIN(NAND1_D4, "nand1_d4"),
350 PINCTRL_PIN(NAND1_D5, "nand1_d5"),
351 PINCTRL_PIN(NAND1_D6, "nand1_d6"),
352 PINCTRL_PIN(NAND1_D7, "nand1_d7"),
353 PINCTRL_PIN(NAND1_DQS, "nand1_dqs"),
354 PINCTRL_PIN(NAND1_DQSN, "nand1_dqsn"),
355 PINCTRL_PIN(NAND1_ALE, "nand1_ale"),
356 PINCTRL_PIN(NAND1_CLE, "nand1_cle"),
357 PINCTRL_PIN(NAND1_CEB0, "nand1_ceb0"),
358 PINCTRL_PIN(NAND1_CEB1, "nand1_ceb1"),
359 PINCTRL_PIN(NAND1_CEB2, "nand1_ceb2"),
360 PINCTRL_PIN(NAND1_CEB3, "nand1_ceb3"),
361 PINCTRL_PIN(SGPIO0, "sgpio0"),
362 PINCTRL_PIN(SGPIO1, "sgpio1"),
363 PINCTRL_PIN(SGPIO2, "sgpio2"),
364 PINCTRL_PIN(SGPIO3, "sgpio3")
365 };
366
367 enum s900_pinmux_functions {
368 S900_MUX_ERAM,
369 S900_MUX_ETH_RMII,
370 S900_MUX_ETH_SMII,
371 S900_MUX_SPI0,
372 S900_MUX_SPI1,
373 S900_MUX_SPI2,
374 S900_MUX_SPI3,
375 S900_MUX_SENS0,
376 S900_MUX_UART0,
377 S900_MUX_UART1,
378 S900_MUX_UART2,
379 S900_MUX_UART3,
380 S900_MUX_UART4,
381 S900_MUX_UART5,
382 S900_MUX_UART6,
383 S900_MUX_I2S0,
384 S900_MUX_I2S1,
385 S900_MUX_PCM0,
386 S900_MUX_PCM1,
387 S900_MUX_JTAG,
388 S900_MUX_PWM0,
389 S900_MUX_PWM1,
390 S900_MUX_PWM2,
391 S900_MUX_PWM3,
392 S900_MUX_PWM4,
393 S900_MUX_PWM5,
394 S900_MUX_SD0,
395 S900_MUX_SD1,
396 S900_MUX_SD2,
397 S900_MUX_SD3,
398 S900_MUX_I2C0,
399 S900_MUX_I2C1,
400 S900_MUX_I2C2,
401 S900_MUX_I2C3,
402 S900_MUX_I2C4,
403 S900_MUX_I2C5,
404 S900_MUX_LVDS,
405 S900_MUX_USB20,
406 S900_MUX_USB30,
407 S900_MUX_GPU,
408 S900_MUX_MIPI_CSI0,
409 S900_MUX_MIPI_CSI1,
410 S900_MUX_MIPI_DSI,
411 S900_MUX_NAND0,
412 S900_MUX_NAND1,
413 S900_MUX_SPDIF,
414 S900_MUX_SIRQ0,
415 S900_MUX_SIRQ1,
416 S900_MUX_SIRQ2,
417 S900_MUX_AUX_START,
418 S900_MUX_MAX,
419 S900_MUX_RESERVED
420 };
421
422 /* mfp0_22 */
423 static unsigned int lvds_oxx_uart4_mfp_pads[] = { LVDS_OAP, LVDS_OAN };
424 static unsigned int lvds_oxx_uart4_mfp_funcs[] = { S900_MUX_ERAM,
425 S900_MUX_UART4 };
426 /* mfp0_21_20 */
427 static unsigned int rmii_mdc_mfp_pads[] = { ETH_MDC };
428 static unsigned int rmii_mdc_mfp_funcs[] = { S900_MUX_ETH_RMII,
429 S900_MUX_PWM2,
430 S900_MUX_UART2,
431 S900_MUX_RESERVED };
432 static unsigned int rmii_mdio_mfp_pads[] = { ETH_MDIO };
433 static unsigned int rmii_mdio_mfp_funcs[] = { S900_MUX_ETH_RMII,
434 S900_MUX_PWM3,
435 S900_MUX_UART2,
436 S900_MUX_RESERVED };
437 /* mfp0_19 */
438 static unsigned int sirq0_mfp_pads[] = { SIRQ0 };
439 static unsigned int sirq0_mfp_funcs[] = { S900_MUX_SIRQ0,
440 S900_MUX_PWM0 };
441 static unsigned int sirq1_mfp_pads[] = { SIRQ1 };
442 static unsigned int sirq1_mfp_funcs[] = { S900_MUX_SIRQ1,
443 S900_MUX_PWM1 };
444 /* mfp0_18_16 */
445 static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };
446 static unsigned int rmii_txd0_mfp_funcs[] = { S900_MUX_ETH_RMII,
447 S900_MUX_ETH_SMII,
448 S900_MUX_SPI2,
449 S900_MUX_UART6,
450 S900_MUX_SENS0,
451 S900_MUX_PWM0 };
452 static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };
453 static unsigned int rmii_txd1_mfp_funcs[] = { S900_MUX_ETH_RMII,
454 S900_MUX_ETH_SMII,
455 S900_MUX_SPI2,
456 S900_MUX_UART6,
457 S900_MUX_SENS0,
458 S900_MUX_PWM1 };
459 /* mfp0_15_13 */
460 static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };
461 static unsigned int rmii_txen_mfp_funcs[] = { S900_MUX_ETH_RMII,
462 S900_MUX_UART2,
463 S900_MUX_SPI3,
464 S900_MUX_RESERVED,
465 S900_MUX_RESERVED,
466 S900_MUX_PWM2,
467 S900_MUX_SENS0 };
468
469 static unsigned int rmii_rxer_mfp_pads[] = { ETH_RXER };
470 static unsigned int rmii_rxer_mfp_funcs[] = { S900_MUX_ETH_RMII,
471 S900_MUX_UART2,
472 S900_MUX_SPI3,
473 S900_MUX_RESERVED,
474 S900_MUX_RESERVED,
475 S900_MUX_PWM3,
476 S900_MUX_SENS0 };
477 /* mfp0_12_11 */
478 static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };
479 static unsigned int rmii_crs_dv_mfp_funcs[] = { S900_MUX_ETH_RMII,
480 S900_MUX_ETH_SMII,
481 S900_MUX_SPI2,
482 S900_MUX_UART4 };
483 /* mfp0_10_8 */
484 static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };
485 static unsigned int rmii_rxd1_mfp_funcs[] = { S900_MUX_ETH_RMII,
486 S900_MUX_UART2,
487 S900_MUX_SPI3,
488 S900_MUX_RESERVED,
489 S900_MUX_UART5,
490 S900_MUX_PWM0,
491 S900_MUX_SENS0 };
492 static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };
493 static unsigned int rmii_rxd0_mfp_funcs[] = { S900_MUX_ETH_RMII,
494 S900_MUX_UART2,
495 S900_MUX_SPI3,
496 S900_MUX_RESERVED,
497 S900_MUX_UART5,
498 S900_MUX_PWM1,
499 S900_MUX_SENS0 };
500 /* mfp0_7_6 */
501 static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
502 static unsigned int rmii_ref_clk_mfp_funcs[] = { S900_MUX_ETH_RMII,
503 S900_MUX_UART4,
504 S900_MUX_SPI2,
505 S900_MUX_RESERVED };
506 /* mfp0_5 */
507 static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
508 static unsigned int i2s_d0_mfp_funcs[] = { S900_MUX_I2S0,
509 S900_MUX_PCM0 };
510 static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
511 static unsigned int i2s_d1_mfp_funcs[] = { S900_MUX_I2S1,
512 S900_MUX_PCM0 };
513
514 /* mfp0_4_3 */
515 static unsigned int i2s_lr_m_clk0_mfp_pads[] = { I2S_LRCLK0,
516 I2S_MCLK0 };
517 static unsigned int i2s_lr_m_clk0_mfp_funcs[] = { S900_MUX_I2S0,
518 S900_MUX_PCM0,
519 S900_MUX_PCM1,
520 S900_MUX_RESERVED };
521 /* mfp0_2 */
522 static unsigned int i2s_bclk0_mfp_pads[] = { I2S_BCLK0 };
523 static unsigned int i2s_bclk0_mfp_funcs[] = { S900_MUX_I2S0,
524 S900_MUX_PCM0 };
525 static unsigned int i2s_bclk1_mclk1_mfp_pads[] = { I2S_BCLK1,
526 I2S_LRCLK1,
527 I2S_MCLK1 };
528 static unsigned int i2s_bclk1_mclk1_mfp_funcs[] = { S900_MUX_I2S1,
529 S900_MUX_PCM0 };
530 /* mfp0_1_0 */
531 static unsigned int pcm1_in_out_mfp_pads[] = { PCM1_IN,
532 PCM1_OUT };
533 static unsigned int pcm1_in_out_mfp_funcs[] = { S900_MUX_PCM1,
534 S900_MUX_SPI1,
535 S900_MUX_I2C3,
536 S900_MUX_UART4 };
537 static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
538 static unsigned int pcm1_clk_mfp_funcs[] = { S900_MUX_PCM1,
539 S900_MUX_SPI1,
540 S900_MUX_PWM4,
541 S900_MUX_UART4 };
542 static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
543 static unsigned int pcm1_sync_mfp_funcs[] = { S900_MUX_PCM1,
544 S900_MUX_SPI1,
545 S900_MUX_PWM5,
546 S900_MUX_UART4 };
547 /* mfp1_31_29 */
548 static unsigned int eram_a5_mfp_pads[] = { ERAM_A5 };
549 static unsigned int eram_a5_mfp_funcs[] = { S900_MUX_UART4,
550 S900_MUX_JTAG,
551 S900_MUX_ERAM,
552 S900_MUX_PWM0,
553 S900_MUX_RESERVED,
554 S900_MUX_SENS0 };
555 static unsigned int eram_a6_mfp_pads[] = { ERAM_A6 };
556 static unsigned int eram_a6_mfp_funcs[] = { S900_MUX_UART4,
557 S900_MUX_JTAG,
558 S900_MUX_ERAM,
559 S900_MUX_PWM1,
560 S900_MUX_RESERVED,
561 S900_MUX_SENS0,
562 };
563 static unsigned int eram_a7_mfp_pads[] = { ERAM_A7 };
564 static unsigned int eram_a7_mfp_funcs[] = { S900_MUX_RESERVED,
565 S900_MUX_JTAG,
566 S900_MUX_ERAM,
567 S900_MUX_RESERVED,
568 S900_MUX_RESERVED,
569 S900_MUX_SENS0 };
570 /* mfp1_28_26 */
571 static unsigned int eram_a8_mfp_pads[] = { ERAM_A8 };
572 static unsigned int eram_a8_mfp_funcs[] = { S900_MUX_RESERVED,
573 S900_MUX_JTAG,
574 S900_MUX_ERAM,
575 S900_MUX_PWM1,
576 S900_MUX_RESERVED,
577 S900_MUX_SENS0 };
578 static unsigned int eram_a9_mfp_pads[] = { ERAM_A9 };
579 static unsigned int eram_a9_mfp_funcs[] = { S900_MUX_USB20,
580 S900_MUX_UART5,
581 S900_MUX_ERAM,
582 S900_MUX_PWM2,
583 S900_MUX_RESERVED,
584 S900_MUX_SENS0 };
585 static unsigned int eram_a10_mfp_pads[] = { ERAM_A10 };
586 static unsigned int eram_a10_mfp_funcs[] = { S900_MUX_USB30,
587 S900_MUX_JTAG,
588 S900_MUX_ERAM,
589 S900_MUX_PWM3,
590 S900_MUX_RESERVED,
591 S900_MUX_SENS0,
592 S900_MUX_RESERVED,
593 S900_MUX_RESERVED };
594 /* mfp1_25_23 */
595 static unsigned int eram_a11_mfp_pads[] = { ERAM_A11 };
596 static unsigned int eram_a11_mfp_funcs[] = { S900_MUX_RESERVED,
597 S900_MUX_RESERVED,
598 S900_MUX_ERAM,
599 S900_MUX_PWM2,
600 S900_MUX_UART5,
601 S900_MUX_RESERVED,
602 S900_MUX_SENS0,
603 S900_MUX_RESERVED };
604 /* mfp1_22 */
605 static unsigned int lvds_oep_odn_mfp_pads[] = { LVDS_OEP,
606 LVDS_OEN,
607 LVDS_ODP,
608 LVDS_ODN };
609 static unsigned int lvds_oep_odn_mfp_funcs[] = { S900_MUX_LVDS,
610 S900_MUX_UART2 };
611 static unsigned int lvds_ocp_obn_mfp_pads[] = { LVDS_OCP,
612 LVDS_OCN,
613 LVDS_OBP,
614 LVDS_OBN };
615 static unsigned int lvds_ocp_obn_mfp_funcs[] = { S900_MUX_LVDS,
616 S900_MUX_PCM1 };
617 static unsigned int lvds_oap_oan_mfp_pads[] = { LVDS_OAP,
618 LVDS_OAN };
619 static unsigned int lvds_oap_oan_mfp_funcs[] = { S900_MUX_LVDS,
620 S900_MUX_ERAM };
621 /* mfp1_21 */
622 static unsigned int lvds_e_mfp_pads[] = { LVDS_EEP,
623 LVDS_EEN,
624 LVDS_EDP,
625 LVDS_EDN,
626 LVDS_ECP,
627 LVDS_ECN,
628 LVDS_EBP,
629 LVDS_EBN,
630 LVDS_EAP,
631 LVDS_EAN };
632 static unsigned int lvds_e_mfp_funcs[] = { S900_MUX_LVDS,
633 S900_MUX_ERAM };
634 /* mfp1_5_4 */
635 static unsigned int spi0_sclk_mosi_mfp_pads[] = { SPI0_SCLK,
636 SPI0_MOSI };
637 static unsigned int spi0_sclk_mosi_mfp_funcs[] = { S900_MUX_SPI0,
638 S900_MUX_ERAM,
639 S900_MUX_I2C3,
640 S900_MUX_PCM0 };
641 /* mfp1_3_1 */
642 static unsigned int spi0_ss_mfp_pads[] = { SPI0_SS };
643 static unsigned int spi0_ss_mfp_funcs[] = { S900_MUX_SPI0,
644 S900_MUX_ERAM,
645 S900_MUX_I2S1,
646 S900_MUX_PCM1,
647 S900_MUX_PCM0,
648 S900_MUX_PWM4 };
649 static unsigned int spi0_miso_mfp_pads[] = { SPI0_MISO };
650 static unsigned int spi0_miso_mfp_funcs[] = { S900_MUX_SPI0,
651 S900_MUX_ERAM,
652 S900_MUX_I2S1,
653 S900_MUX_PCM1,
654 S900_MUX_PCM0,
655 S900_MUX_PWM5 };
656 /* mfp2_23 */
657 static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
658 static unsigned int uart2_rtsb_mfp_funcs[] = { S900_MUX_UART2,
659 S900_MUX_UART0 };
660 /* mfp2_22 */
661 static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
662 static unsigned int uart2_ctsb_mfp_funcs[] = { S900_MUX_UART2,
663 S900_MUX_UART0 };
664 /* mfp2_21 */
665 static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
666 static unsigned int uart3_rtsb_mfp_funcs[] = { S900_MUX_UART3,
667 S900_MUX_UART5 };
668 /* mfp2_20 */
669 static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
670 static unsigned int uart3_ctsb_mfp_funcs[] = { S900_MUX_UART3,
671 S900_MUX_UART5 };
672 /* mfp2_19_17 */
673 static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
674 static unsigned int sd0_d0_mfp_funcs[] = { S900_MUX_SD0,
675 S900_MUX_ERAM,
676 S900_MUX_RESERVED,
677 S900_MUX_JTAG,
678 S900_MUX_UART2,
679 S900_MUX_UART5,
680 S900_MUX_GPU };
681 /* mfp2_16_14 */
682 static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
683 static unsigned int sd0_d1_mfp_funcs[] = { S900_MUX_SD0,
684 S900_MUX_ERAM,
685 S900_MUX_GPU,
686 S900_MUX_RESERVED,
687 S900_MUX_UART2,
688 S900_MUX_UART5 };
689 /* mfp_13_11 */
690 static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,
691 SD0_D3 };
692 static unsigned int sd0_d2_d3_mfp_funcs[] = { S900_MUX_SD0,
693 S900_MUX_ERAM,
694 S900_MUX_RESERVED,
695 S900_MUX_JTAG,
696 S900_MUX_UART2,
697 S900_MUX_UART1,
698 S900_MUX_GPU };
699 /* mfp2_10_9 */
700 static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,
701 SD1_D2, SD1_D3 };
702 static unsigned int sd1_d0_d3_mfp_funcs[] = { S900_MUX_SD1,
703 S900_MUX_ERAM };
704 /* mfp2_8_7 */
705 static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
706 static unsigned int sd0_cmd_mfp_funcs[] = { S900_MUX_SD0,
707 S900_MUX_ERAM,
708 S900_MUX_GPU,
709 S900_MUX_JTAG };
710 /* mfp2_6_5 */
711 static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
712 static unsigned int sd0_clk_mfp_funcs[] = { S900_MUX_SD0,
713 S900_MUX_ERAM,
714 S900_MUX_JTAG,
715 S900_MUX_GPU };
716 /* mfp2_4_3 */
717 static unsigned int sd1_cmd_clk_mfp_pads[] = { SD1_CMD, SD1_CLK };
718 static unsigned int sd1_cmd_clk_mfp_funcs[] = { S900_MUX_SD1,
719 S900_MUX_ERAM };
720 /* mfp2_2_0 */
721 static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
722 static unsigned int uart0_rx_mfp_funcs[] = { S900_MUX_UART0,
723 S900_MUX_UART2,
724 S900_MUX_SPI1,
725 S900_MUX_I2C5,
726 S900_MUX_PCM1,
727 S900_MUX_I2S1 };
728 /* mfp3_27 */
729 static unsigned int nand0_d0_ceb3_mfp_pads[] = { NAND0_D0, NAND0_D1,
730 NAND0_D2, NAND0_D3,
731 NAND0_D4, NAND0_D5,
732 NAND0_D6, NAND0_D7,
733 NAND0_DQSN, NAND0_CEB3 };
734 static unsigned int nand0_d0_ceb3_mfp_funcs[] = { S900_MUX_NAND0,
735 S900_MUX_SD2 };
736 /* mfp3_21_19 */
737 static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
738 static unsigned int uart0_tx_mfp_funcs[] = { S900_MUX_UART0,
739 S900_MUX_UART2,
740 S900_MUX_SPI1,
741 S900_MUX_I2C5,
742 S900_MUX_SPDIF,
743 S900_MUX_PCM1,
744 S900_MUX_I2S1 };
745 /* mfp3_18_16 */
746 static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, I2C0_SDATA };
747 static unsigned int i2c0_mfp_funcs[] = { S900_MUX_I2C0,
748 S900_MUX_UART2,
749 S900_MUX_I2C1,
750 S900_MUX_UART1,
751 S900_MUX_SPI1 };
752 /* mfp3_15 */
753 static unsigned int csi0_cn_cp_mfp_pads[] = { CSI0_CN, CSI0_CP };
754 static unsigned int csi0_cn_cp_mfp_funcs[] = { S900_MUX_SENS0,
755 S900_MUX_SENS0 };
756 /* mfp3_14 */
757 static unsigned int csi0_dn0_dp3_mfp_pads[] = { CSI0_DN0, CSI0_DP0,
758 CSI0_DN1, CSI0_DP1,
759 CSI0_CN, CSI0_CP,
760 CSI0_DP2, CSI0_DN2,
761 CSI0_DN3, CSI0_DP3 };
762 static unsigned int csi0_dn0_dp3_mfp_funcs[] = { S900_MUX_MIPI_CSI0,
763 S900_MUX_SENS0 };
764 /* mfp3_13 */
765 static unsigned int csi1_dn0_cp_mfp_pads[] = { CSI1_DN0, CSI1_DP0,
766 CSI1_DN1, CSI1_DP1,
767 CSI1_CN, CSI1_CP };
768 static unsigned int csi1_dn0_cp_mfp_funcs[] = { S900_MUX_MIPI_CSI1,
769 S900_MUX_SENS0 };
770 /* mfp3_12_dsi */
771 static unsigned int dsi_dp3_dn1_mfp_pads[] = { DSI_DP3, DSI_DN2,
772 DSI_DP1, DSI_DN1 };
773 static unsigned int dsi_dp3_dn1_mfp_funcs[] = { S900_MUX_MIPI_DSI,
774 S900_MUX_UART2 };
775 static unsigned int dsi_cp_dn0_mfp_pads[] = { DSI_CP, DSI_CN,
776 DSI_DP0, DSI_DN0 };
777 static unsigned int dsi_cp_dn0_mfp_funcs[] = { S900_MUX_MIPI_DSI,
778 S900_MUX_PCM1 };
779 static unsigned int dsi_dp2_dn2_mfp_pads[] = { DSI_DP2, DSI_DN2 };
780 static unsigned int dsi_dp2_dn2_mfp_funcs[] = { S900_MUX_MIPI_DSI,
781 S900_MUX_UART4 };
782 /* mfp3_11 */
783 static unsigned int nand1_d0_ceb1_mfp_pads[] = { NAND1_D0, NAND1_D1,
784 NAND1_D2, NAND1_D3,
785 NAND1_D4, NAND1_D5,
786 NAND1_D6, NAND1_D7,
787 NAND1_DQSN, NAND1_CEB1 };
788 static unsigned int nand1_d0_ceb1_mfp_funcs[] = { S900_MUX_NAND1,
789 S900_MUX_SD3 };
790 /* mfp3_10 */
791 static unsigned int nand1_ceb3_mfp_pads[] = { NAND1_CEB3 };
792 static unsigned int nand1_ceb3_mfp_funcs[] = { S900_MUX_NAND1,
793 S900_MUX_PWM0 };
794 static unsigned int nand1_ceb0_mfp_pads[] = { NAND1_CEB0 };
795 static unsigned int nand1_ceb0_mfp_funcs[] = { S900_MUX_NAND1,
796 S900_MUX_PWM1 };
797 /* mfp3_9 */
798 static unsigned int csi1_dn0_dp0_mfp_pads[] = { CSI1_DN0, CSI1_DP0 };
799 static unsigned int csi1_dn0_dp0_mfp_funcs[] = { S900_MUX_SENS0,
800 S900_MUX_SENS0 };
801 /* mfp3_8 */
802 static unsigned int uart4_rx_tx_mfp_pads[] = { UART4_RX, UART4_TX };
803 static unsigned int uart4_rx_tx_mfp_funcs[] = { S900_MUX_UART4,
804 S900_MUX_I2C4 };
805 /* PADDRV group data */
806 /* drv0 */
807 static unsigned int sgpio3_drv_pads[] = { SGPIO3 };
808 static unsigned int sgpio2_drv_pads[] = { SGPIO2 };
809 static unsigned int sgpio1_drv_pads[] = { SGPIO1 };
810 static unsigned int sgpio0_drv_pads[] = { SGPIO0 };
811 static unsigned int rmii_tx_d0_d1_drv_pads[] = { ETH_TXD0, ETH_TXD1 };
812 static unsigned int rmii_txen_rxer_drv_pads[] = { ETH_TXEN, ETH_RXER };
813 static unsigned int rmii_crs_dv_drv_pads[] = { ETH_CRS_DV };
814 static unsigned int rmii_rx_d1_d0_drv_pads[] = { ETH_RXD1, ETH_RXD0 };
815 static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
816 static unsigned int rmii_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };
817 static unsigned int sirq_0_1_drv_pads[] = { SIRQ0, SIRQ1 };
818 static unsigned int sirq2_drv_pads[] = { SIRQ2 };
819 static unsigned int i2s_d0_d1_drv_pads[] = { I2S_D0, I2S_D1 };
820 static unsigned int i2s_lr_m_clk0_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
821 static unsigned int i2s_blk1_mclk1_drv_pads[] = { I2S_BCLK0, I2S_BCLK1,
822 I2S_LRCLK1, I2S_MCLK1 };
823 static unsigned int pcm1_in_out_drv_pads[] = { PCM1_IN, PCM1_CLK,
824 PCM1_SYNC, PCM1_OUT };
825 /* drv1 */
826 static unsigned int lvds_oap_oan_drv_pads[] = { LVDS_OAP, LVDS_OAN };
827 static unsigned int lvds_oep_odn_drv_pads[] = { LVDS_OEP, LVDS_OEN,
828 LVDS_ODP, LVDS_ODN };
829 static unsigned int lvds_ocp_obn_drv_pads[] = { LVDS_OCP, LVDS_OCN,
830 LVDS_OBP, LVDS_OBN };
831 static unsigned int lvds_e_drv_pads[] = { LVDS_EEP, LVDS_EEN,
832 LVDS_EDP, LVDS_EDN,
833 LVDS_ECP, LVDS_ECN,
834 LVDS_EBP, LVDS_EBN };
835 static unsigned int sd0_d3_d0_drv_pads[] = { SD0_D3, SD0_D2,
836 SD0_D1, SD0_D0 };
837 static unsigned int sd1_d3_d0_drv_pads[] = { SD1_D3, SD1_D2,
838 SD1_D1, SD1_D0 };
839 static unsigned int sd0_sd1_cmd_clk_drv_pads[] = { SD0_CLK, SD0_CMD,
840 SD1_CLK, SD1_CMD };
841 static unsigned int spi0_sclk_mosi_drv_pads[] = { SPI0_SCLK, SPI0_MOSI };
842 static unsigned int spi0_ss_miso_drv_pads[] = { SPI0_SS, SPI0_MISO };
843 static unsigned int uart0_rx_tx_drv_pads[] = { UART0_RX, UART0_TX };
844 static unsigned int uart4_rx_tx_drv_pads[] = { UART4_RX, UART4_TX };
845 static unsigned int uart2_drv_pads[] = { UART2_RX, UART2_TX,
846 UART2_RTSB, UART2_CTSB };
847 static unsigned int uart3_drv_pads[] = { UART3_RX, UART3_TX,
848 UART3_RTSB, UART3_CTSB };
849 /* drv2 */
850 static unsigned int i2c0_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };
851 static unsigned int i2c1_drv_pads[] = { I2C1_SCLK, I2C1_SDATA };
852 static unsigned int i2c2_drv_pads[] = { I2C2_SCLK, I2C2_SDATA };
853 static unsigned int sensor0_drv_pads[] = { SENSOR0_PCLK,
854 SENSOR0_CKOUT };
855 /* SR group data */
856 /* sr0 */
857 static unsigned int sgpio3_sr_pads[] = { SGPIO3 };
858 static unsigned int sgpio2_sr_pads[] = { SGPIO2 };
859 static unsigned int sgpio1_sr_pads[] = { SGPIO1 };
860 static unsigned int sgpio0_sr_pads[] = { SGPIO0 };
861 static unsigned int rmii_tx_d0_d1_sr_pads[] = { ETH_TXD0, ETH_TXD1 };
862 static unsigned int rmii_txen_rxer_sr_pads[] = { ETH_TXEN, ETH_RXER };
863 static unsigned int rmii_crs_dv_sr_pads[] = { ETH_CRS_DV };
864 static unsigned int rmii_rx_d1_d0_sr_pads[] = { ETH_RXD1, ETH_RXD0 };
865 static unsigned int rmii_ref_clk_sr_pads[] = { ETH_REF_CLK };
866 static unsigned int rmii_mdc_mdio_sr_pads[] = { ETH_MDC, ETH_MDIO };
867 static unsigned int sirq_0_1_sr_pads[] = { SIRQ0, SIRQ1 };
868 static unsigned int sirq2_sr_pads[] = { SIRQ2 };
869 static unsigned int i2s_do_d1_sr_pads[] = { I2S_D0, I2S_D1 };
870 static unsigned int i2s_lr_m_clk0_sr_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
871 static unsigned int i2s_bclk0_mclk1_sr_pads[] = { I2S_BCLK0, I2S_BCLK1,
872 I2S_LRCLK1, I2S_MCLK1 };
873 static unsigned int pcm1_in_out_sr_pads[] = { PCM1_IN, PCM1_CLK,
874 PCM1_SYNC, PCM1_OUT };
875 /* sr1 */
876 static unsigned int sd1_d3_d0_sr_pads[] = { SD1_D3, SD1_D2,
877 SD1_D1, SD1_D0 };
878 static unsigned int sd0_sd1_clk_cmd_sr_pads[] = { SD0_CLK, SD0_CMD,
879 SD1_CLK, SD1_CMD };
880 static unsigned int spi0_sclk_mosi_sr_pads[] = { SPI0_SCLK, SPI0_MOSI };
881 static unsigned int spi0_ss_miso_sr_pads[] = { SPI0_SS, SPI0_MISO };
882 static unsigned int uart0_rx_tx_sr_pads[] = { UART0_RX, UART0_TX };
883 static unsigned int uart4_rx_tx_sr_pads[] = { UART4_RX, UART4_TX };
884 static unsigned int uart2_sr_pads[] = { UART2_RX, UART2_TX,
885 UART2_RTSB, UART2_CTSB };
886 static unsigned int uart3_sr_pads[] = { UART3_RX, UART3_TX,
887 UART3_RTSB, UART3_CTSB };
888 /* sr2 */
889 static unsigned int i2c0_sr_pads[] = { I2C0_SCLK, I2C0_SDATA };
890 static unsigned int i2c1_sr_pads[] = { I2C1_SCLK, I2C1_SDATA };
891 static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
892 static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
893 SENSOR0_CKOUT };
894
895 #define MUX_PG(group_name, reg, shift, width) \
896 { \
897 .name = #group_name, \
898 .pads = group_name##_pads, \
899 .npads = ARRAY_SIZE(group_name##_pads), \
900 .funcs = group_name##_funcs, \
901 .nfuncs = ARRAY_SIZE(group_name##_funcs), \
902 .mfpctl_reg = MFCTL##reg, \
903 .mfpctl_shift = shift, \
904 .mfpctl_width = width, \
905 .drv_reg = -1, \
906 .drv_shift = -1, \
907 .drv_width = -1, \
908 .sr_reg = -1, \
909 .sr_shift = -1, \
910 .sr_width = -1, \
911 }
912
913 #define DRV_PG(group_name, reg, shift, width) \
914 { \
915 .name = #group_name, \
916 .pads = group_name##_pads, \
917 .npads = ARRAY_SIZE(group_name##_pads), \
918 .mfpctl_reg = -1, \
919 .mfpctl_shift = -1, \
920 .mfpctl_width = -1, \
921 .drv_reg = PAD_DRV##reg, \
922 .drv_shift = shift, \
923 .drv_width = width, \
924 .sr_reg = -1, \
925 .sr_shift = -1, \
926 .sr_width = -1, \
927 }
928
929 #define SR_PG(group_name, reg, shift, width) \
930 { \
931 .name = #group_name, \
932 .pads = group_name##_pads, \
933 .npads = ARRAY_SIZE(group_name##_pads), \
934 .mfpctl_reg = -1, \
935 .mfpctl_shift = -1, \
936 .mfpctl_width = -1, \
937 .drv_reg = -1, \
938 .drv_shift = -1, \
939 .drv_width = -1, \
940 .sr_reg = PAD_SR##reg, \
941 .sr_shift = shift, \
942 .sr_width = width, \
943 }
944
945 /* Pinctrl groups */
946 static const struct owl_pingroup s900_groups[] = {
947 MUX_PG(lvds_oxx_uart4_mfp, 0, 22, 1),
948 MUX_PG(rmii_mdc_mfp, 0, 20, 2),
949 MUX_PG(rmii_mdio_mfp, 0, 20, 2),
950 MUX_PG(sirq0_mfp, 0, 19, 1),
951 MUX_PG(sirq1_mfp, 0, 19, 1),
952 MUX_PG(rmii_txd0_mfp, 0, 16, 3),
953 MUX_PG(rmii_txd1_mfp, 0, 16, 3),
954 MUX_PG(rmii_txen_mfp, 0, 13, 3),
955 MUX_PG(rmii_rxer_mfp, 0, 13, 3),
956 MUX_PG(rmii_crs_dv_mfp, 0, 11, 2),
957 MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
958 MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
959 MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
960 MUX_PG(i2s_d0_mfp, 0, 5, 1),
961 MUX_PG(i2s_d1_mfp, 0, 5, 1),
962 MUX_PG(i2s_lr_m_clk0_mfp, 0, 3, 2),
963 MUX_PG(i2s_bclk0_mfp, 0, 2, 1),
964 MUX_PG(i2s_bclk1_mclk1_mfp, 0, 2, 1),
965 MUX_PG(pcm1_in_out_mfp, 0, 0, 2),
966 MUX_PG(pcm1_clk_mfp, 0, 0, 2),
967 MUX_PG(pcm1_sync_mfp, 0, 0, 2),
968 MUX_PG(eram_a5_mfp, 1, 29, 3),
969 MUX_PG(eram_a6_mfp, 1, 29, 3),
970 MUX_PG(eram_a7_mfp, 1, 29, 3),
971 MUX_PG(eram_a8_mfp, 1, 26, 3),
972 MUX_PG(eram_a9_mfp, 1, 26, 3),
973 MUX_PG(eram_a10_mfp, 1, 26, 3),
974 MUX_PG(eram_a11_mfp, 1, 23, 3),
975 MUX_PG(lvds_oep_odn_mfp, 1, 22, 1),
976 MUX_PG(lvds_ocp_obn_mfp, 1, 22, 1),
977 MUX_PG(lvds_oap_oan_mfp, 1, 22, 1),
978 MUX_PG(lvds_e_mfp, 1, 21, 1),
979 MUX_PG(spi0_sclk_mosi_mfp, 1, 4, 2),
980 MUX_PG(spi0_ss_mfp, 1, 1, 3),
981 MUX_PG(spi0_miso_mfp, 1, 1, 3),
982 MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
983 MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
984 MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
985 MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
986 MUX_PG(sd0_d0_mfp, 2, 17, 3),
987 MUX_PG(sd0_d1_mfp, 2, 14, 3),
988 MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
989 MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
990 MUX_PG(sd0_cmd_mfp, 2, 7, 2),
991 MUX_PG(sd0_clk_mfp, 2, 5, 2),
992 MUX_PG(sd1_cmd_clk_mfp, 2, 3, 2),
993 MUX_PG(uart0_rx_mfp, 2, 0, 3),
994 MUX_PG(nand0_d0_ceb3_mfp, 3, 27, 1),
995 MUX_PG(uart0_tx_mfp, 3, 19, 3),
996 MUX_PG(i2c0_mfp, 3, 16, 3),
997 MUX_PG(csi0_cn_cp_mfp, 3, 15, 1),
998 MUX_PG(csi0_dn0_dp3_mfp, 3, 14, 1),
999 MUX_PG(csi1_dn0_cp_mfp, 3, 13, 1),
1000 MUX_PG(dsi_dp3_dn1_mfp, 3, 12, 1),
1001 MUX_PG(dsi_cp_dn0_mfp, 3, 12, 1),
1002 MUX_PG(dsi_dp2_dn2_mfp, 3, 12, 1),
1003 MUX_PG(nand1_d0_ceb1_mfp, 3, 11, 1),
1004 MUX_PG(nand1_ceb3_mfp, 3, 10, 1),
1005 MUX_PG(nand1_ceb0_mfp, 3, 10, 1),
1006 MUX_PG(csi1_dn0_dp0_mfp, 3, 9, 1),
1007 MUX_PG(uart4_rx_tx_mfp, 3, 8, 1),
1008
1009 DRV_PG(sgpio3_drv, 0, 30, 2),
1010 DRV_PG(sgpio2_drv, 0, 28, 2),
1011 DRV_PG(sgpio1_drv, 0, 26, 2),
1012 DRV_PG(sgpio0_drv, 0, 24, 2),
1013 DRV_PG(rmii_tx_d0_d1_drv, 0, 22, 2),
1014 DRV_PG(rmii_txen_rxer_drv, 0, 20, 2),
1015 DRV_PG(rmii_crs_dv_drv, 0, 18, 2),
1016 DRV_PG(rmii_rx_d1_d0_drv, 0, 16, 2),
1017 DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
1018 DRV_PG(rmii_mdc_mdio_drv, 0, 12, 2),
1019 DRV_PG(sirq_0_1_drv, 0, 10, 2),
1020 DRV_PG(sirq2_drv, 0, 8, 2),
1021 DRV_PG(i2s_d0_d1_drv, 0, 6, 2),
1022 DRV_PG(i2s_lr_m_clk0_drv, 0, 4, 2),
1023 DRV_PG(i2s_blk1_mclk1_drv, 0, 2, 2),
1024 DRV_PG(pcm1_in_out_drv, 0, 0, 2),
1025 DRV_PG(lvds_oap_oan_drv, 1, 28, 2),
1026 DRV_PG(lvds_oep_odn_drv, 1, 26, 2),
1027 DRV_PG(lvds_ocp_obn_drv, 1, 24, 2),
1028 DRV_PG(lvds_e_drv, 1, 22, 2),
1029 DRV_PG(sd0_d3_d0_drv, 1, 20, 2),
1030 DRV_PG(sd1_d3_d0_drv, 1, 18, 2),
1031 DRV_PG(sd0_sd1_cmd_clk_drv, 1, 16, 2),
1032 DRV_PG(spi0_sclk_mosi_drv, 1, 14, 2),
1033 DRV_PG(spi0_ss_miso_drv, 1, 12, 2),
1034 DRV_PG(uart0_rx_tx_drv, 1, 10, 2),
1035 DRV_PG(uart4_rx_tx_drv, 1, 8, 2),
1036 DRV_PG(uart2_drv, 1, 6, 2),
1037 DRV_PG(uart3_drv, 1, 4, 2),
1038 DRV_PG(i2c0_drv, 2, 30, 2),
1039 DRV_PG(i2c1_drv, 2, 28, 2),
1040 DRV_PG(i2c2_drv, 2, 26, 2),
1041 DRV_PG(sensor0_drv, 2, 20, 2),
1042
1043 SR_PG(sgpio3_sr, 0, 15, 1),
1044 SR_PG(sgpio2_sr, 0, 14, 1),
1045 SR_PG(sgpio1_sr, 0, 13, 1),
1046 SR_PG(sgpio0_sr, 0, 12, 1),
1047 SR_PG(rmii_tx_d0_d1_sr, 0, 11, 1),
1048 SR_PG(rmii_txen_rxer_sr, 0, 10, 1),
1049 SR_PG(rmii_crs_dv_sr, 0, 9, 1),
1050 SR_PG(rmii_rx_d1_d0_sr, 0, 8, 1),
1051 SR_PG(rmii_ref_clk_sr, 0, 7, 1),
1052 SR_PG(rmii_mdc_mdio_sr, 0, 6, 1),
1053 SR_PG(sirq_0_1_sr, 0, 5, 1),
1054 SR_PG(sirq2_sr, 0, 4, 1),
1055 SR_PG(i2s_do_d1_sr, 0, 3, 1),
1056 SR_PG(i2s_lr_m_clk0_sr, 0, 2, 1),
1057 SR_PG(i2s_bclk0_mclk1_sr, 0, 1, 1),
1058 SR_PG(pcm1_in_out_sr, 0, 0, 1),
1059 SR_PG(sd1_d3_d0_sr, 1, 25, 1),
1060 SR_PG(sd0_sd1_clk_cmd_sr, 1, 24, 1),
1061 SR_PG(spi0_sclk_mosi_sr, 1, 23, 1),
1062 SR_PG(spi0_ss_miso_sr, 1, 22, 1),
1063 SR_PG(uart0_rx_tx_sr, 1, 21, 1),
1064 SR_PG(uart4_rx_tx_sr, 1, 20, 1),
1065 SR_PG(uart2_sr, 1, 19, 1),
1066 SR_PG(uart3_sr, 1, 18, 1),
1067 SR_PG(i2c0_sr, 2, 31, 1),
1068 SR_PG(i2c1_sr, 2, 30, 1),
1069 SR_PG(i2c2_sr, 2, 29, 1),
1070 SR_PG(sensor0_sr, 2, 25, 1)
1071 };
1072
1073 static const char * const eram_groups[] = {
1074 "lvds_oxx_uart4_mfp",
1075 "eram_a5_mfp",
1076 "eram_a6_mfp",
1077 "eram_a7_mfp",
1078 "eram_a8_mfp",
1079 "eram_a9_mfp",
1080 "eram_a10_mfp",
1081 "eram_a11_mfp",
1082 "lvds_oap_oan_mfp",
1083 "lvds_e_mfp",
1084 "spi0_sclk_mosi_mfp",
1085 "spi0_ss_mfp",
1086 "spi0_miso_mfp",
1087 "sd0_d0_mfp",
1088 "sd0_d1_mfp",
1089 "sd0_d2_d3_mfp",
1090 "sd1_d0_d3_mfp",
1091 "sd0_cmd_mfp",
1092 "sd0_clk_mfp",
1093 "sd1_cmd_clk_mfp",
1094 };
1095
1096 static const char * const eth_rmii_groups[] = {
1097 "rmii_mdc_mfp",
1098 "rmii_mdio_mfp",
1099 "rmii_txd0_mfp",
1100 "rmii_txd1_mfp",
1101 "rmii_txen_mfp",
1102 "rmii_rxer_mfp",
1103 "rmii_crs_dv_mfp",
1104 "rmii_rxd1_mfp",
1105 "rmii_rxd0_mfp",
1106 "rmii_ref_clk_mfp",
1107 "eth_smi_dummy",
1108 };
1109
1110 static const char * const eth_smii_groups[] = {
1111 "rmii_txd0_mfp",
1112 "rmii_txd1_mfp",
1113 "rmii_crs_dv_mfp",
1114 "eth_smi_dummy",
1115 };
1116
1117 static const char * const spi0_groups[] = {
1118 "spi0_sclk_mosi_mfp",
1119 "spi0_ss_mfp",
1120 "spi0_miso_mfp",
1121 "spi0_sclk_mosi_mfp",
1122 "spi0_ss_mfp",
1123 "spi0_miso_mfp",
1124 };
1125
1126 static const char * const spi1_groups[] = {
1127 "pcm1_in_out_mfp",
1128 "pcm1_clk_mfp",
1129 "pcm1_sync_mfp",
1130 "uart0_rx_mfp",
1131 "uart0_tx_mfp",
1132 "i2c0_mfp",
1133 };
1134
1135 static const char * const spi2_groups[] = {
1136 "rmii_txd0_mfp",
1137 "rmii_txd1_mfp",
1138 "rmii_crs_dv_mfp",
1139 "rmii_ref_clk_mfp",
1140 };
1141
1142 static const char * const spi3_groups[] = {
1143 "rmii_txen_mfp",
1144 "rmii_rxer_mfp",
1145 };
1146
1147 static const char * const sens0_groups[] = {
1148 "rmii_txd0_mfp",
1149 "rmii_txd1_mfp",
1150 "rmii_txen_mfp",
1151 "rmii_rxer_mfp",
1152 "rmii_rxd1_mfp",
1153 "rmii_rxd0_mfp",
1154 "eram_a5_mfp",
1155 "eram_a6_mfp",
1156 "eram_a7_mfp",
1157 "eram_a8_mfp",
1158 "eram_a9_mfp",
1159 "csi0_cn_cp_mfp",
1160 "csi0_dn0_dp3_mfp",
1161 "csi1_dn0_cp_mfp",
1162 "csi1_dn0_dp0_mfp",
1163 };
1164
1165 static const char * const uart0_groups[] = {
1166 "uart2_rtsb_mfp",
1167 "uart2_ctsb_mfp",
1168 "uart0_rx_mfp",
1169 "uart0_tx_mfp",
1170 };
1171
1172 static const char * const uart1_groups[] = {
1173 "sd0_d2_d3_mfp",
1174 "i2c0_mfp",
1175 };
1176
1177 static const char * const uart2_groups[] = {
1178 "rmii_mdc_mfp",
1179 "rmii_mdio_mfp",
1180 "rmii_txen_mfp",
1181 "rmii_rxer_mfp",
1182 "rmii_rxd1_mfp",
1183 "rmii_rxd0_mfp",
1184 "lvds_oep_odn_mfp",
1185 "uart2_rtsb_mfp",
1186 "uart2_ctsb_mfp",
1187 "sd0_d0_mfp",
1188 "sd0_d1_mfp",
1189 "sd0_d2_d3_mfp",
1190 "uart0_rx_mfp",
1191 "uart0_tx_mfp_pads",
1192 "i2c0_mfp_pads",
1193 "dsi_dp3_dn1_mfp",
1194 "uart2_dummy"
1195 };
1196
1197 static const char * const uart3_groups[] = {
1198 "uart3_rtsb_mfp",
1199 "uart3_ctsb_mfp",
1200 "uart3_dummy"
1201 };
1202
1203 static const char * const uart4_groups[] = {
1204 "lvds_oxx_uart4_mfp",
1205 "rmii_crs_dv_mfp",
1206 "rmii_ref_clk_mfp",
1207 "pcm1_in_out_mfp",
1208 "pcm1_clk_mfp",
1209 "pcm1_sync_mfp",
1210 "eram_a5_mfp",
1211 "eram_a6_mfp",
1212 "dsi_dp2_dn2_mfp",
1213 "uart4_rx_tx_mfp_pads",
1214 "uart4_dummy"
1215 };
1216
1217 static const char * const uart5_groups[] = {
1218 "rmii_rxd1_mfp",
1219 "rmii_rxd0_mfp",
1220 "eram_a9_mfp",
1221 "eram_a11_mfp",
1222 "uart3_rtsb_mfp",
1223 "uart3_ctsb_mfp",
1224 "sd0_d0_mfp",
1225 "sd0_d1_mfp",
1226 };
1227
1228 static const char * const uart6_groups[] = {
1229 "rmii_txd0_mfp",
1230 "rmii_txd1_mfp",
1231 };
1232
1233 static const char * const i2s0_groups[] = {
1234 "i2s_d0_mfp",
1235 "i2s_lr_m_clk0_mfp",
1236 "i2s_bclk0_mfp",
1237 "i2s0_dummy",
1238 };
1239
1240 static const char * const i2s1_groups[] = {
1241 "i2s_d1_mfp",
1242 "i2s_bclk1_mclk1_mfp",
1243 "spi0_ss_mfp",
1244 "spi0_miso_mfp",
1245 "uart0_rx_mfp",
1246 "uart0_tx_mfp",
1247 "i2s1_dummy",
1248 };
1249
1250 static const char * const pcm0_groups[] = {
1251 "i2s_d0_mfp",
1252 "i2s_d1_mfp",
1253 "i2s_lr_m_clk0_mfp",
1254 "i2s_bclk0_mfp",
1255 "i2s_bclk1_mclk1_mfp",
1256 "spi0_sclk_mosi_mfp",
1257 "spi0_ss_mfp",
1258 "spi0_miso_mfp",
1259 };
1260
1261 static const char * const pcm1_groups[] = {
1262 "i2s_lr_m_clk0_mfp",
1263 "pcm1_in_out_mfp",
1264 "pcm1_clk_mfp",
1265 "pcm1_sync_mfp",
1266 "lvds_oep_odn_mfp",
1267 "spi0_ss_mfp",
1268 "spi0_miso_mfp",
1269 "uart0_rx_mfp",
1270 "uart0_tx_mfp",
1271 "dsi_cp_dn0_mfp",
1272 "pcm1_dummy",
1273 };
1274
1275 static const char * const jtag_groups[] = {
1276 "eram_a5_mfp",
1277 "eram_a6_mfp",
1278 "eram_a7_mfp",
1279 "eram_a8_mfp",
1280 "eram_a10_mfp",
1281 "eram_a10_mfp",
1282 "sd0_d2_d3_mfp",
1283 "sd0_cmd_mfp",
1284 "sd0_clk_mfp",
1285 };
1286
1287 static const char * const pwm0_groups[] = {
1288 "sirq0_mfp",
1289 "rmii_txd0_mfp",
1290 "rmii_rxd1_mfp",
1291 "eram_a5_mfp",
1292 "nand1_ceb3_mfp",
1293 };
1294
1295 static const char * const pwm1_groups[] = {
1296 "sirq1_mfp",
1297 "rmii_txd1_mfp",
1298 "rmii_rxd0_mfp",
1299 "eram_a6_mfp",
1300 "eram_a8_mfp",
1301 "nand1_ceb0_mfp",
1302 };
1303
1304 static const char * const pwm2_groups[] = {
1305 "rmii_mdc_mfp",
1306 "rmii_txen_mfp",
1307 "eram_a9_mfp",
1308 "eram_a11_mfp",
1309 };
1310
1311 static const char * const pwm3_groups[] = {
1312 "rmii_mdio_mfp",
1313 "rmii_rxer_mfp",
1314 "eram_a10_mfp",
1315 };
1316
1317 static const char * const pwm4_groups[] = {
1318 "pcm1_clk_mfp",
1319 "spi0_ss_mfp",
1320 };
1321
1322 static const char * const pwm5_groups[] = {
1323 "pcm1_sync_mfp",
1324 "spi0_miso_mfp",
1325 };
1326
1327 static const char * const sd0_groups[] = {
1328 "sd0_d0_mfp",
1329 "sd0_d1_mfp",
1330 "sd0_d2_d3_mfp",
1331 "sd0_cmd_mfp",
1332 "sd0_clk_mfp",
1333 };
1334
1335 static const char * const sd1_groups[] = {
1336 "sd1_d0_d3_mfp",
1337 "sd1_cmd_clk_mfp",
1338 "sd1_dummy",
1339 };
1340
1341 static const char * const sd2_groups[] = {
1342 "nand0_d0_ceb3_mfp",
1343 };
1344
1345 static const char * const sd3_groups[] = {
1346 "nand1_d0_ceb1_mfp",
1347 };
1348
1349 static const char * const i2c0_groups[] = {
1350 "i2c0_mfp",
1351 };
1352
1353 static const char * const i2c1_groups[] = {
1354 "i2c0_mfp",
1355 "i2c1_dummy"
1356 };
1357
1358 static const char * const i2c2_groups[] = {
1359 "i2c2_dummy"
1360 };
1361
1362 static const char * const i2c3_groups[] = {
1363 "pcm1_in_out_mfp",
1364 "spi0_sclk_mosi_mfp",
1365 };
1366
1367 static const char * const i2c4_groups[] = {
1368 "uart4_rx_tx_mfp",
1369 };
1370
1371 static const char * const i2c5_groups[] = {
1372 "uart0_rx_mfp",
1373 "uart0_tx_mfp",
1374 };
1375
1376
1377 static const char * const lvds_groups[] = {
1378 "lvds_oep_odn_mfp",
1379 "lvds_ocp_obn_mfp",
1380 "lvds_oap_oan_mfp",
1381 "lvds_e_mfp",
1382 };
1383
1384 static const char * const usb20_groups[] = {
1385 "eram_a9_mfp",
1386 };
1387
1388 static const char * const usb30_groups[] = {
1389 "eram_a10_mfp",
1390 };
1391
1392 static const char * const gpu_groups[] = {
1393 "sd0_d0_mfp",
1394 "sd0_d1_mfp",
1395 "sd0_d2_d3_mfp",
1396 "sd0_cmd_mfp",
1397 "sd0_clk_mfp",
1398 };
1399
1400 static const char * const mipi_csi0_groups[] = {
1401 "csi0_dn0_dp3_mfp",
1402 };
1403
1404 static const char * const mipi_csi1_groups[] = {
1405 "csi1_dn0_cp_mfp",
1406 };
1407
1408 static const char * const mipi_dsi_groups[] = {
1409 "dsi_dp3_dn1_mfp",
1410 "dsi_cp_dn0_mfp",
1411 "dsi_dp2_dn2_mfp",
1412 "mipi_dsi_dummy",
1413 };
1414
1415 static const char * const nand0_groups[] = {
1416 "nand0_d0_ceb3_mfp",
1417 "nand0_dummy",
1418 };
1419
1420 static const char * const nand1_groups[] = {
1421 "nand1_d0_ceb1_mfp",
1422 "nand1_ceb3_mfp",
1423 "nand1_ceb0_mfp",
1424 "nand1_dummy",
1425 };
1426
1427 static const char * const spdif_groups[] = {
1428 "uart0_tx_mfp",
1429 };
1430
1431 static const char * const sirq0_groups[] = {
1432 "sirq0_mfp",
1433 "sirq0_dummy",
1434 };
1435
1436 static const char * const sirq1_groups[] = {
1437 "sirq1_mfp",
1438 "sirq1_dummy",
1439 };
1440
1441 static const char * const sirq2_groups[] = {
1442 "sirq2_dummy",
1443 };
1444
1445 #define FUNCTION(fname) \
1446 { \
1447 .name = #fname, \
1448 .groups = fname##_groups, \
1449 .ngroups = ARRAY_SIZE(fname##_groups), \
1450 }
1451
1452 static const struct owl_pinmux_func s900_functions[] = {
1453 [S900_MUX_ERAM] = FUNCTION(eram),
1454 [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
1455 [S900_MUX_ETH_SMII] = FUNCTION(eth_smii),
1456 [S900_MUX_SPI0] = FUNCTION(spi0),
1457 [S900_MUX_SPI1] = FUNCTION(spi1),
1458 [S900_MUX_SPI2] = FUNCTION(spi2),
1459 [S900_MUX_SPI3] = FUNCTION(spi3),
1460 [S900_MUX_SENS0] = FUNCTION(sens0),
1461 [S900_MUX_UART0] = FUNCTION(uart0),
1462 [S900_MUX_UART1] = FUNCTION(uart1),
1463 [S900_MUX_UART2] = FUNCTION(uart2),
1464 [S900_MUX_UART3] = FUNCTION(uart3),
1465 [S900_MUX_UART4] = FUNCTION(uart4),
1466 [S900_MUX_UART5] = FUNCTION(uart5),
1467 [S900_MUX_UART6] = FUNCTION(uart6),
1468 [S900_MUX_I2S0] = FUNCTION(i2s0),
1469 [S900_MUX_I2S1] = FUNCTION(i2s1),
1470 [S900_MUX_PCM0] = FUNCTION(pcm0),
1471 [S900_MUX_PCM1] = FUNCTION(pcm1),
1472 [S900_MUX_JTAG] = FUNCTION(jtag),
1473 [S900_MUX_PWM0] = FUNCTION(pwm0),
1474 [S900_MUX_PWM1] = FUNCTION(pwm1),
1475 [S900_MUX_PWM2] = FUNCTION(pwm2),
1476 [S900_MUX_PWM3] = FUNCTION(pwm3),
1477 [S900_MUX_PWM4] = FUNCTION(pwm4),
1478 [S900_MUX_PWM5] = FUNCTION(pwm5),
1479 [S900_MUX_SD0] = FUNCTION(sd0),
1480 [S900_MUX_SD1] = FUNCTION(sd1),
1481 [S900_MUX_SD2] = FUNCTION(sd2),
1482 [S900_MUX_SD3] = FUNCTION(sd3),
1483 [S900_MUX_I2C0] = FUNCTION(i2c0),
1484 [S900_MUX_I2C1] = FUNCTION(i2c1),
1485 [S900_MUX_I2C2] = FUNCTION(i2c2),
1486 [S900_MUX_I2C3] = FUNCTION(i2c3),
1487 [S900_MUX_I2C4] = FUNCTION(i2c4),
1488 [S900_MUX_I2C5] = FUNCTION(i2c5),
1489 [S900_MUX_LVDS] = FUNCTION(lvds),
1490 [S900_MUX_USB30] = FUNCTION(usb30),
1491 [S900_MUX_USB20] = FUNCTION(usb20),
1492 [S900_MUX_GPU] = FUNCTION(gpu),
1493 [S900_MUX_MIPI_CSI0] = FUNCTION(mipi_csi0),
1494 [S900_MUX_MIPI_CSI1] = FUNCTION(mipi_csi1),
1495 [S900_MUX_MIPI_DSI] = FUNCTION(mipi_dsi),
1496 [S900_MUX_NAND0] = FUNCTION(nand0),
1497 [S900_MUX_NAND1] = FUNCTION(nand1),
1498 [S900_MUX_SPDIF] = FUNCTION(spdif),
1499 [S900_MUX_SIRQ0] = FUNCTION(sirq0),
1500 [S900_MUX_SIRQ1] = FUNCTION(sirq1),
1501 [S900_MUX_SIRQ2] = FUNCTION(sirq2)
1502 };
1503 /* PAD PULL UP/DOWN CONFIGURES */
1504 #define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
1505 { \
1506 .reg = PAD_PULLCTL##pull_reg, \
1507 .shift = pull_sft, \
1508 .width = pull_wdt, \
1509 }
1510
1511 #define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
1512 struct owl_pullctl pad_name##_pullctl_conf \
1513 = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
1514
1515 #define ST_CONF(st_reg, st_sft, st_wdt) \
1516 { \
1517 .reg = PAD_ST##st_reg, \
1518 .shift = st_sft, \
1519 .width = st_wdt, \
1520 }
1521
1522 #define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
1523 struct owl_st pad_name##_st_conf \
1524 = ST_CONF(st_reg, st_sft, st_wdt)
1525
1526 /* PAD_PULLCTL0 */
1527 static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
1528 static PAD_PULLCTL_CONF(SIRQ0, 0, 16, 2);
1529 static PAD_PULLCTL_CONF(SIRQ1, 0, 14, 2);
1530 static PAD_PULLCTL_CONF(SIRQ2, 0, 12, 2);
1531 static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 10, 2);
1532 static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 2);
1533 static PAD_PULLCTL_CONF(ERAM_A5, 0, 6, 2);
1534 static PAD_PULLCTL_CONF(ERAM_A6, 0, 4, 2);
1535 static PAD_PULLCTL_CONF(ERAM_A7, 0, 2, 2);
1536 static PAD_PULLCTL_CONF(ERAM_A10, 0, 0, 2);
1537
1538 /* PAD_PULLCTL1 */
1539 static PAD_PULLCTL_CONF(PCM1_IN, 1, 30, 2);
1540 static PAD_PULLCTL_CONF(PCM1_OUT, 1, 28, 2);
1541 static PAD_PULLCTL_CONF(SD0_D0, 1, 26, 2);
1542 static PAD_PULLCTL_CONF(SD0_D1, 1, 24, 2);
1543 static PAD_PULLCTL_CONF(SD0_D2, 1, 22, 2);
1544 static PAD_PULLCTL_CONF(SD0_D3, 1, 20, 2);
1545 static PAD_PULLCTL_CONF(SD0_CMD, 1, 18, 2);
1546 static PAD_PULLCTL_CONF(SD0_CLK, 1, 16, 2);
1547 static PAD_PULLCTL_CONF(SD1_CMD, 1, 14, 2);
1548 static PAD_PULLCTL_CONF(SD1_D0, 1, 12, 2);
1549 static PAD_PULLCTL_CONF(SD1_D1, 1, 10, 2);
1550 static PAD_PULLCTL_CONF(SD1_D2, 1, 8, 2);
1551 static PAD_PULLCTL_CONF(SD1_D3, 1, 6, 2);
1552 static PAD_PULLCTL_CONF(UART0_RX, 1, 4, 2);
1553 static PAD_PULLCTL_CONF(UART0_TX, 1, 2, 2);
1554
1555 /* PAD_PULLCTL2 */
1556 static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 26, 2);
1557 static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 24, 2);
1558 static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 22, 2);
1559 static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 20, 2);
1560 static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 18, 2);
1561 static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 16, 2);
1562 static PAD_PULLCTL_CONF(NAND0_D0, 2, 15, 1);
1563 static PAD_PULLCTL_CONF(NAND0_D1, 2, 15, 1);
1564 static PAD_PULLCTL_CONF(NAND0_D2, 2, 15, 1);
1565 static PAD_PULLCTL_CONF(NAND0_D3, 2, 15, 1);
1566 static PAD_PULLCTL_CONF(NAND0_D4, 2, 15, 1);
1567 static PAD_PULLCTL_CONF(NAND0_D5, 2, 15, 1);
1568 static PAD_PULLCTL_CONF(NAND0_D6, 2, 15, 1);
1569 static PAD_PULLCTL_CONF(NAND0_D7, 2, 15, 1);
1570 static PAD_PULLCTL_CONF(NAND0_DQSN, 2, 14, 1);
1571 static PAD_PULLCTL_CONF(NAND0_DQS, 2, 13, 1);
1572 static PAD_PULLCTL_CONF(NAND1_D0, 2, 12, 1);
1573 static PAD_PULLCTL_CONF(NAND1_D1, 2, 12, 1);
1574 static PAD_PULLCTL_CONF(NAND1_D2, 2, 12, 1);
1575 static PAD_PULLCTL_CONF(NAND1_D3, 2, 12, 1);
1576 static PAD_PULLCTL_CONF(NAND1_D4, 2, 12, 1);
1577 static PAD_PULLCTL_CONF(NAND1_D5, 2, 12, 1);
1578 static PAD_PULLCTL_CONF(NAND1_D6, 2, 12, 1);
1579 static PAD_PULLCTL_CONF(NAND1_D7, 2, 12, 1);
1580 static PAD_PULLCTL_CONF(NAND1_DQSN, 2, 11, 1);
1581 static PAD_PULLCTL_CONF(NAND1_DQS, 2, 10, 1);
1582 static PAD_PULLCTL_CONF(SGPIO2, 2, 8, 2);
1583 static PAD_PULLCTL_CONF(SGPIO3, 2, 6, 2);
1584 static PAD_PULLCTL_CONF(UART4_RX, 2, 4, 2);
1585 static PAD_PULLCTL_CONF(UART4_TX, 2, 2, 2);
1586
1587 /* PAD_ST0 */
1588 static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
1589 static PAD_ST_CONF(UART0_RX, 0, 29, 1);
1590 static PAD_ST_CONF(ETH_MDC, 0, 28, 1);
1591 static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
1592 static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
1593 static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
1594 static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
1595 static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
1596 static PAD_ST_CONF(SGPIO2, 0, 18, 1);
1597 static PAD_ST_CONF(SGPIO3, 0, 17, 1);
1598 static PAD_ST_CONF(UART4_TX, 0, 16, 1);
1599 static PAD_ST_CONF(I2S_D1, 0, 15, 1);
1600 static PAD_ST_CONF(UART0_TX, 0, 14, 1);
1601 static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
1602 static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
1603 static PAD_ST_CONF(ERAM_A5, 0, 11, 1);
1604 static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
1605 static PAD_ST_CONF(ERAM_A9, 0, 6, 1);
1606 static PAD_ST_CONF(LVDS_OEP, 0, 5, 1);
1607 static PAD_ST_CONF(LVDS_ODN, 0, 4, 1);
1608 static PAD_ST_CONF(LVDS_OAP, 0, 3, 1);
1609 static PAD_ST_CONF(I2S_BCLK1, 0, 2, 1);
1610
1611 /* PAD_ST1 */
1612 static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
1613 static PAD_ST_CONF(UART4_RX, 1, 28, 1);
1614 static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
1615 static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
1616 static PAD_ST_CONF(UART3_RX, 1, 25, 1);
1617 static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
1618 static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
1619 static PAD_ST_CONF(UART2_RX, 1, 22, 1);
1620 static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
1621 static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
1622 static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
1623 static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
1624 static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
1625 static PAD_ST_CONF(LVDS_OCP, 1, 16, 1);
1626 static PAD_ST_CONF(LVDS_OBP, 1, 15, 1);
1627 static PAD_ST_CONF(LVDS_OBN, 1, 14, 1);
1628 static PAD_ST_CONF(PCM1_OUT, 1, 12, 1);
1629 static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
1630 static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
1631 static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
1632 static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
1633 static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
1634 static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
1635 static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
1636 static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
1637 static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
1638 static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
1639 static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
1640 static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
1641
1642 #define PAD_INFO(name) \
1643 { \
1644 .pad = name, \
1645 .pullctl = NULL, \
1646 .st = NULL, \
1647 }
1648
1649 #define PAD_INFO_ST(name) \
1650 { \
1651 .pad = name, \
1652 .pullctl = NULL, \
1653 .st = &name##_st_conf, \
1654 }
1655
1656 #define PAD_INFO_PULLCTL(name) \
1657 { \
1658 .pad = name, \
1659 .pullctl = &name##_pullctl_conf, \
1660 .st = NULL, \
1661 }
1662
1663 #define PAD_INFO_PULLCTL_ST(name) \
1664 { \
1665 .pad = name, \
1666 .pullctl = &name##_pullctl_conf, \
1667 .st = &name##_st_conf, \
1668 }
1669
1670 /* Pad info table */
1671 static struct owl_padinfo s900_padinfo[NUM_PADS] = {
1672 [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
1673 [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
1674 [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
1675 [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
1676 [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
1677 [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
1678 [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
1679 [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
1680 [ETH_MDC] = PAD_INFO_ST(ETH_MDC),
1681 [ETH_MDIO] = PAD_INFO(ETH_MDIO),
1682 [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
1683 [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
1684 [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
1685 [I2S_D0] = PAD_INFO(I2S_D0),
1686 [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
1687 [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
1688 [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
1689 [I2S_D1] = PAD_INFO_ST(I2S_D1),
1690 [I2S_BCLK1] = PAD_INFO_ST(I2S_BCLK1),
1691 [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
1692 [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
1693 [PCM1_IN] = PAD_INFO_PULLCTL_ST(PCM1_IN),
1694 [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
1695 [PCM1_SYNC] = PAD_INFO_ST(PCM1_SYNC),
1696 [PCM1_OUT] = PAD_INFO_PULLCTL_ST(PCM1_OUT),
1697 [ERAM_A5] = PAD_INFO_PULLCTL_ST(ERAM_A5),
1698 [ERAM_A6] = PAD_INFO_PULLCTL(ERAM_A6),
1699 [ERAM_A7] = PAD_INFO_PULLCTL(ERAM_A7),
1700 [ERAM_A8] = PAD_INFO(ERAM_A8),
1701 [ERAM_A9] = PAD_INFO_ST(ERAM_A9),
1702 [ERAM_A10] = PAD_INFO_PULLCTL(ERAM_A10),
1703 [ERAM_A11] = PAD_INFO(ERAM_A11),
1704 [LVDS_OEP] = PAD_INFO_ST(LVDS_OEP),
1705 [LVDS_OEN] = PAD_INFO(LVDS_OEN),
1706 [LVDS_ODP] = PAD_INFO(LVDS_ODP),
1707 [LVDS_ODN] = PAD_INFO_ST(LVDS_ODN),
1708 [LVDS_OCP] = PAD_INFO_ST(LVDS_OCP),
1709 [LVDS_OCN] = PAD_INFO(LVDS_OCN),
1710 [LVDS_OBP] = PAD_INFO_ST(LVDS_OBP),
1711 [LVDS_OBN] = PAD_INFO_ST(LVDS_OBN),
1712 [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
1713 [LVDS_OAN] = PAD_INFO(LVDS_OAN),
1714 [LVDS_EEP] = PAD_INFO(LVDS_EEP),
1715 [LVDS_EEN] = PAD_INFO(LVDS_EEN),
1716 [LVDS_EDP] = PAD_INFO(LVDS_EDP),
1717 [LVDS_EDN] = PAD_INFO(LVDS_EDN),
1718 [LVDS_ECP] = PAD_INFO(LVDS_ECP),
1719 [LVDS_ECN] = PAD_INFO(LVDS_ECN),
1720 [LVDS_EBP] = PAD_INFO(LVDS_EBP),
1721 [LVDS_EBN] = PAD_INFO(LVDS_EBN),
1722 [LVDS_EAP] = PAD_INFO(LVDS_EAP),
1723 [LVDS_EAN] = PAD_INFO(LVDS_EAN),
1724 [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
1725 [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
1726 [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
1727 [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
1728 [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
1729 [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
1730 [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
1731 [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
1732 [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
1733 [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
1734 [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
1735 [SD1_CLK] = PAD_INFO(SD1_CLK),
1736 [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
1737 [SPI0_SS] = PAD_INFO_ST(SPI0_SS),
1738 [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
1739 [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
1740 [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
1741 [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
1742 [UART2_RX] = PAD_INFO_ST(UART2_RX),
1743 [UART2_TX] = PAD_INFO(UART2_TX),
1744 [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
1745 [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
1746 [UART3_RX] = PAD_INFO_ST(UART3_RX),
1747 [UART3_TX] = PAD_INFO(UART3_TX),
1748 [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
1749 [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
1750 [UART4_RX] = PAD_INFO_PULLCTL_ST(UART4_RX),
1751 [UART4_TX] = PAD_INFO_PULLCTL_ST(UART4_TX),
1752 [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
1753 [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
1754 [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
1755 [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
1756 [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
1757 [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
1758 [CSI0_DN0] = PAD_INFO(CSI0_DN0),
1759 [CSI0_DP0] = PAD_INFO(CSI0_DP0),
1760 [CSI0_DN1] = PAD_INFO(CSI0_DN1),
1761 [CSI0_DP1] = PAD_INFO(CSI0_DP1),
1762 [CSI0_CN] = PAD_INFO(CSI0_CN),
1763 [CSI0_CP] = PAD_INFO(CSI0_CP),
1764 [CSI0_DN2] = PAD_INFO(CSI0_DN2),
1765 [CSI0_DP2] = PAD_INFO(CSI0_DP2),
1766 [CSI0_DN3] = PAD_INFO(CSI0_DN3),
1767 [CSI0_DP3] = PAD_INFO(CSI0_DP3),
1768 [DSI_DP3] = PAD_INFO(DSI_DP3),
1769 [DSI_DN3] = PAD_INFO(DSI_DN3),
1770 [DSI_DP1] = PAD_INFO(DSI_DP1),
1771 [DSI_DN1] = PAD_INFO(DSI_DN1),
1772 [DSI_CP] = PAD_INFO(DSI_CP),
1773 [DSI_CN] = PAD_INFO(DSI_CN),
1774 [DSI_DP0] = PAD_INFO(DSI_DP0),
1775 [DSI_DN0] = PAD_INFO(DSI_DN0),
1776 [DSI_DP2] = PAD_INFO(DSI_DP2),
1777 [DSI_DN2] = PAD_INFO(DSI_DN2),
1778 [SENSOR0_PCLK] = PAD_INFO(SENSOR0_PCLK),
1779 [CSI1_DN0] = PAD_INFO(CSI1_DN0),
1780 [CSI1_DP0] = PAD_INFO(CSI1_DP0),
1781 [CSI1_DN1] = PAD_INFO(CSI1_DN1),
1782 [CSI1_DP1] = PAD_INFO(CSI1_DP1),
1783 [CSI1_CN] = PAD_INFO(CSI1_CN),
1784 [CSI1_CP] = PAD_INFO(CSI1_CP),
1785 [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
1786 [NAND0_D0] = PAD_INFO_PULLCTL(NAND0_D0),
1787 [NAND0_D1] = PAD_INFO_PULLCTL(NAND0_D1),
1788 [NAND0_D2] = PAD_INFO_PULLCTL(NAND0_D2),
1789 [NAND0_D3] = PAD_INFO_PULLCTL(NAND0_D3),
1790 [NAND0_D4] = PAD_INFO_PULLCTL(NAND0_D4),
1791 [NAND0_D5] = PAD_INFO_PULLCTL(NAND0_D5),
1792 [NAND0_D6] = PAD_INFO_PULLCTL(NAND0_D6),
1793 [NAND0_D7] = PAD_INFO_PULLCTL(NAND0_D7),
1794 [NAND0_DQS] = PAD_INFO_PULLCTL(NAND0_DQS),
1795 [NAND0_DQSN] = PAD_INFO_PULLCTL(NAND0_DQSN),
1796 [NAND0_ALE] = PAD_INFO(NAND0_ALE),
1797 [NAND0_CLE] = PAD_INFO(NAND0_CLE),
1798 [NAND0_CEB0] = PAD_INFO(NAND0_CEB0),
1799 [NAND0_CEB1] = PAD_INFO(NAND0_CEB1),
1800 [NAND0_CEB2] = PAD_INFO(NAND0_CEB2),
1801 [NAND0_CEB3] = PAD_INFO(NAND0_CEB3),
1802 [NAND1_D0] = PAD_INFO_PULLCTL(NAND1_D0),
1803 [NAND1_D1] = PAD_INFO_PULLCTL(NAND1_D1),
1804 [NAND1_D2] = PAD_INFO_PULLCTL(NAND1_D2),
1805 [NAND1_D3] = PAD_INFO_PULLCTL(NAND1_D3),
1806 [NAND1_D4] = PAD_INFO_PULLCTL(NAND1_D4),
1807 [NAND1_D5] = PAD_INFO_PULLCTL(NAND1_D5),
1808 [NAND1_D6] = PAD_INFO_PULLCTL(NAND1_D6),
1809 [NAND1_D7] = PAD_INFO_PULLCTL(NAND1_D7),
1810 [NAND1_DQS] = PAD_INFO_PULLCTL(NAND1_DQS),
1811 [NAND1_DQSN] = PAD_INFO_PULLCTL(NAND1_DQSN),
1812 [NAND1_ALE] = PAD_INFO(NAND1_ALE),
1813 [NAND1_CLE] = PAD_INFO(NAND1_CLE),
1814 [NAND1_CEB0] = PAD_INFO(NAND1_CEB0),
1815 [NAND1_CEB1] = PAD_INFO(NAND1_CEB1),
1816 [NAND1_CEB2] = PAD_INFO(NAND1_CEB2),
1817 [NAND1_CEB3] = PAD_INFO(NAND1_CEB3),
1818 [SGPIO0] = PAD_INFO(SGPIO0),
1819 [SGPIO1] = PAD_INFO(SGPIO1),
1820 [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),
1821 [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
1822 };
1823
1824 #define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
1825 _intc_ctl, _intc_pd, _intc_msk, _intc_type) \
1826 [OWL_GPIO_PORT_##port] = { \
1827 .offset = base, \
1828 .pins = count, \
1829 .outen = _outen, \
1830 .inen = _inen, \
1831 .dat = _dat, \
1832 .intc_ctl = _intc_ctl, \
1833 .intc_pd = _intc_pd, \
1834 .intc_msk = _intc_msk, \
1835 .intc_type = _intc_type, \
1836 }
1837
1838 static const struct owl_gpio_port s900_gpio_ports[] = {
1839 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
1840 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
1841 OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
1842 OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
1843 OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
1844 OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
1845 };
1846
1847 static struct owl_pinctrl_soc_data s900_pinctrl_data = {
1848 .padinfo = s900_padinfo,
1849 .pins = (const struct pinctrl_pin_desc *)s900_pads,
1850 .npins = ARRAY_SIZE(s900_pads),
1851 .functions = s900_functions,
1852 .nfunctions = ARRAY_SIZE(s900_functions),
1853 .groups = s900_groups,
1854 .ngroups = ARRAY_SIZE(s900_groups),
1855 .ngpios = NUM_GPIOS,
1856 .ports = s900_gpio_ports,
1857 .nports = ARRAY_SIZE(s900_gpio_ports)
1858 };
1859
s900_pinctrl_probe(struct platform_device * pdev)1860 static int s900_pinctrl_probe(struct platform_device *pdev)
1861 {
1862 return owl_pinctrl_probe(pdev, &s900_pinctrl_data);
1863 }
1864
1865 static const struct of_device_id s900_pinctrl_of_match[] = {
1866 { .compatible = "actions,s900-pinctrl", },
1867 { }
1868 };
1869
1870 static struct platform_driver s900_pinctrl_driver = {
1871 .driver = {
1872 .name = "pinctrl-s900",
1873 .of_match_table = of_match_ptr(s900_pinctrl_of_match),
1874 },
1875 .probe = s900_pinctrl_probe,
1876 };
1877
s900_pinctrl_init(void)1878 static int __init s900_pinctrl_init(void)
1879 {
1880 return platform_driver_register(&s900_pinctrl_driver);
1881 }
1882 arch_initcall(s900_pinctrl_init);
1883
s900_pinctrl_exit(void)1884 static void __exit s900_pinctrl_exit(void)
1885 {
1886 platform_driver_unregister(&s900_pinctrl_driver);
1887 }
1888 module_exit(s900_pinctrl_exit);
1889
1890 MODULE_AUTHOR("Actions Semi Inc.");
1891 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
1892 MODULE_DESCRIPTION("Actions Semi S900 SoC Pinctrl Driver");
1893 MODULE_LICENSE("GPL");
1894
