Searched refs:dpm_level_enable_mask (Results 1 – 14 of 14) sorted by relevance
2642 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3303 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3357 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()3821 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3824 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3831 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3834 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3841 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3844 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3941 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()[all …]
237 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member
2780 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3448 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3500 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()3968 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3971 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3978 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3981 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3989 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3992 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()4087 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()[all …]
239 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member
2603 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_highest()2605 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_dpm_highest()2616 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()2618 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()2630 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { in smu7_force_dpm_highest()2632 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; in smu7_force_dpm_highest()2655 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2658 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_upload_dpm_level_enable_mask()2662 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2665 data->dpm_level_enable_mask.mclk_dpm_enable_mask); in smu7_upload_dpm_level_enable_mask()[all …]
293 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; member
368 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; member
372 struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; member
594 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in vegam_populate_smc_link_level()908 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in vegam_populate_all_graphic_levels()913 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()924 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()925 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()929 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()930 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()935 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()1065 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in vegam_populate_all_memory_levels()1070 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_memory_levels()
861 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in fiji_populate_smc_link_level()1057 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()1069 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1070 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1074 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1075 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1080 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1271 data->dpm_level_enable_mask.mclk_dpm_enable_mask = in fiji_populate_all_memory_levels()
790 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in polaris10_populate_smc_link_level()1019 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()1032 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1033 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1037 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1038 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1043 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1162 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in polaris10_populate_all_memory_levels()
499 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()1014 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()1336 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in ci_populate_all_memory_levels()2872 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_update_uvd_smc_table()2876 data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_update_uvd_smc_table()2881 data->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_update_uvd_smc_table()2903 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_update_vce_smc_table()2907 data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_update_vce_smc_table()2912 data->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_update_vce_smc_table()
522 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in tonga_populate_smc_link_level()722 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()735 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()738 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()739 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()744 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()745 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()751 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()1120 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in tonga_populate_all_memory_levels()
789 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in iceland_populate_smc_link_level()1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()1005 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1016 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1382 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in iceland_populate_all_memory_levels()
