1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24 #include <linux/firmware.h>
25 #include "i915_drv.h"
26 #include "i915_reg.h"
27
28 /**
29 * DOC: csr support for dmc
30 *
31 * Display Context Save and Restore (CSR) firmware support added from gen9
32 * onwards to drive newly added DMC (Display microcontroller) in display
33 * engine to save and restore the state of display engine when it enter into
34 * low-power state and comes back to normal.
35 */
36
37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
38 MODULE_FIRMWARE(I915_CSR_GLK);
39 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
40
41 #define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
42 MODULE_FIRMWARE(I915_CSR_CNL);
43 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
44
45 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
46 MODULE_FIRMWARE(I915_CSR_KBL);
47 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
48
49 #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin"
50 MODULE_FIRMWARE(I915_CSR_SKL);
51 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
52
53 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
54 MODULE_FIRMWARE(I915_CSR_BXT);
55 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
56
57
58 #define CSR_MAX_FW_SIZE 0x2FFF
59 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
60
61 struct intel_css_header {
62 /* 0x09 for DMC */
63 uint32_t module_type;
64
65 /* Includes the DMC specific header in dwords */
66 uint32_t header_len;
67
68 /* always value would be 0x10000 */
69 uint32_t header_ver;
70
71 /* Not used */
72 uint32_t module_id;
73
74 /* Not used */
75 uint32_t module_vendor;
76
77 /* in YYYYMMDD format */
78 uint32_t date;
79
80 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
81 uint32_t size;
82
83 /* Not used */
84 uint32_t key_size;
85
86 /* Not used */
87 uint32_t modulus_size;
88
89 /* Not used */
90 uint32_t exponent_size;
91
92 /* Not used */
93 uint32_t reserved1[12];
94
95 /* Major Minor */
96 uint32_t version;
97
98 /* Not used */
99 uint32_t reserved2[8];
100
101 /* Not used */
102 uint32_t kernel_header_info;
103 } __packed;
104
105 struct intel_fw_info {
106 uint16_t reserved1;
107
108 /* Stepping (A, B, C, ..., *). * is a wildcard */
109 char stepping;
110
111 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
112 char substepping;
113
114 uint32_t offset;
115 uint32_t reserved2;
116 } __packed;
117
118 struct intel_package_header {
119 /* DMC container header length in dwords */
120 unsigned char header_len;
121
122 /* always value would be 0x01 */
123 unsigned char header_ver;
124
125 unsigned char reserved[10];
126
127 /* Number of valid entries in the FWInfo array below */
128 uint32_t num_entries;
129
130 struct intel_fw_info fw_info[20];
131 } __packed;
132
133 struct intel_dmc_header {
134 /* always value would be 0x40403E3E */
135 uint32_t signature;
136
137 /* DMC binary header length */
138 unsigned char header_len;
139
140 /* 0x01 */
141 unsigned char header_ver;
142
143 /* Reserved */
144 uint16_t dmcc_ver;
145
146 /* Major, Minor */
147 uint32_t project;
148
149 /* Firmware program size (excluding header) in dwords */
150 uint32_t fw_size;
151
152 /* Major Minor version */
153 uint32_t fw_version;
154
155 /* Number of valid MMIO cycles present. */
156 uint32_t mmio_count;
157
158 /* MMIO address */
159 uint32_t mmioaddr[8];
160
161 /* MMIO data */
162 uint32_t mmiodata[8];
163
164 /* FW filename */
165 unsigned char dfile[32];
166
167 uint32_t reserved1[2];
168 } __packed;
169
170 struct stepping_info {
171 char stepping;
172 char substepping;
173 };
174
175 static const struct stepping_info skl_stepping_info[] = {
176 {'A', '0'}, {'B', '0'}, {'C', '0'},
177 {'D', '0'}, {'E', '0'}, {'F', '0'},
178 {'G', '0'}, {'H', '0'}, {'I', '0'},
179 {'J', '0'}, {'K', '0'}
180 };
181
182 static const struct stepping_info bxt_stepping_info[] = {
183 {'A', '0'}, {'A', '1'}, {'A', '2'},
184 {'B', '0'}, {'B', '1'}, {'B', '2'}
185 };
186
187 static const struct stepping_info no_stepping_info = { '*', '*' };
188
189 static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private * dev_priv)190 intel_get_stepping_info(struct drm_i915_private *dev_priv)
191 {
192 const struct stepping_info *si;
193 unsigned int size;
194
195 if (IS_SKYLAKE(dev_priv)) {
196 size = ARRAY_SIZE(skl_stepping_info);
197 si = skl_stepping_info;
198 } else if (IS_BROXTON(dev_priv)) {
199 size = ARRAY_SIZE(bxt_stepping_info);
200 si = bxt_stepping_info;
201 } else {
202 size = 0;
203 si = NULL;
204 }
205
206 if (INTEL_REVID(dev_priv) < size)
207 return si + INTEL_REVID(dev_priv);
208
209 return &no_stepping_info;
210 }
211
gen9_set_dc_state_debugmask(struct drm_i915_private * dev_priv)212 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
213 {
214 uint32_t val, mask;
215
216 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
217
218 if (IS_GEN9_LP(dev_priv))
219 mask |= DC_STATE_DEBUG_MASK_CORES;
220
221 /* The below bit doesn't need to be cleared ever afterwards */
222 val = I915_READ(DC_STATE_DEBUG);
223 if ((val & mask) != mask) {
224 val |= mask;
225 I915_WRITE(DC_STATE_DEBUG, val);
226 POSTING_READ(DC_STATE_DEBUG);
227 }
228 }
229
230 /**
231 * intel_csr_load_program() - write the firmware from memory to register.
232 * @dev_priv: i915 drm device.
233 *
234 * CSR firmware is read from a .bin file and kept in internal memory one time.
235 * Everytime display comes back from low power state this function is called to
236 * copy the firmware from internal memory to registers.
237 */
intel_csr_load_program(struct drm_i915_private * dev_priv)238 void intel_csr_load_program(struct drm_i915_private *dev_priv)
239 {
240 u32 *payload = dev_priv->csr.dmc_payload;
241 uint32_t i, fw_size;
242
243 if (!HAS_CSR(dev_priv)) {
244 DRM_ERROR("No CSR support available for this platform\n");
245 return;
246 }
247
248 if (!dev_priv->csr.dmc_payload) {
249 DRM_ERROR("Tried to program CSR with empty payload\n");
250 return;
251 }
252
253 fw_size = dev_priv->csr.dmc_fw_size;
254 assert_rpm_wakelock_held(dev_priv);
255
256 preempt_disable();
257
258 for (i = 0; i < fw_size; i++)
259 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
260
261 preempt_enable();
262
263 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
264 I915_WRITE(dev_priv->csr.mmioaddr[i],
265 dev_priv->csr.mmiodata[i]);
266 }
267
268 dev_priv->csr.dc_state = 0;
269
270 gen9_set_dc_state_debugmask(dev_priv);
271 }
272
parse_csr_fw(struct drm_i915_private * dev_priv,const struct firmware * fw)273 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
274 const struct firmware *fw)
275 {
276 struct intel_css_header *css_header;
277 struct intel_package_header *package_header;
278 struct intel_dmc_header *dmc_header;
279 struct intel_csr *csr = &dev_priv->csr;
280 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
281 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
282 uint32_t i;
283 uint32_t *dmc_payload;
284 uint32_t required_version;
285
286 if (!fw)
287 return NULL;
288
289 /* Extract CSS Header information*/
290 css_header = (struct intel_css_header *)fw->data;
291 if (sizeof(struct intel_css_header) !=
292 (css_header->header_len * 4)) {
293 DRM_ERROR("DMC firmware has wrong CSS header length "
294 "(%u bytes)\n",
295 (css_header->header_len * 4));
296 return NULL;
297 }
298
299 csr->version = css_header->version;
300
301 if (csr->fw_path == i915_modparams.dmc_firmware_path) {
302 /* Bypass version check for firmware override. */
303 required_version = csr->version;
304 } else if (IS_CANNONLAKE(dev_priv)) {
305 required_version = CNL_CSR_VERSION_REQUIRED;
306 } else if (IS_GEMINILAKE(dev_priv)) {
307 required_version = GLK_CSR_VERSION_REQUIRED;
308 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
309 required_version = KBL_CSR_VERSION_REQUIRED;
310 } else if (IS_SKYLAKE(dev_priv)) {
311 required_version = SKL_CSR_VERSION_REQUIRED;
312 } else if (IS_BROXTON(dev_priv)) {
313 required_version = BXT_CSR_VERSION_REQUIRED;
314 } else {
315 MISSING_CASE(INTEL_REVID(dev_priv));
316 required_version = 0;
317 }
318
319 if (csr->version != required_version) {
320 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
321 " please use v%u.%u\n",
322 CSR_VERSION_MAJOR(csr->version),
323 CSR_VERSION_MINOR(csr->version),
324 CSR_VERSION_MAJOR(required_version),
325 CSR_VERSION_MINOR(required_version));
326 return NULL;
327 }
328
329 readcount += sizeof(struct intel_css_header);
330
331 /* Extract Package Header information*/
332 package_header = (struct intel_package_header *)
333 &fw->data[readcount];
334 if (sizeof(struct intel_package_header) !=
335 (package_header->header_len * 4)) {
336 DRM_ERROR("DMC firmware has wrong package header length "
337 "(%u bytes)\n",
338 (package_header->header_len * 4));
339 return NULL;
340 }
341 readcount += sizeof(struct intel_package_header);
342
343 /* Search for dmc_offset to find firware binary. */
344 for (i = 0; i < package_header->num_entries; i++) {
345 if (package_header->fw_info[i].substepping == '*' &&
346 si->stepping == package_header->fw_info[i].stepping) {
347 dmc_offset = package_header->fw_info[i].offset;
348 break;
349 } else if (si->stepping == package_header->fw_info[i].stepping &&
350 si->substepping == package_header->fw_info[i].substepping) {
351 dmc_offset = package_header->fw_info[i].offset;
352 break;
353 } else if (package_header->fw_info[i].stepping == '*' &&
354 package_header->fw_info[i].substepping == '*')
355 dmc_offset = package_header->fw_info[i].offset;
356 }
357 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
358 DRM_ERROR("DMC firmware not supported for %c stepping\n",
359 si->stepping);
360 return NULL;
361 }
362 readcount += dmc_offset;
363
364 /* Extract dmc_header information. */
365 dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
366 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
367 DRM_ERROR("DMC firmware has wrong dmc header length "
368 "(%u bytes)\n",
369 (dmc_header->header_len));
370 return NULL;
371 }
372 readcount += sizeof(struct intel_dmc_header);
373
374 /* Cache the dmc header info. */
375 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
376 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
377 dmc_header->mmio_count);
378 return NULL;
379 }
380 csr->mmio_count = dmc_header->mmio_count;
381 for (i = 0; i < dmc_header->mmio_count; i++) {
382 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
383 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
384 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
385 dmc_header->mmioaddr[i]);
386 return NULL;
387 }
388 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
389 csr->mmiodata[i] = dmc_header->mmiodata[i];
390 }
391
392 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
393 nbytes = dmc_header->fw_size * 4;
394 if (nbytes > CSR_MAX_FW_SIZE) {
395 DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
396 return NULL;
397 }
398 csr->dmc_fw_size = dmc_header->fw_size;
399
400 dmc_payload = kmalloc(nbytes, GFP_KERNEL);
401 if (!dmc_payload) {
402 DRM_ERROR("Memory allocation failed for dmc payload\n");
403 return NULL;
404 }
405
406 return memcpy(dmc_payload, &fw->data[readcount], nbytes);
407 }
408
csr_load_work_fn(struct work_struct * work)409 static void csr_load_work_fn(struct work_struct *work)
410 {
411 struct drm_i915_private *dev_priv;
412 struct intel_csr *csr;
413 const struct firmware *fw = NULL;
414
415 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
416 csr = &dev_priv->csr;
417
418 request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
419 if (fw)
420 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
421
422 if (dev_priv->csr.dmc_payload) {
423 intel_csr_load_program(dev_priv);
424
425 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
426
427 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
428 dev_priv->csr.fw_path,
429 CSR_VERSION_MAJOR(csr->version),
430 CSR_VERSION_MINOR(csr->version));
431 } else {
432 dev_notice(dev_priv->drm.dev,
433 "Failed to load DMC firmware %s."
434 " Disabling runtime power management.\n",
435 csr->fw_path);
436 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
437 INTEL_UC_FIRMWARE_URL);
438 }
439
440 release_firmware(fw);
441 }
442
443 /**
444 * intel_csr_ucode_init() - initialize the firmware loading.
445 * @dev_priv: i915 drm device.
446 *
447 * This function is called at the time of loading the display driver to read
448 * firmware from a .bin file and copied into a internal memory.
449 */
intel_csr_ucode_init(struct drm_i915_private * dev_priv)450 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
451 {
452 struct intel_csr *csr = &dev_priv->csr;
453
454 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
455
456 if (!HAS_CSR(dev_priv))
457 return;
458
459 if (i915_modparams.dmc_firmware_path)
460 csr->fw_path = i915_modparams.dmc_firmware_path;
461 else if (IS_CANNONLAKE(dev_priv))
462 csr->fw_path = I915_CSR_CNL;
463 else if (IS_GEMINILAKE(dev_priv))
464 csr->fw_path = I915_CSR_GLK;
465 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
466 csr->fw_path = I915_CSR_KBL;
467 else if (IS_SKYLAKE(dev_priv))
468 csr->fw_path = I915_CSR_SKL;
469 else if (IS_BROXTON(dev_priv))
470 csr->fw_path = I915_CSR_BXT;
471 else {
472 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
473 return;
474 }
475
476 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
477
478 /*
479 * Obtain a runtime pm reference, until CSR is loaded,
480 * to avoid entering runtime-suspend.
481 */
482 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
483
484 schedule_work(&dev_priv->csr.work);
485 }
486
487 /**
488 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
489 * @dev_priv: i915 drm device
490 *
491 * Prepare the DMC firmware before entering system suspend. This includes
492 * flushing pending work items and releasing any resources acquired during
493 * init.
494 */
intel_csr_ucode_suspend(struct drm_i915_private * dev_priv)495 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
496 {
497 if (!HAS_CSR(dev_priv))
498 return;
499
500 flush_work(&dev_priv->csr.work);
501
502 /* Drop the reference held in case DMC isn't loaded. */
503 if (!dev_priv->csr.dmc_payload)
504 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
505 }
506
507 /**
508 * intel_csr_ucode_resume() - init CSR firmware during system resume
509 * @dev_priv: i915 drm device
510 *
511 * Reinitialize the DMC firmware during system resume, reacquiring any
512 * resources released in intel_csr_ucode_suspend().
513 */
intel_csr_ucode_resume(struct drm_i915_private * dev_priv)514 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
515 {
516 if (!HAS_CSR(dev_priv))
517 return;
518
519 /*
520 * Reacquire the reference to keep RPM disabled in case DMC isn't
521 * loaded.
522 */
523 if (!dev_priv->csr.dmc_payload)
524 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
525 }
526
527 /**
528 * intel_csr_ucode_fini() - unload the CSR firmware.
529 * @dev_priv: i915 drm device.
530 *
531 * Firmmware unloading includes freeing the internal memory and reset the
532 * firmware loading status.
533 */
intel_csr_ucode_fini(struct drm_i915_private * dev_priv)534 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
535 {
536 if (!HAS_CSR(dev_priv))
537 return;
538
539 intel_csr_ucode_suspend(dev_priv);
540
541 kfree(dev_priv->csr.dmc_payload);
542 }
543
