Searched refs:divsel (Results 1 – 3 of 3) sorted by relevance
503 u32 divsel; member510 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,515 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,1423 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()1577 u32 divsel; in dsiclk_rate() local1580 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()1581 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()1583 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()1584 divsel = dsiclk[n].divsel; in dsiclk_rate()1586 dsiclk[n].divsel = divsel; in dsiclk_rate()[all …]
745 u32 divsel:1; member768 pll_div->divsel = 1; in pll_factors()777 pll_div->divsel = 0; in pll_factors()838 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()843 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
4425 u32 divsel, phaseinc, auxdiv, phasedir = 0; in lpt_program_iclkip() local4443 divsel = (desired_divisor / iclk_pi_range) - 2; in lpt_program_iclkip()4450 if (divsel <= 0x7f) in lpt_program_iclkip()4455 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & in lpt_program_iclkip()4463 divsel, in lpt_program_iclkip()4472 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); in lpt_program_iclkip()4500 u32 divsel, phaseinc, auxdiv; in lpt_get_iclkip() local4518 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> in lpt_get_iclkip()4529 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; in lpt_get_iclkip()
