| /Linux-v4.19/drivers/clk/imx/ |
| D | clk-pllv3.c | 49 u32 div_mask; member
119 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
147 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
167 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
202 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
224 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
289 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
357 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; in clk_pllv3_vf610_recalc_rate()
380 val &= ~pll->div_mask; /* clear bit for mfi=20 */ in clk_pllv3_vf610_set_rate()
382 val |= pll->div_mask; /* set bit for mfi=22 */ in clk_pllv3_vf610_set_rate()
[all …]
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| D | clk-fixup-div.c | 18 #define div_mask(d) ((1 << (d->width)) - 1) macro
72 if (value > div_mask(div)) in clk_fixup_div_set_rate()
73 value = div_mask(div); in clk_fixup_div_set_rate()
78 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
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| D | clk.h | 43 const char *parent_name, void __iomem *base, u32 div_mask);
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| /Linux-v4.19/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 10 #define div_mask(width) ((1 << (width)) - 1) macro
28 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
45 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
87 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
117 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
125 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
128 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
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| /Linux-v4.19/drivers/clk/tegra/ |
| D | clk-utils.c | 10 #define div_mask(w) ((1 << (w)) - 1) macro
39 if (divider_ux1 > div_mask(width)) in div_frac_get()
40 return div_mask(width); in div_frac_get()
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| D | clk-divider.c | 26 #define div_mask(d) ((1 << (d->width)) - 1) macro
28 #define get_max_div(d) div_mask(d)
55 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
102 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
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| /Linux-v4.19/drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 23 #define div_mask(width) ((1 << (width)) - 1) macro
56 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
86 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
121 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
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| /Linux-v4.19/drivers/i2c/busses/ |
| D | i2c-brcmstb.c | 94 u32 div_mask; member
126 .div_mask = 0
131 .div_mask = 0
136 .div_mask = 0
141 .div_mask = 0
146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
560 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
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| /Linux-v4.19/drivers/clk/ |
| D | clk-vt8500.c | 32 unsigned int div_mask; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
130 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
135 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
178 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
190 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
271 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
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| /Linux-v4.19/drivers/clk/ti/ |
| D | divider.c | 29 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
45 return div_mask(divider); in _get_maxdiv()
47 return 1 << div_mask(divider); in _get_maxdiv()
50 return div_mask(divider) + 1; in _get_maxdiv()
104 val &= div_mask(divider); in ti_clk_divider_recalc_rate()
254 if (value > div_mask(divider)) in ti_clk_divider_set_rate()
255 value = div_mask(divider); in ti_clk_divider_set_rate()
258 val = div_mask(divider) << (divider->shift + 16); in ti_clk_divider_set_rate()
261 val &= ~(div_mask(divider) << divider->shift); in ti_clk_divider_set_rate()
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| /Linux-v4.19/include/linux/ |
| D | sh_clk.h | 60 unsigned int div_mask; member
157 .div_mask = SH_CLK_DIV4_MSK, \
181 .div_mask = SH_CLK_DIV6_MSK, \
193 .div_mask = SH_CLK_DIV6_MSK, \
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| /Linux-v4.19/drivers/clk/actions/ |
| D | owl-factor.c | 159 val &= div_mask(factor_hw); in owl_factor_helper_recalc_rate()
194 if (val > div_mask(factor_hw)) in owl_factor_helper_set_rate()
195 val = div_mask(factor_hw); in owl_factor_helper_set_rate()
199 reg &= ~(div_mask(factor_hw) << factor_hw->shift); in owl_factor_helper_set_rate()
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| D | owl-factor.h | 58 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
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| /Linux-v4.19/drivers/clk/samsung/ |
| D | clk-cpu.c | 232 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
254 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
257 exynos_set_safe_div(base, div, div_mask); in exynos_cpuclk_post_rate_change()
342 unsigned long div = 0, div_mask = DIV_MASK; in exynos5433_cpuclk_post_rate_change() local
353 exynos5433_set_safe_div(base, div, div_mask); in exynos5433_cpuclk_post_rate_change()
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| /Linux-v4.19/drivers/sh/clk/ |
| D | cpg.c | 138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
167 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()
190 val |= clk->div_mask; in sh_clk_div_disable()
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| /Linux-v4.19/drivers/clk/mmp/ |
| D | clk-mix.c | 29 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
34 return div_mask; in _get_maxdiv()
36 return 1 << div_mask; in _get_maxdiv()
43 return div_mask + 1; in _get_maxdiv()
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| /Linux-v4.19/drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 925 #define div_mask(width) ((1 << (width)) - 1) macro
957 val &= div_mask(divider->width); in clk_divider_recalc_rate()
973 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
993 div_mask(divider->width) << divider->shift, in clk_divider_set_rate()
1481 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) in lpc32xx_clk_div_quirk() argument
1487 if (!(val & div_mask)) { in lpc32xx_clk_div_quirk()
1489 val |= BIT(__ffs(div_mask)); in lpc32xx_clk_div_quirk()
1492 regmap_update_bits(clk_regmap, reg, gate | div_mask, val); in lpc32xx_clk_div_quirk()
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| /Linux-v4.19/drivers/mfd/ |
| D | db8500-prcmu.c | 521 u32 div_mask; member
528 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
533 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
538 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
732 u32 div_mask; in prcmu_config_clkout() local
742 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()
747 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()
758 if (val & div_mask) { in prcmu_config_clkout()
765 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()
1606 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
[all …]
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| /Linux-v4.19/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_14nm.c | 684 #define div_mask(width) ((1 << (width)) - 1) macro
698 val &= div_mask(width); in dsi_pll_14nm_postdiv_recalc_rate()
740 val &= ~(div_mask(width) << shift); in dsi_pll_14nm_postdiv_set_rate()
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