Searched refs:dev_base (Results 1 – 5 of 5) sorted by relevance
298 int dev_base, dev_limit; in early_gart_iommu_check() local301 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in early_gart_iommu_check()304 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()354 int dev_base, dev_limit; in early_gart_iommu_check() local357 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in early_gart_iommu_check()360 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()398 int dev_base, dev_limit; in gart_iommu_hole_init() local402 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in gart_iommu_hole_init()405 for (slot = dev_base; slot < dev_limit; slot++) { in gart_iommu_hole_init()522 int bus, dev_base, dev_limit; in gart_iommu_hole_init() local[all …]
42 u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); in pci_exp_set_dev_base() local44 if (dev_base != mmcfg_last_accessed_device || in pci_exp_set_dev_base()46 mmcfg_last_accessed_device = dev_base; in pci_exp_set_dev_base()48 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); in pci_exp_set_dev_base()
350 u8 slot = amd_nb_bus_dev_ranges[i].dev_base; in pci_enable_pci_io_ecs()
661 u32 dev_base; member711 u32 dev_base = bus->number << 24 | devfn << 16; in mpc83xx_pcie_remap_cfg() local724 if (pcie->dev_base == dev_base) in mpc83xx_pcie_remap_cfg()727 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); in mpc83xx_pcie_remap_cfg()729 pcie->dev_base = dev_base; in mpc83xx_pcie_remap_cfg()
11 u8 dev_base; member
