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Searched refs:dbi_base (Results 1 – 18 of 18) sorted by relevance

/Linux-v4.19/drivers/pci/controller/dwc/
Dpcie-spear13xx.c92 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); in spear13xx_pcie_establish_link()
94 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); in spear13xx_pcie_establish_link()
96 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A); in spear13xx_pcie_establish_link()
97 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); in spear13xx_pcie_establish_link()
104 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, in spear13xx_pcie_establish_link()
109 dw_pcie_write(pci->dbi_base + exp_cap_off + in spear13xx_pcie_establish_link()
113 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, in spear13xx_pcie_establish_link()
118 dw_pcie_write(pci->dbi_base + exp_cap_off + in spear13xx_pcie_establish_link()
234 struct resource *dbi_base; in spear13xx_pcie_probe() local
273 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in spear13xx_pcie_probe()
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Dpci-layerscape.c61 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_is_bridge()
72 iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_clear_multifunction()
81 val = ioread32(pci->dbi_base + PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
83 iowrite32(val, pci->dbi_base + PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
131 iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); in ls_pcie_fix_error_response()
297 struct resource *dbi_base; in ls_pcie_probe() local
315 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_probe()
316 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); in ls_pcie_probe()
317 if (IS_ERR(pci->dbi_base)) in ls_pcie_probe()
318 return PTR_ERR(pci->dbi_base); in ls_pcie_probe()
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Dpcie-designware.h216 void __iomem *dbi_base; member
250 __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val); in dw_pcie_writel_dbi()
255 return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4); in dw_pcie_readl_dbi()
260 __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val); in dw_pcie_writew_dbi()
265 return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2); in dw_pcie_readw_dbi()
270 __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val); in dw_pcie_writeb_dbi()
275 return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1); in dw_pcie_readb_dbi()
Dpci-dra7xx.c147 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, in dra7xx_pcie_establish_link()
152 dw_pcie_write(pci->dbi_base + exp_cap_off + in dra7xx_pcie_establish_link()
156 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, in dra7xx_pcie_establish_link()
161 dw_pcie_write(pci->dbi_base + exp_cap_off + in dra7xx_pcie_establish_link()
410 pci->dbi_base = devm_ioremap_resource(dev, res); in dra7xx_add_pcie_ep()
411 if (IS_ERR(pci->dbi_base)) in dra7xx_add_pcie_ep()
412 return PTR_ERR(pci->dbi_base); in dra7xx_add_pcie_ep()
463 pci->dbi_base = devm_ioremap_resource(dev, res); in dra7xx_add_pcie_port()
464 if (IS_ERR(pci->dbi_base)) in dra7xx_add_pcie_port()
465 return PTR_ERR(pci->dbi_base); in dra7xx_add_pcie_port()
Dpcie-qcom.c355 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_init_2_1_0()
357 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_init_2_1_0()
1047 writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); in qcom_pcie_init_2_3_3()
1048 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); in qcom_pcie_init_2_3_3()
1049 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); in qcom_pcie_init_2_3_3()
1051 val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); in qcom_pcie_init_2_3_3()
1053 writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); in qcom_pcie_init_2_3_3()
1055 writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + in qcom_pcie_init_2_3_3()
1081 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1141 *val = readl(pci->dbi_base + PCI_CLASS_REVISION); in qcom_pcie_rd_own_conf()
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Dpci-keystone-dw.c342 return pci->dbi_base; in ks_pcie_cfg_setup()
453 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); in ks_dw_pcie_host_init()
454 if (IS_ERR(pci->dbi_base)) in ks_dw_pcie_host_init()
455 return PTR_ERR(pci->dbi_base); in ks_dw_pcie_host_init()
461 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; in ks_dw_pcie_host_init()
Dpcie-designware-plat.c205 pci->dbi_base = devm_ioremap_resource(dev, res); in dw_plat_pcie_probe()
206 if (IS_ERR(pci->dbi_base)) in dw_plat_pcie_probe()
207 return PTR_ERR(pci->dbi_base); in dw_plat_pcie_probe()
Dpcie-histb.c132 ret = dw_pcie_read(pci->dbi_base + where, size, val); in histb_pcie_rd_own_conf()
145 ret = dw_pcie_write(pci->dbi_base + where, size, val); in histb_pcie_wr_own_conf()
335 pci->dbi_base = devm_ioremap_resource(dev, res); in histb_pcie_probe()
336 if (IS_ERR(pci->dbi_base)) { in histb_pcie_probe()
338 return PTR_ERR(pci->dbi_base); in histb_pcie_probe()
Dpcie-artpec6.c490 struct resource *dbi_base; in artpec6_pcie_probe() local
521 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in artpec6_pcie_probe()
522 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); in artpec6_pcie_probe()
523 if (IS_ERR(pci->dbi_base)) in artpec6_pcie_probe()
524 return PTR_ERR(pci->dbi_base); in artpec6_pcie_probe()
Dpcie-armada8k.c245 pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); in armada8k_pcie_probe()
246 if (IS_ERR(pci->dbi_base)) { in armada8k_pcie_probe()
248 ret = PTR_ERR(pci->dbi_base); in armada8k_pcie_probe()
Dpcie-kirin.c166 kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); in kirin_pcie_get_resource()
167 if (IS_ERR(kirin_pcie->pci->dbi_base)) in kirin_pcie_get_resource()
168 return PTR_ERR(kirin_pcie->pci->dbi_base); in kirin_pcie_get_resource()
346 ret = dw_pcie_read(pci->dbi_base + where, size, val); in kirin_pcie_rd_own_conf()
360 ret = dw_pcie_write(pci->dbi_base + where, size, val); in kirin_pcie_wr_own_conf()
Dpci-keystone.c270 pci->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
273 writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID); in ks_pcie_host_init()
276 val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); in ks_pcie_host_init()
280 writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); in ks_pcie_host_init()
Dpci-imx6.c690 struct resource *dbi_base; in imx6_pcie_probe() local
709 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); in imx6_pcie_probe()
710 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); in imx6_pcie_probe()
711 if (IS_ERR(pci->dbi_base)) in imx6_pcie_probe()
712 return PTR_ERR(pci->dbi_base); in imx6_pcie_probe()
Dpcie-hisi.c293 pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg); in hisi_pcie_probe()
294 if (IS_ERR(pci->dbi_base)) in hisi_pcie_probe()
295 return PTR_ERR(pci->dbi_base); in hisi_pcie_probe()
Dpcie-designware-host.c32 return dw_pcie_read(pci->dbi_base + where, size, val); in dw_pcie_rd_own_conf()
44 return dw_pcie_write(pci->dbi_base + where, size, val); in dw_pcie_wr_own_conf()
398 if (!pci->dbi_base) { in dw_pcie_host_init()
399 pci->dbi_base = devm_pci_remap_cfgspace(dev, in dw_pcie_host_init()
402 if (!pci->dbi_base) { in dw_pcie_host_init()
Dpci-exynos.c349 ret = dw_pcie_read(pci->dbi_base + where, size, val); in exynos_pcie_rd_own_conf()
362 ret = dw_pcie_write(pci->dbi_base + where, size, val); in exynos_pcie_wr_own_conf()
Dpcie-designware.c337 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1); in dw_pcie_link_up()
Dpcie-designware-ep.c503 if (!pci->dbi_base || !pci->dbi_base2) { in dw_pcie_ep_init()