1 /***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (C) 2003-2018 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28 #ifndef __CVMX_GMXX_DEFS_H__
29 #define __CVMX_GMXX_DEFS_H__
30
CVMX_GMXX_BAD_REG(unsigned long block_id)31 static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
32 {
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
35 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
36 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
37 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
38 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
40 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
41 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
42 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
43 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
44 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
45 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
46 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
47 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
48 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull;
49 }
50 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
51 }
52
CVMX_GMXX_BIST(unsigned long block_id)53 static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
54 {
55 switch (cvmx_get_octeon_family()) {
56 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
57 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
58 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
59 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
60 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
61 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
63 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
66 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
68 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
69 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
70 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull;
71 }
72 return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
73 }
74
75 #define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
76 #define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull)
CVMX_GMXX_CLK_EN(unsigned long block_id)77 static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
78 {
79 switch (cvmx_get_octeon_family()) {
80 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
81 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
82 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
83 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
84 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
85 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
86 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
87 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
88 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
89 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull;
90 }
91 return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
92 }
93
94 #define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull)
95 #define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull)
CVMX_GMXX_HG2_CONTROL(unsigned long block_id)96 static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
97 {
98 switch (cvmx_get_octeon_family()) {
99 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
100 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
101 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
102 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
103 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
104 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
105 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
106 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
107 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
108 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
109 }
110 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
111 }
112
CVMX_GMXX_INF_MODE(unsigned long block_id)113 static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
114 {
115 switch (cvmx_get_octeon_family()) {
116 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
117 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
118 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
119 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
120 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
121 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
122 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
123 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
124 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
125 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
126 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
127 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
128 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
129 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
130 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
131 }
132 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
133 }
134
CVMX_GMXX_NXA_ADR(unsigned long block_id)135 static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
136 {
137 switch (cvmx_get_octeon_family()) {
138 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
139 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
140 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
141 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
142 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
143 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
144 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
145 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
146 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
147 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
149 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
150 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull;
153 }
154 return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
155 }
156
157 #define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull)
CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset,unsigned long block_id)158 static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
159 {
160 switch (cvmx_get_octeon_family()) {
161 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
162 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
163 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
164 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
165 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
166 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
167 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
169 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
170 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull;
171 }
172 return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
173 }
174
CVMX_GMXX_PRTX_CFG(unsigned long offset,unsigned long block_id)175 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
176 {
177 switch (cvmx_get_octeon_family()) {
178 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
179 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
180 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
181 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
182 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
183 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
184 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
185 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
186 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
187 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
188 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
189 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
190 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
191 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
192 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
193 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
194 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
195 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
196 }
197 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
198 }
199
200 #define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull)
CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset,unsigned long block_id)201 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
202 {
203 switch (cvmx_get_octeon_family()) {
204 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
205 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
206 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
207 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
208 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
209 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
210 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
211 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
212 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
213 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
214 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
215 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
216 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
217 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
218 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
219 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
220 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
221 }
222 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
223 }
224
CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset,unsigned long block_id)225 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
226 {
227 switch (cvmx_get_octeon_family()) {
228 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
229 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
230 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
231 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
232 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
233 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
234 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
235 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
236 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
237 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
238 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
239 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
240 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
241 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
242 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
243 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
244 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
245 }
246 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
247 }
248
CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset,unsigned long block_id)249 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
250 {
251 switch (cvmx_get_octeon_family()) {
252 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
253 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
254 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
255 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
256 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
257 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
258 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
259 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
260 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
261 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
262 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
263 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
264 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
265 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
266 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
267 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
268 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
269 }
270 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
271 }
272
CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset,unsigned long block_id)273 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
274 {
275 switch (cvmx_get_octeon_family()) {
276 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
277 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
278 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
279 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
280 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
281 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
282 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
283 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
284 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
285 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
286 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
287 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
288 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
289 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
290 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
291 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
292 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
293 }
294 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
295 }
296
CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset,unsigned long block_id)297 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
298 {
299 switch (cvmx_get_octeon_family()) {
300 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
301 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
302 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
303 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
304 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
305 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
306 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
307 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
308 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
309 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
310 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
311 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
312 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
313 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
314 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
315 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
316 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
317 }
318 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
319 }
320
CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset,unsigned long block_id)321 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
322 {
323 switch (cvmx_get_octeon_family()) {
324 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
325 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
326 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
327 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
328 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
329 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
330 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
331 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
332 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
333 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
334 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
335 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
336 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
337 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
338 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
339 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
340 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
341 }
342 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
343 }
344
CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset,unsigned long block_id)345 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
346 {
347 switch (cvmx_get_octeon_family()) {
348 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
349 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
350 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
351 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
352 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
353 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
354 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
355 }
356 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
357 }
358
CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset,unsigned long block_id)359 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
360 {
361 switch (cvmx_get_octeon_family()) {
362 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
363 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
364 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
365 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
366 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
367 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
368 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
369 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
370 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
371 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
372 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
373 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
374 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
375 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
376 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
377 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
378 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
379 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
380 }
381 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
382 }
383
CVMX_GMXX_RXX_ADR_CTL(unsigned long offset,unsigned long block_id)384 static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
385 {
386 switch (cvmx_get_octeon_family()) {
387 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
388 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
389 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
390 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
391 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
392 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
393 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
394 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
395 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
396 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
397 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
398 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
399 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
400 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
401 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
402 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
403 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
404 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
405 }
406 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
407 }
408
CVMX_GMXX_RXX_DECISION(unsigned long offset,unsigned long block_id)409 static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
410 {
411 switch (cvmx_get_octeon_family()) {
412 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
413 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
414 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
415 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
416 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
417 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
418 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
419 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
420 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
421 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
422 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
423 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
424 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
425 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
426 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
427 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048;
428 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
429 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
430 }
431 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
432 }
433
CVMX_GMXX_RXX_FRM_CHK(unsigned long offset,unsigned long block_id)434 static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
435 {
436 switch (cvmx_get_octeon_family()) {
437 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
438 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
439 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
440 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
441 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
442 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
443 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
444 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
445 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
446 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
447 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
448 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
449 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
450 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
451 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
452 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048;
453 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
454 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
455 }
456 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
457 }
458
CVMX_GMXX_RXX_FRM_CTL(unsigned long offset,unsigned long block_id)459 static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
460 {
461 switch (cvmx_get_octeon_family()) {
462 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
463 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
464 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
465 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
466 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
467 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
468 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
469 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
470 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
471 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
472 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
473 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
474 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
475 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
476 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
477 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
478 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
479 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
480 }
481 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
482 }
483
484 #define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
485 #define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
CVMX_GMXX_RXX_IFG(unsigned long offset,unsigned long block_id)486 static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
487 {
488 switch (cvmx_get_octeon_family()) {
489 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
490 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
491 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
492 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
493 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
494 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
495 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
496 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
497 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
498 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
499 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
500 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
501 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
502 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
503 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
504 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048;
505 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
506 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
507 }
508 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
509 }
510
CVMX_GMXX_RXX_INT_EN(unsigned long offset,unsigned long block_id)511 static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
512 {
513 switch (cvmx_get_octeon_family()) {
514 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
515 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
516 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
517 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
518 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
519 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
520 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
521 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
522 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
523 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
524 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
525 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
526 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
527 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
528 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
529 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
530 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
531 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
532 }
533 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
534 }
535
CVMX_GMXX_RXX_INT_REG(unsigned long offset,unsigned long block_id)536 static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
537 {
538 switch (cvmx_get_octeon_family()) {
539 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
540 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
541 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
542 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
543 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
544 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
545 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
546 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
547 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
548 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
549 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
550 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
551 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
552 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
553 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
554 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
555 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
556 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
557 }
558 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
559 }
560
CVMX_GMXX_RXX_JABBER(unsigned long offset,unsigned long block_id)561 static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
562 {
563 switch (cvmx_get_octeon_family()) {
564 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
565 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
566 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
567 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
568 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
569 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
570 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
571 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
572 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
573 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
574 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
575 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
576 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
577 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
578 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
579 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
580 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
581 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
582 }
583 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
584 }
585
CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset,unsigned long block_id)586 static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
587 {
588 switch (cvmx_get_octeon_family()) {
589 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
590 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
591 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
592 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
593 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
594 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
595 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
596 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
597 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
598 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
599 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
600 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
601 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048;
602 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
603 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
604 }
605 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
606 }
607
608 #define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
CVMX_GMXX_RXX_STATS_CTL(unsigned long offset,unsigned long block_id)609 static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
610 {
611 switch (cvmx_get_octeon_family()) {
612 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
613 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
614 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
615 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
616 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
617 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
618 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
619 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
620 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
621 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
622 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
623 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
624 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
625 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
626 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
627 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048;
628 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
629 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
630 }
631 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
632 }
633
CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset,unsigned long block_id)634 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
635 {
636 switch (cvmx_get_octeon_family()) {
637 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
638 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
639 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
640 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
641 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
642 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
643 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
644 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
645 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
646 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
647 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
648 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
649 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
650 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
651 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
652 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048;
653 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
654 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
655 }
656 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
657 }
658
CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset,unsigned long block_id)659 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
660 {
661 switch (cvmx_get_octeon_family()) {
662 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
663 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
664 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
665 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
666 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
667 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
668 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
669 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
670 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
671 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
672 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
673 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
674 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
675 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
676 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
677 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048;
678 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
679 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
680 }
681 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
682 }
683
CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset,unsigned long block_id)684 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
685 {
686 switch (cvmx_get_octeon_family()) {
687 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
688 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
689 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
690 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
691 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
692 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
693 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
694 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
695 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
696 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
697 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
698 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
699 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
700 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
701 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
702 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
703 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
704 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
705 }
706 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
707 }
708
CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset,unsigned long block_id)709 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
710 {
711 switch (cvmx_get_octeon_family()) {
712 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
713 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
714 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
715 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
716 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
717 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
718 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
719 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
720 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
721 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
722 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
723 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
724 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
725 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
726 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
727 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
728 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
729 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
730 }
731 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
732 }
733
CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset,unsigned long block_id)734 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
735 {
736 switch (cvmx_get_octeon_family()) {
737 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
738 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
739 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
740 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
741 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
742 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
743 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
744 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
745 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
746 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
747 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
748 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
749 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
750 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
751 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
752 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048;
753 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
754 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
755 }
756 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
757 }
758
CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset,unsigned long block_id)759 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
760 {
761 switch (cvmx_get_octeon_family()) {
762 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
763 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
764 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
765 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
766 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
767 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
768 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
769 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
770 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
771 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
772 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
773 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
774 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
775 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
776 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
777 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
778 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
779 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
780 }
781 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
782 }
783
CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset,unsigned long block_id)784 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
785 {
786 switch (cvmx_get_octeon_family()) {
787 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
788 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
789 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
790 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
791 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
792 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
793 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
794 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
795 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
796 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
797 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
798 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
799 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
800 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
801 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
802 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048;
803 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
804 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
805 }
806 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
807 }
808
CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset,unsigned long block_id)809 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
810 {
811 switch (cvmx_get_octeon_family()) {
812 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
813 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
814 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
815 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
816 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
817 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
818 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
819 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
820 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
821 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
822 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
823 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
824 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
825 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
826 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
827 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
828 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
829 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
830 }
831 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
832 }
833
CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset,unsigned long block_id)834 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
835 {
836 switch (cvmx_get_octeon_family()) {
837 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
838 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
839 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
840 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
841 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
842 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
843 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
844 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
845 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
846 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
847 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
848 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
849 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
850 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
851 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
852 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
853 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
854 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
855 }
856 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
857 }
858
CVMX_GMXX_RXX_UDD_SKP(unsigned long offset,unsigned long block_id)859 static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
860 {
861 switch (cvmx_get_octeon_family()) {
862 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
863 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
864 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
865 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
866 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
867 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
868 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
869 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
870 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
871 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
872 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
873 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
874 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
875 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
876 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
877 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048;
878 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
879 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
880 }
881 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
882 }
883
CVMX_GMXX_RX_BP_DROPX(unsigned long offset,unsigned long block_id)884 static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
885 {
886 switch (cvmx_get_octeon_family()) {
887 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
888 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
889 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
890 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
891 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
892 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
893 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
894 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
895 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
896 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
897 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
898 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
899 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
900 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
901 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
902 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8;
903 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
904 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8;
905 }
906 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
907 }
908
CVMX_GMXX_RX_BP_OFFX(unsigned long offset,unsigned long block_id)909 static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
910 {
911 switch (cvmx_get_octeon_family()) {
912 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
913 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
914 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
915 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
916 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
917 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
918 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
919 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
920 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
921 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
922 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
923 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
924 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
925 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
926 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
927 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8;
928 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
929 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8;
930 }
931 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
932 }
933
CVMX_GMXX_RX_BP_ONX(unsigned long offset,unsigned long block_id)934 static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
935 {
936 switch (cvmx_get_octeon_family()) {
937 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
938 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
939 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
940 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
941 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
942 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
943 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
944 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
945 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
946 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
947 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
948 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
949 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
950 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
951 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
952 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8;
953 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
954 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8;
955 }
956 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
957 }
958
CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)959 static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
960 {
961 switch (cvmx_get_octeon_family()) {
962 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
963 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
964 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
965 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
966 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
967 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
968 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
969 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
970 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
971 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull;
972 }
973 return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
974 }
975
976 #define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull)
977 #define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
CVMX_GMXX_RX_PRTS(unsigned long block_id)978 static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
979 {
980 switch (cvmx_get_octeon_family()) {
981 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
982 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
983 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
984 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
985 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
986 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
987 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
988 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
989 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
990 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
991 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
992 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
993 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
994 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
995 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
996 }
997 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
998 }
999
CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)1000 static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
1001 {
1002 switch (cvmx_get_octeon_family()) {
1003 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1004 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1005 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1006 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1007 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1008 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1009 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
1010 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1011 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1012 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1013 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1014 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1015 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
1016 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1017 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull;
1018 }
1019 return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
1020 }
1021
1022 #define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)1023 static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
1024 {
1025 switch (cvmx_get_octeon_family()) {
1026 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1027 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1028 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1029 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
1030 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1031 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1032 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1033 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
1034 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1035 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull;
1036 }
1037 return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
1038 }
1039
CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)1040 static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
1041 {
1042 switch (cvmx_get_octeon_family()) {
1043 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1044 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1045 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1046 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
1047 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1048 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1049 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1050 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
1051 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1052 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
1053 }
1054 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
1055 }
1056
CVMX_GMXX_SMACX(unsigned long offset,unsigned long block_id)1057 static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
1058 {
1059 switch (cvmx_get_octeon_family()) {
1060 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1061 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1062 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1063 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1064 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1065 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1066 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1067 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1068 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1069 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1070 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1071 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1072 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1073 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1074 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1075 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1076 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1077 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1078 }
1079 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1080 }
1081
CVMX_GMXX_SOFT_BIST(unsigned long block_id)1082 static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
1083 {
1084 switch (cvmx_get_octeon_family()) {
1085 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1086 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull;
1087 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1088 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull;
1089 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1090 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull;
1091 }
1092 return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull;
1093 }
1094
CVMX_GMXX_STAT_BP(unsigned long block_id)1095 static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
1096 {
1097 switch (cvmx_get_octeon_family()) {
1098 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1099 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1100 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1101 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1102 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1103 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1104 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
1105 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1106 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1107 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1108 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1109 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1110 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
1111 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1112 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull;
1113 }
1114 return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
1115 }
1116
CVMX_GMXX_TB_REG(unsigned long block_id)1117 static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id)
1118 {
1119 switch (cvmx_get_octeon_family()) {
1120 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1121 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1122 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
1123 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1124 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
1125 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1126 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull;
1127 }
1128 return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
1129 }
1130
CVMX_GMXX_TXX_APPEND(unsigned long offset,unsigned long block_id)1131 static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
1132 {
1133 switch (cvmx_get_octeon_family()) {
1134 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1135 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1136 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1137 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1138 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1139 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1140 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1141 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1142 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1143 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1144 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1145 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1146 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1147 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1148 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1149 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1150 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1151 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1152 }
1153 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1154 }
1155
CVMX_GMXX_TXX_BURST(unsigned long offset,unsigned long block_id)1156 static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
1157 {
1158 switch (cvmx_get_octeon_family()) {
1159 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1160 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1161 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1162 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1163 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1164 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1165 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1166 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1167 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1168 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1169 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1170 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1171 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1172 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1173 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1174 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1175 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1176 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1177 }
1178 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1179 }
1180
CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset,unsigned long block_id)1181 static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
1182 {
1183 switch (cvmx_get_octeon_family()) {
1184 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1185 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1186 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1187 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
1188 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1189 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1190 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1191 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
1192 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1193 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull;
1194 }
1195 return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
1196 }
1197
CVMX_GMXX_TXX_CBFC_XON(unsigned long offset,unsigned long block_id)1198 static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
1199 {
1200 switch (cvmx_get_octeon_family()) {
1201 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1202 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1203 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1204 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
1205 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1206 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1207 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1208 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
1209 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1210 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull;
1211 }
1212 return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
1213 }
1214
1215 #define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
CVMX_GMXX_TXX_CTL(unsigned long offset,unsigned long block_id)1216 static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
1217 {
1218 switch (cvmx_get_octeon_family()) {
1219 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1220 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1221 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1222 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1223 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1224 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1225 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1226 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1227 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1228 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1229 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1230 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1231 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1232 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1233 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1234 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1235 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1236 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1237 }
1238 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1239 }
1240
CVMX_GMXX_TXX_MIN_PKT(unsigned long offset,unsigned long block_id)1241 static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
1242 {
1243 switch (cvmx_get_octeon_family()) {
1244 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1245 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1246 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1247 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1248 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1249 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1250 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1251 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1252 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1253 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1254 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1255 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1256 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1257 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1258 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1259 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1260 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1261 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1262 }
1263 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1264 }
1265
CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset,unsigned long block_id)1266 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
1267 {
1268 switch (cvmx_get_octeon_family()) {
1269 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1270 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1271 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1272 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1273 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1274 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1275 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1276 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1277 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1278 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1279 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1280 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1281 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1282 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1283 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1284 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1285 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1286 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1287 }
1288 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1289 }
1290
CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset,unsigned long block_id)1291 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
1292 {
1293 switch (cvmx_get_octeon_family()) {
1294 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1295 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1296 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1297 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1298 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1299 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1300 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1301 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1302 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1303 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1304 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1305 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1306 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1307 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1308 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1309 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1310 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1311 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1312 }
1313 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1314 }
1315
CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset,unsigned long block_id)1316 static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
1317 {
1318 switch (cvmx_get_octeon_family()) {
1319 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1320 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1321 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1322 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1323 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1324 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1325 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1326 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1327 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1329 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1330 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1331 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1332 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1333 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1334 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1335 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1336 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1337 }
1338 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1339 }
1340
CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset,unsigned long block_id)1341 static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
1342 {
1343 switch (cvmx_get_octeon_family()) {
1344 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1345 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1346 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1347 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1348 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1349 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1350 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1351 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1352 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1353 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1354 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1355 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1356 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1357 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1358 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1359 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1360 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1361 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1362 }
1363 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1364 }
1365
1366 #define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset,unsigned long block_id)1367 static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
1368 {
1369 switch (cvmx_get_octeon_family()) {
1370 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1371 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1372 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1373 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1374 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1375 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1376 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1377 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1378 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1379 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1380 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1381 }
1382 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1383 }
1384
CVMX_GMXX_TXX_SLOT(unsigned long offset,unsigned long block_id)1385 static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
1386 {
1387 switch (cvmx_get_octeon_family()) {
1388 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1389 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1390 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1391 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1392 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1393 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1394 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1395 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1396 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1397 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1398 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1399 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1400 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1401 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1402 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1403 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1404 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1405 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1406 }
1407 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1408 }
1409
CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset,unsigned long block_id)1410 static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
1411 {
1412 switch (cvmx_get_octeon_family()) {
1413 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1414 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1415 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1416 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1417 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1418 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1419 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1420 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1421 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1422 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1423 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1424 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1425 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1426 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1427 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1428 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1429 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1430 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1431 }
1432 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1433 }
1434
CVMX_GMXX_TXX_STAT0(unsigned long offset,unsigned long block_id)1435 static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
1436 {
1437 switch (cvmx_get_octeon_family()) {
1438 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1439 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1440 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1441 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1442 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1443 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1444 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1445 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1446 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1447 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1448 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1449 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1450 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1451 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1452 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1453 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1454 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1455 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1456 }
1457 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1458 }
1459
CVMX_GMXX_TXX_STAT1(unsigned long offset,unsigned long block_id)1460 static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
1461 {
1462 switch (cvmx_get_octeon_family()) {
1463 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1464 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1465 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1466 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1467 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1468 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1469 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1470 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1471 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1472 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1473 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1474 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1475 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1476 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1477 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1478 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1479 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1480 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1481 }
1482 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1483 }
1484
CVMX_GMXX_TXX_STAT2(unsigned long offset,unsigned long block_id)1485 static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
1486 {
1487 switch (cvmx_get_octeon_family()) {
1488 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1489 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1490 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1491 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1492 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1493 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1494 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1495 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1496 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1497 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1498 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1499 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1500 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1501 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1502 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1503 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1504 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1505 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1506 }
1507 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1508 }
1509
CVMX_GMXX_TXX_STAT3(unsigned long offset,unsigned long block_id)1510 static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
1511 {
1512 switch (cvmx_get_octeon_family()) {
1513 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1514 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1515 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1516 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1517 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1518 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1519 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1520 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1521 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1522 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1523 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1524 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1525 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1526 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1527 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1528 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1529 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1530 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1531 }
1532 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1533 }
1534
CVMX_GMXX_TXX_STAT4(unsigned long offset,unsigned long block_id)1535 static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
1536 {
1537 switch (cvmx_get_octeon_family()) {
1538 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1539 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1540 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1541 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1542 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1543 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1544 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1545 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1546 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1547 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1548 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1549 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1550 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1551 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1552 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1553 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1554 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1555 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1556 }
1557 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1558 }
1559
CVMX_GMXX_TXX_STAT5(unsigned long offset,unsigned long block_id)1560 static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
1561 {
1562 switch (cvmx_get_octeon_family()) {
1563 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1564 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1565 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1566 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1567 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1568 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1569 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1570 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1571 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1572 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1573 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1574 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1575 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1576 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1577 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1578 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1579 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1580 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1581 }
1582 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1583 }
1584
CVMX_GMXX_TXX_STAT6(unsigned long offset,unsigned long block_id)1585 static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
1586 {
1587 switch (cvmx_get_octeon_family()) {
1588 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1589 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1590 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1591 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1592 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1593 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1594 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1595 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1596 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1597 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1598 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1599 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1600 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1601 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1602 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1603 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1604 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1605 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1606 }
1607 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1608 }
1609
CVMX_GMXX_TXX_STAT7(unsigned long offset,unsigned long block_id)1610 static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
1611 {
1612 switch (cvmx_get_octeon_family()) {
1613 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1614 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1615 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1616 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1617 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1618 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1619 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1620 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1621 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1622 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1623 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1624 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1625 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1626 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1627 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1628 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1629 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1630 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1631 }
1632 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1633 }
1634
CVMX_GMXX_TXX_STAT8(unsigned long offset,unsigned long block_id)1635 static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
1636 {
1637 switch (cvmx_get_octeon_family()) {
1638 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1639 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1640 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1641 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1642 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1643 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1644 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1645 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1646 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1647 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1648 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1649 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1650 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1651 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1652 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1653 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1654 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1655 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1656 }
1657 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1658 }
1659
CVMX_GMXX_TXX_STAT9(unsigned long offset,unsigned long block_id)1660 static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
1661 {
1662 switch (cvmx_get_octeon_family()) {
1663 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1664 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1665 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1666 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1667 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1668 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1669 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1670 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1671 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1672 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1673 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1674 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1675 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1676 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1677 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1678 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1679 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1680 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1681 }
1682 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1683 }
1684
CVMX_GMXX_TXX_STATS_CTL(unsigned long offset,unsigned long block_id)1685 static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
1686 {
1687 switch (cvmx_get_octeon_family()) {
1688 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1689 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1690 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1691 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1692 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1693 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1694 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1695 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1696 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1697 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1698 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1699 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1700 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1701 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1702 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1703 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1704 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1705 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1706 }
1707 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1708 }
1709
CVMX_GMXX_TXX_THRESH(unsigned long offset,unsigned long block_id)1710 static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
1711 {
1712 switch (cvmx_get_octeon_family()) {
1713 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1714 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1715 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1716 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1717 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1718 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1719 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1720 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1721 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1722 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1723 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1724 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1725 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1726 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1727 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1728 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
1729 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1730 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
1731 }
1732 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
1733 }
1734
CVMX_GMXX_TX_BP(unsigned long block_id)1735 static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
1736 {
1737 switch (cvmx_get_octeon_family()) {
1738 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1739 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1740 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1741 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1742 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1743 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1744 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
1745 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1746 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1747 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1748 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1749 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1750 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
1751 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1752 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull;
1753 }
1754 return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
1755 }
1756
1757 #define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)1758 static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
1759 {
1760 switch (cvmx_get_octeon_family()) {
1761 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1762 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1763 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1764 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1765 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1766 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1767 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
1768 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1769 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1770 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1771 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1772 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1773 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
1774 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1775 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull;
1776 }
1777 return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
1778 }
1779
CVMX_GMXX_TX_CORRUPT(unsigned long block_id)1780 static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
1781 {
1782 switch (cvmx_get_octeon_family()) {
1783 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1784 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1785 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1786 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1787 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1788 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1789 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
1790 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1791 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1792 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1793 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1794 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1795 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
1796 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1797 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull;
1798 }
1799 return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
1800 }
1801
CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)1802 static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
1803 {
1804 switch (cvmx_get_octeon_family()) {
1805 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1806 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1807 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1808 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
1809 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1810 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1811 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1812 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
1813 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1814 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull;
1815 }
1816 return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
1817 }
1818
CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)1819 static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
1820 {
1821 switch (cvmx_get_octeon_family()) {
1822 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1823 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1824 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1825 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
1826 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1827 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1828 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1829 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
1830 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1831 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull;
1832 }
1833 return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
1834 }
1835
CVMX_GMXX_TX_IFG(unsigned long block_id)1836 static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
1837 {
1838 switch (cvmx_get_octeon_family()) {
1839 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1840 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1841 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1842 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1843 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1844 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1845 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
1846 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1847 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1848 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1849 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1850 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1851 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
1852 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1853 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull;
1854 }
1855 return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
1856 }
1857
CVMX_GMXX_TX_INT_EN(unsigned long block_id)1858 static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
1859 {
1860 switch (cvmx_get_octeon_family()) {
1861 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1862 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1863 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1864 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1865 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1866 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1867 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
1868 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1869 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1870 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1871 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1872 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1873 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
1874 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1875 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
1876 }
1877 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
1878 }
1879
CVMX_GMXX_TX_INT_REG(unsigned long block_id)1880 static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
1881 {
1882 switch (cvmx_get_octeon_family()) {
1883 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1884 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1885 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1886 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1887 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1888 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1889 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
1890 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1891 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1892 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1893 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1894 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1895 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
1896 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1897 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
1898 }
1899 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
1900 }
1901
CVMX_GMXX_TX_JAM(unsigned long block_id)1902 static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
1903 {
1904 switch (cvmx_get_octeon_family()) {
1905 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1906 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1907 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1908 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1909 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1910 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1911 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
1912 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1913 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1914 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1915 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1916 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1917 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
1918 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1919 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull;
1920 }
1921 return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
1922 }
1923
CVMX_GMXX_TX_LFSR(unsigned long block_id)1924 static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
1925 {
1926 switch (cvmx_get_octeon_family()) {
1927 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1928 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1929 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1930 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1931 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1932 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1933 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
1934 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1935 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1936 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1937 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1938 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1939 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
1940 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1941 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull;
1942 }
1943 return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
1944 }
1945
CVMX_GMXX_TX_OVR_BP(unsigned long block_id)1946 static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
1947 {
1948 switch (cvmx_get_octeon_family()) {
1949 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1950 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1951 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1952 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1953 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1954 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1955 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
1956 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1957 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1958 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1959 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1960 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1961 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
1962 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1963 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
1964 }
1965 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
1966 }
1967
CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)1968 static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
1969 {
1970 switch (cvmx_get_octeon_family()) {
1971 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1972 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1973 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1974 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1975 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1976 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1977 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
1978 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
1979 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1980 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
1981 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
1982 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1983 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
1984 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1985 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull;
1986 }
1987 return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
1988 }
1989
CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)1990 static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
1991 {
1992 switch (cvmx_get_octeon_family()) {
1993 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
1994 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
1995 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
1996 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
1997 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1998 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1999 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
2000 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
2001 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
2002 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
2003 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
2004 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
2005 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
2006 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
2007 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull;
2008 }
2009 return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
2010 }
2011
CVMX_GMXX_TX_PRTS(unsigned long block_id)2012 static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
2013 {
2014 switch (cvmx_get_octeon_family()) {
2015 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
2016 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
2017 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
2018 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
2019 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
2020 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
2021 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
2022 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
2023 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
2024 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
2025 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
2026 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
2027 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
2028 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
2029 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
2030 }
2031 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
2032 }
2033
2034 #define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
2035 #define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull)
2036 #define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
2037 #define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
2038 #define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)2039 static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
2040 {
2041 switch (cvmx_get_octeon_family()) {
2042 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
2043 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
2044 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
2045 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
2046 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
2047 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
2048 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
2049 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
2050 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
2051 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
2052 }
2053 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
2054 }
2055
CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)2056 static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
2057 {
2058 switch (cvmx_get_octeon_family()) {
2059 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
2060 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
2061 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
2062 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
2063 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
2064 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
2065 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
2066 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
2067 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
2068 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull;
2069 }
2070 return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
2071 }
2072
2073 void __cvmx_interrupt_gmxx_enable(int interface);
2074
2075 union cvmx_gmxx_bad_reg {
2076 uint64_t u64;
2077 struct cvmx_gmxx_bad_reg_s {
2078 #ifdef __BIG_ENDIAN_BITFIELD
2079 uint64_t reserved_31_63:33;
2080 uint64_t inb_nxa:4;
2081 uint64_t statovr:1;
2082 uint64_t loststat:4;
2083 uint64_t reserved_18_21:4;
2084 uint64_t out_ovr:16;
2085 uint64_t ncb_ovr:1;
2086 uint64_t out_col:1;
2087 #else
2088 uint64_t out_col:1;
2089 uint64_t ncb_ovr:1;
2090 uint64_t out_ovr:16;
2091 uint64_t reserved_18_21:4;
2092 uint64_t loststat:4;
2093 uint64_t statovr:1;
2094 uint64_t inb_nxa:4;
2095 uint64_t reserved_31_63:33;
2096 #endif
2097 } s;
2098 struct cvmx_gmxx_bad_reg_cn30xx {
2099 #ifdef __BIG_ENDIAN_BITFIELD
2100 uint64_t reserved_31_63:33;
2101 uint64_t inb_nxa:4;
2102 uint64_t statovr:1;
2103 uint64_t reserved_25_25:1;
2104 uint64_t loststat:3;
2105 uint64_t reserved_5_21:17;
2106 uint64_t out_ovr:3;
2107 uint64_t reserved_0_1:2;
2108 #else
2109 uint64_t reserved_0_1:2;
2110 uint64_t out_ovr:3;
2111 uint64_t reserved_5_21:17;
2112 uint64_t loststat:3;
2113 uint64_t reserved_25_25:1;
2114 uint64_t statovr:1;
2115 uint64_t inb_nxa:4;
2116 uint64_t reserved_31_63:33;
2117 #endif
2118 } cn30xx;
2119 struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
2120 struct cvmx_gmxx_bad_reg_s cn38xx;
2121 struct cvmx_gmxx_bad_reg_s cn38xxp2;
2122 struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
2123 struct cvmx_gmxx_bad_reg_cn52xx {
2124 #ifdef __BIG_ENDIAN_BITFIELD
2125 uint64_t reserved_31_63:33;
2126 uint64_t inb_nxa:4;
2127 uint64_t statovr:1;
2128 uint64_t loststat:4;
2129 uint64_t reserved_6_21:16;
2130 uint64_t out_ovr:4;
2131 uint64_t reserved_0_1:2;
2132 #else
2133 uint64_t reserved_0_1:2;
2134 uint64_t out_ovr:4;
2135 uint64_t reserved_6_21:16;
2136 uint64_t loststat:4;
2137 uint64_t statovr:1;
2138 uint64_t inb_nxa:4;
2139 uint64_t reserved_31_63:33;
2140 #endif
2141 } cn52xx;
2142 struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
2143 struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
2144 struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
2145 struct cvmx_gmxx_bad_reg_s cn58xx;
2146 struct cvmx_gmxx_bad_reg_s cn58xxp1;
2147 struct cvmx_gmxx_bad_reg_cn52xx cn61xx;
2148 struct cvmx_gmxx_bad_reg_cn52xx cn63xx;
2149 struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;
2150 struct cvmx_gmxx_bad_reg_cn52xx cn66xx;
2151 struct cvmx_gmxx_bad_reg_cn52xx cn68xx;
2152 struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;
2153 struct cvmx_gmxx_bad_reg_cn52xx cnf71xx;
2154 };
2155
2156 union cvmx_gmxx_bist {
2157 uint64_t u64;
2158 struct cvmx_gmxx_bist_s {
2159 #ifdef __BIG_ENDIAN_BITFIELD
2160 uint64_t reserved_25_63:39;
2161 uint64_t status:25;
2162 #else
2163 uint64_t status:25;
2164 uint64_t reserved_25_63:39;
2165 #endif
2166 } s;
2167 struct cvmx_gmxx_bist_cn30xx {
2168 #ifdef __BIG_ENDIAN_BITFIELD
2169 uint64_t reserved_10_63:54;
2170 uint64_t status:10;
2171 #else
2172 uint64_t status:10;
2173 uint64_t reserved_10_63:54;
2174 #endif
2175 } cn30xx;
2176 struct cvmx_gmxx_bist_cn30xx cn31xx;
2177 struct cvmx_gmxx_bist_cn30xx cn38xx;
2178 struct cvmx_gmxx_bist_cn30xx cn38xxp2;
2179 struct cvmx_gmxx_bist_cn50xx {
2180 #ifdef __BIG_ENDIAN_BITFIELD
2181 uint64_t reserved_12_63:52;
2182 uint64_t status:12;
2183 #else
2184 uint64_t status:12;
2185 uint64_t reserved_12_63:52;
2186 #endif
2187 } cn50xx;
2188 struct cvmx_gmxx_bist_cn52xx {
2189 #ifdef __BIG_ENDIAN_BITFIELD
2190 uint64_t reserved_16_63:48;
2191 uint64_t status:16;
2192 #else
2193 uint64_t status:16;
2194 uint64_t reserved_16_63:48;
2195 #endif
2196 } cn52xx;
2197 struct cvmx_gmxx_bist_cn52xx cn52xxp1;
2198 struct cvmx_gmxx_bist_cn52xx cn56xx;
2199 struct cvmx_gmxx_bist_cn52xx cn56xxp1;
2200 struct cvmx_gmxx_bist_cn58xx {
2201 #ifdef __BIG_ENDIAN_BITFIELD
2202 uint64_t reserved_17_63:47;
2203 uint64_t status:17;
2204 #else
2205 uint64_t status:17;
2206 uint64_t reserved_17_63:47;
2207 #endif
2208 } cn58xx;
2209 struct cvmx_gmxx_bist_cn58xx cn58xxp1;
2210 struct cvmx_gmxx_bist_s cn61xx;
2211 struct cvmx_gmxx_bist_s cn63xx;
2212 struct cvmx_gmxx_bist_s cn63xxp1;
2213 struct cvmx_gmxx_bist_s cn66xx;
2214 struct cvmx_gmxx_bist_s cn68xx;
2215 struct cvmx_gmxx_bist_s cn68xxp1;
2216 struct cvmx_gmxx_bist_s cnf71xx;
2217 };
2218
2219 union cvmx_gmxx_bpid_mapx {
2220 uint64_t u64;
2221 struct cvmx_gmxx_bpid_mapx_s {
2222 #ifdef __BIG_ENDIAN_BITFIELD
2223 uint64_t reserved_17_63:47;
2224 uint64_t status:1;
2225 uint64_t reserved_9_15:7;
2226 uint64_t val:1;
2227 uint64_t reserved_6_7:2;
2228 uint64_t bpid:6;
2229 #else
2230 uint64_t bpid:6;
2231 uint64_t reserved_6_7:2;
2232 uint64_t val:1;
2233 uint64_t reserved_9_15:7;
2234 uint64_t status:1;
2235 uint64_t reserved_17_63:47;
2236 #endif
2237 } s;
2238 struct cvmx_gmxx_bpid_mapx_s cn68xx;
2239 struct cvmx_gmxx_bpid_mapx_s cn68xxp1;
2240 };
2241
2242 union cvmx_gmxx_bpid_msk {
2243 uint64_t u64;
2244 struct cvmx_gmxx_bpid_msk_s {
2245 #ifdef __BIG_ENDIAN_BITFIELD
2246 uint64_t reserved_48_63:16;
2247 uint64_t msk_or:16;
2248 uint64_t reserved_16_31:16;
2249 uint64_t msk_and:16;
2250 #else
2251 uint64_t msk_and:16;
2252 uint64_t reserved_16_31:16;
2253 uint64_t msk_or:16;
2254 uint64_t reserved_48_63:16;
2255 #endif
2256 } s;
2257 struct cvmx_gmxx_bpid_msk_s cn68xx;
2258 struct cvmx_gmxx_bpid_msk_s cn68xxp1;
2259 };
2260
2261 union cvmx_gmxx_clk_en {
2262 uint64_t u64;
2263 struct cvmx_gmxx_clk_en_s {
2264 #ifdef __BIG_ENDIAN_BITFIELD
2265 uint64_t reserved_1_63:63;
2266 uint64_t clk_en:1;
2267 #else
2268 uint64_t clk_en:1;
2269 uint64_t reserved_1_63:63;
2270 #endif
2271 } s;
2272 struct cvmx_gmxx_clk_en_s cn52xx;
2273 struct cvmx_gmxx_clk_en_s cn52xxp1;
2274 struct cvmx_gmxx_clk_en_s cn56xx;
2275 struct cvmx_gmxx_clk_en_s cn56xxp1;
2276 struct cvmx_gmxx_clk_en_s cn61xx;
2277 struct cvmx_gmxx_clk_en_s cn63xx;
2278 struct cvmx_gmxx_clk_en_s cn63xxp1;
2279 struct cvmx_gmxx_clk_en_s cn66xx;
2280 struct cvmx_gmxx_clk_en_s cn68xx;
2281 struct cvmx_gmxx_clk_en_s cn68xxp1;
2282 struct cvmx_gmxx_clk_en_s cnf71xx;
2283 };
2284
2285 union cvmx_gmxx_ebp_dis {
2286 uint64_t u64;
2287 struct cvmx_gmxx_ebp_dis_s {
2288 #ifdef __BIG_ENDIAN_BITFIELD
2289 uint64_t reserved_16_63:48;
2290 uint64_t dis:16;
2291 #else
2292 uint64_t dis:16;
2293 uint64_t reserved_16_63:48;
2294 #endif
2295 } s;
2296 struct cvmx_gmxx_ebp_dis_s cn68xx;
2297 struct cvmx_gmxx_ebp_dis_s cn68xxp1;
2298 };
2299
2300 union cvmx_gmxx_ebp_msk {
2301 uint64_t u64;
2302 struct cvmx_gmxx_ebp_msk_s {
2303 #ifdef __BIG_ENDIAN_BITFIELD
2304 uint64_t reserved_16_63:48;
2305 uint64_t msk:16;
2306 #else
2307 uint64_t msk:16;
2308 uint64_t reserved_16_63:48;
2309 #endif
2310 } s;
2311 struct cvmx_gmxx_ebp_msk_s cn68xx;
2312 struct cvmx_gmxx_ebp_msk_s cn68xxp1;
2313 };
2314
2315 union cvmx_gmxx_hg2_control {
2316 uint64_t u64;
2317 struct cvmx_gmxx_hg2_control_s {
2318 #ifdef __BIG_ENDIAN_BITFIELD
2319 uint64_t reserved_19_63:45;
2320 uint64_t hg2tx_en:1;
2321 uint64_t hg2rx_en:1;
2322 uint64_t phys_en:1;
2323 uint64_t logl_en:16;
2324 #else
2325 uint64_t logl_en:16;
2326 uint64_t phys_en:1;
2327 uint64_t hg2rx_en:1;
2328 uint64_t hg2tx_en:1;
2329 uint64_t reserved_19_63:45;
2330 #endif
2331 } s;
2332 struct cvmx_gmxx_hg2_control_s cn52xx;
2333 struct cvmx_gmxx_hg2_control_s cn52xxp1;
2334 struct cvmx_gmxx_hg2_control_s cn56xx;
2335 struct cvmx_gmxx_hg2_control_s cn61xx;
2336 struct cvmx_gmxx_hg2_control_s cn63xx;
2337 struct cvmx_gmxx_hg2_control_s cn63xxp1;
2338 struct cvmx_gmxx_hg2_control_s cn66xx;
2339 struct cvmx_gmxx_hg2_control_s cn68xx;
2340 struct cvmx_gmxx_hg2_control_s cn68xxp1;
2341 struct cvmx_gmxx_hg2_control_s cnf71xx;
2342 };
2343
2344 union cvmx_gmxx_inf_mode {
2345 uint64_t u64;
2346 struct cvmx_gmxx_inf_mode_s {
2347 #ifdef __BIG_ENDIAN_BITFIELD
2348 uint64_t reserved_20_63:44;
2349 uint64_t rate:4;
2350 uint64_t reserved_12_15:4;
2351 uint64_t speed:4;
2352 uint64_t reserved_7_7:1;
2353 uint64_t mode:3;
2354 uint64_t reserved_3_3:1;
2355 uint64_t p0mii:1;
2356 uint64_t en:1;
2357 uint64_t type:1;
2358 #else
2359 uint64_t type:1;
2360 uint64_t en:1;
2361 uint64_t p0mii:1;
2362 uint64_t reserved_3_3:1;
2363 uint64_t mode:3;
2364 uint64_t reserved_7_7:1;
2365 uint64_t speed:4;
2366 uint64_t reserved_12_15:4;
2367 uint64_t rate:4;
2368 uint64_t reserved_20_63:44;
2369 #endif
2370 } s;
2371 struct cvmx_gmxx_inf_mode_cn30xx {
2372 #ifdef __BIG_ENDIAN_BITFIELD
2373 uint64_t reserved_3_63:61;
2374 uint64_t p0mii:1;
2375 uint64_t en:1;
2376 uint64_t type:1;
2377 #else
2378 uint64_t type:1;
2379 uint64_t en:1;
2380 uint64_t p0mii:1;
2381 uint64_t reserved_3_63:61;
2382 #endif
2383 } cn30xx;
2384 struct cvmx_gmxx_inf_mode_cn31xx {
2385 #ifdef __BIG_ENDIAN_BITFIELD
2386 uint64_t reserved_2_63:62;
2387 uint64_t en:1;
2388 uint64_t type:1;
2389 #else
2390 uint64_t type:1;
2391 uint64_t en:1;
2392 uint64_t reserved_2_63:62;
2393 #endif
2394 } cn31xx;
2395 struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
2396 struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
2397 struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
2398 struct cvmx_gmxx_inf_mode_cn52xx {
2399 #ifdef __BIG_ENDIAN_BITFIELD
2400 uint64_t reserved_10_63:54;
2401 uint64_t speed:2;
2402 uint64_t reserved_6_7:2;
2403 uint64_t mode:2;
2404 uint64_t reserved_2_3:2;
2405 uint64_t en:1;
2406 uint64_t type:1;
2407 #else
2408 uint64_t type:1;
2409 uint64_t en:1;
2410 uint64_t reserved_2_3:2;
2411 uint64_t mode:2;
2412 uint64_t reserved_6_7:2;
2413 uint64_t speed:2;
2414 uint64_t reserved_10_63:54;
2415 #endif
2416 } cn52xx;
2417 struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
2418 struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
2419 struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
2420 struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
2421 struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
2422 struct cvmx_gmxx_inf_mode_cn61xx {
2423 #ifdef __BIG_ENDIAN_BITFIELD
2424 uint64_t reserved_12_63:52;
2425 uint64_t speed:4;
2426 uint64_t reserved_5_7:3;
2427 uint64_t mode:1;
2428 uint64_t reserved_2_3:2;
2429 uint64_t en:1;
2430 uint64_t type:1;
2431 #else
2432 uint64_t type:1;
2433 uint64_t en:1;
2434 uint64_t reserved_2_3:2;
2435 uint64_t mode:1;
2436 uint64_t reserved_5_7:3;
2437 uint64_t speed:4;
2438 uint64_t reserved_12_63:52;
2439 #endif
2440 } cn61xx;
2441 struct cvmx_gmxx_inf_mode_cn61xx cn63xx;
2442 struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;
2443 struct cvmx_gmxx_inf_mode_cn66xx {
2444 #ifdef __BIG_ENDIAN_BITFIELD
2445 uint64_t reserved_20_63:44;
2446 uint64_t rate:4;
2447 uint64_t reserved_12_15:4;
2448 uint64_t speed:4;
2449 uint64_t reserved_5_7:3;
2450 uint64_t mode:1;
2451 uint64_t reserved_2_3:2;
2452 uint64_t en:1;
2453 uint64_t type:1;
2454 #else
2455 uint64_t type:1;
2456 uint64_t en:1;
2457 uint64_t reserved_2_3:2;
2458 uint64_t mode:1;
2459 uint64_t reserved_5_7:3;
2460 uint64_t speed:4;
2461 uint64_t reserved_12_15:4;
2462 uint64_t rate:4;
2463 uint64_t reserved_20_63:44;
2464 #endif
2465 } cn66xx;
2466 struct cvmx_gmxx_inf_mode_cn68xx {
2467 #ifdef __BIG_ENDIAN_BITFIELD
2468 uint64_t reserved_12_63:52;
2469 uint64_t speed:4;
2470 uint64_t reserved_7_7:1;
2471 uint64_t mode:3;
2472 uint64_t reserved_2_3:2;
2473 uint64_t en:1;
2474 uint64_t type:1;
2475 #else
2476 uint64_t type:1;
2477 uint64_t en:1;
2478 uint64_t reserved_2_3:2;
2479 uint64_t mode:3;
2480 uint64_t reserved_7_7:1;
2481 uint64_t speed:4;
2482 uint64_t reserved_12_63:52;
2483 #endif
2484 } cn68xx;
2485 struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;
2486 struct cvmx_gmxx_inf_mode_cn61xx cnf71xx;
2487 };
2488
2489 union cvmx_gmxx_nxa_adr {
2490 uint64_t u64;
2491 struct cvmx_gmxx_nxa_adr_s {
2492 #ifdef __BIG_ENDIAN_BITFIELD
2493 uint64_t reserved_23_63:41;
2494 uint64_t pipe:7;
2495 uint64_t reserved_6_15:10;
2496 uint64_t prt:6;
2497 #else
2498 uint64_t prt:6;
2499 uint64_t reserved_6_15:10;
2500 uint64_t pipe:7;
2501 uint64_t reserved_23_63:41;
2502 #endif
2503 } s;
2504 struct cvmx_gmxx_nxa_adr_cn30xx {
2505 #ifdef __BIG_ENDIAN_BITFIELD
2506 uint64_t reserved_6_63:58;
2507 uint64_t prt:6;
2508 #else
2509 uint64_t prt:6;
2510 uint64_t reserved_6_63:58;
2511 #endif
2512 } cn30xx;
2513 struct cvmx_gmxx_nxa_adr_cn30xx cn31xx;
2514 struct cvmx_gmxx_nxa_adr_cn30xx cn38xx;
2515 struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;
2516 struct cvmx_gmxx_nxa_adr_cn30xx cn50xx;
2517 struct cvmx_gmxx_nxa_adr_cn30xx cn52xx;
2518 struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;
2519 struct cvmx_gmxx_nxa_adr_cn30xx cn56xx;
2520 struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;
2521 struct cvmx_gmxx_nxa_adr_cn30xx cn58xx;
2522 struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;
2523 struct cvmx_gmxx_nxa_adr_cn30xx cn61xx;
2524 struct cvmx_gmxx_nxa_adr_cn30xx cn63xx;
2525 struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;
2526 struct cvmx_gmxx_nxa_adr_cn30xx cn66xx;
2527 struct cvmx_gmxx_nxa_adr_s cn68xx;
2528 struct cvmx_gmxx_nxa_adr_s cn68xxp1;
2529 struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;
2530 };
2531
2532 union cvmx_gmxx_pipe_status {
2533 uint64_t u64;
2534 struct cvmx_gmxx_pipe_status_s {
2535 #ifdef __BIG_ENDIAN_BITFIELD
2536 uint64_t reserved_20_63:44;
2537 uint64_t ovr:4;
2538 uint64_t reserved_12_15:4;
2539 uint64_t bp:4;
2540 uint64_t reserved_4_7:4;
2541 uint64_t stop:4;
2542 #else
2543 uint64_t stop:4;
2544 uint64_t reserved_4_7:4;
2545 uint64_t bp:4;
2546 uint64_t reserved_12_15:4;
2547 uint64_t ovr:4;
2548 uint64_t reserved_20_63:44;
2549 #endif
2550 } s;
2551 struct cvmx_gmxx_pipe_status_s cn68xx;
2552 struct cvmx_gmxx_pipe_status_s cn68xxp1;
2553 };
2554
2555 union cvmx_gmxx_prtx_cbfc_ctl {
2556 uint64_t u64;
2557 struct cvmx_gmxx_prtx_cbfc_ctl_s {
2558 #ifdef __BIG_ENDIAN_BITFIELD
2559 uint64_t phys_en:16;
2560 uint64_t logl_en:16;
2561 uint64_t phys_bp:16;
2562 uint64_t reserved_4_15:12;
2563 uint64_t bck_en:1;
2564 uint64_t drp_en:1;
2565 uint64_t tx_en:1;
2566 uint64_t rx_en:1;
2567 #else
2568 uint64_t rx_en:1;
2569 uint64_t tx_en:1;
2570 uint64_t drp_en:1;
2571 uint64_t bck_en:1;
2572 uint64_t reserved_4_15:12;
2573 uint64_t phys_bp:16;
2574 uint64_t logl_en:16;
2575 uint64_t phys_en:16;
2576 #endif
2577 } s;
2578 struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
2579 struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
2580 struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;
2581 struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;
2582 struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;
2583 struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;
2584 struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;
2585 struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;
2586 struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;
2587 };
2588
2589 union cvmx_gmxx_prtx_cfg {
2590 uint64_t u64;
2591 struct cvmx_gmxx_prtx_cfg_s {
2592 #ifdef __BIG_ENDIAN_BITFIELD
2593 uint64_t reserved_22_63:42;
2594 uint64_t pknd:6;
2595 uint64_t reserved_14_15:2;
2596 uint64_t tx_idle:1;
2597 uint64_t rx_idle:1;
2598 uint64_t reserved_9_11:3;
2599 uint64_t speed_msb:1;
2600 uint64_t reserved_4_7:4;
2601 uint64_t slottime:1;
2602 uint64_t duplex:1;
2603 uint64_t speed:1;
2604 uint64_t en:1;
2605 #else
2606 uint64_t en:1;
2607 uint64_t speed:1;
2608 uint64_t duplex:1;
2609 uint64_t slottime:1;
2610 uint64_t reserved_4_7:4;
2611 uint64_t speed_msb:1;
2612 uint64_t reserved_9_11:3;
2613 uint64_t rx_idle:1;
2614 uint64_t tx_idle:1;
2615 uint64_t reserved_14_15:2;
2616 uint64_t pknd:6;
2617 uint64_t reserved_22_63:42;
2618 #endif
2619 } s;
2620 struct cvmx_gmxx_prtx_cfg_cn30xx {
2621 #ifdef __BIG_ENDIAN_BITFIELD
2622 uint64_t reserved_4_63:60;
2623 uint64_t slottime:1;
2624 uint64_t duplex:1;
2625 uint64_t speed:1;
2626 uint64_t en:1;
2627 #else
2628 uint64_t en:1;
2629 uint64_t speed:1;
2630 uint64_t duplex:1;
2631 uint64_t slottime:1;
2632 uint64_t reserved_4_63:60;
2633 #endif
2634 } cn30xx;
2635 struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
2636 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
2637 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
2638 struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
2639 struct cvmx_gmxx_prtx_cfg_cn52xx {
2640 #ifdef __BIG_ENDIAN_BITFIELD
2641 uint64_t reserved_14_63:50;
2642 uint64_t tx_idle:1;
2643 uint64_t rx_idle:1;
2644 uint64_t reserved_9_11:3;
2645 uint64_t speed_msb:1;
2646 uint64_t reserved_4_7:4;
2647 uint64_t slottime:1;
2648 uint64_t duplex:1;
2649 uint64_t speed:1;
2650 uint64_t en:1;
2651 #else
2652 uint64_t en:1;
2653 uint64_t speed:1;
2654 uint64_t duplex:1;
2655 uint64_t slottime:1;
2656 uint64_t reserved_4_7:4;
2657 uint64_t speed_msb:1;
2658 uint64_t reserved_9_11:3;
2659 uint64_t rx_idle:1;
2660 uint64_t tx_idle:1;
2661 uint64_t reserved_14_63:50;
2662 #endif
2663 } cn52xx;
2664 struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;
2665 struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;
2666 struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;
2667 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
2668 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
2669 struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;
2670 struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;
2671 struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;
2672 struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;
2673 struct cvmx_gmxx_prtx_cfg_s cn68xx;
2674 struct cvmx_gmxx_prtx_cfg_s cn68xxp1;
2675 struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;
2676 };
2677
2678 union cvmx_gmxx_rxx_adr_cam0 {
2679 uint64_t u64;
2680 struct cvmx_gmxx_rxx_adr_cam0_s {
2681 #ifdef __BIG_ENDIAN_BITFIELD
2682 uint64_t adr:64;
2683 #else
2684 uint64_t adr:64;
2685 #endif
2686 } s;
2687 struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
2688 struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
2689 struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
2690 struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
2691 struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
2692 struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
2693 struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
2694 struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
2695 struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
2696 struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
2697 struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
2698 struct cvmx_gmxx_rxx_adr_cam0_s cn61xx;
2699 struct cvmx_gmxx_rxx_adr_cam0_s cn63xx;
2700 struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;
2701 struct cvmx_gmxx_rxx_adr_cam0_s cn66xx;
2702 struct cvmx_gmxx_rxx_adr_cam0_s cn68xx;
2703 struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;
2704 struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;
2705 };
2706
2707 union cvmx_gmxx_rxx_adr_cam1 {
2708 uint64_t u64;
2709 struct cvmx_gmxx_rxx_adr_cam1_s {
2710 #ifdef __BIG_ENDIAN_BITFIELD
2711 uint64_t adr:64;
2712 #else
2713 uint64_t adr:64;
2714 #endif
2715 } s;
2716 struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
2717 struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
2718 struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
2719 struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
2720 struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
2721 struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
2722 struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
2723 struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
2724 struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
2725 struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
2726 struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
2727 struct cvmx_gmxx_rxx_adr_cam1_s cn61xx;
2728 struct cvmx_gmxx_rxx_adr_cam1_s cn63xx;
2729 struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;
2730 struct cvmx_gmxx_rxx_adr_cam1_s cn66xx;
2731 struct cvmx_gmxx_rxx_adr_cam1_s cn68xx;
2732 struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;
2733 struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;
2734 };
2735
2736 union cvmx_gmxx_rxx_adr_cam2 {
2737 uint64_t u64;
2738 struct cvmx_gmxx_rxx_adr_cam2_s {
2739 #ifdef __BIG_ENDIAN_BITFIELD
2740 uint64_t adr:64;
2741 #else
2742 uint64_t adr:64;
2743 #endif
2744 } s;
2745 struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
2746 struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
2747 struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
2748 struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
2749 struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
2750 struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
2751 struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
2752 struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
2753 struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
2754 struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
2755 struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
2756 struct cvmx_gmxx_rxx_adr_cam2_s cn61xx;
2757 struct cvmx_gmxx_rxx_adr_cam2_s cn63xx;
2758 struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;
2759 struct cvmx_gmxx_rxx_adr_cam2_s cn66xx;
2760 struct cvmx_gmxx_rxx_adr_cam2_s cn68xx;
2761 struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;
2762 struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;
2763 };
2764
2765 union cvmx_gmxx_rxx_adr_cam3 {
2766 uint64_t u64;
2767 struct cvmx_gmxx_rxx_adr_cam3_s {
2768 #ifdef __BIG_ENDIAN_BITFIELD
2769 uint64_t adr:64;
2770 #else
2771 uint64_t adr:64;
2772 #endif
2773 } s;
2774 struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
2775 struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
2776 struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
2777 struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
2778 struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
2779 struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
2780 struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
2781 struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
2782 struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
2783 struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
2784 struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
2785 struct cvmx_gmxx_rxx_adr_cam3_s cn61xx;
2786 struct cvmx_gmxx_rxx_adr_cam3_s cn63xx;
2787 struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;
2788 struct cvmx_gmxx_rxx_adr_cam3_s cn66xx;
2789 struct cvmx_gmxx_rxx_adr_cam3_s cn68xx;
2790 struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;
2791 struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;
2792 };
2793
2794 union cvmx_gmxx_rxx_adr_cam4 {
2795 uint64_t u64;
2796 struct cvmx_gmxx_rxx_adr_cam4_s {
2797 #ifdef __BIG_ENDIAN_BITFIELD
2798 uint64_t adr:64;
2799 #else
2800 uint64_t adr:64;
2801 #endif
2802 } s;
2803 struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
2804 struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
2805 struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
2806 struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
2807 struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
2808 struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
2809 struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
2810 struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
2811 struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
2812 struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
2813 struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
2814 struct cvmx_gmxx_rxx_adr_cam4_s cn61xx;
2815 struct cvmx_gmxx_rxx_adr_cam4_s cn63xx;
2816 struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;
2817 struct cvmx_gmxx_rxx_adr_cam4_s cn66xx;
2818 struct cvmx_gmxx_rxx_adr_cam4_s cn68xx;
2819 struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;
2820 struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;
2821 };
2822
2823 union cvmx_gmxx_rxx_adr_cam5 {
2824 uint64_t u64;
2825 struct cvmx_gmxx_rxx_adr_cam5_s {
2826 #ifdef __BIG_ENDIAN_BITFIELD
2827 uint64_t adr:64;
2828 #else
2829 uint64_t adr:64;
2830 #endif
2831 } s;
2832 struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
2833 struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
2834 struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
2835 struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
2836 struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
2837 struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
2838 struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
2839 struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
2840 struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
2841 struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
2842 struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
2843 struct cvmx_gmxx_rxx_adr_cam5_s cn61xx;
2844 struct cvmx_gmxx_rxx_adr_cam5_s cn63xx;
2845 struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;
2846 struct cvmx_gmxx_rxx_adr_cam5_s cn66xx;
2847 struct cvmx_gmxx_rxx_adr_cam5_s cn68xx;
2848 struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;
2849 struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;
2850 };
2851
2852 union cvmx_gmxx_rxx_adr_cam_all_en {
2853 uint64_t u64;
2854 struct cvmx_gmxx_rxx_adr_cam_all_en_s {
2855 #ifdef __BIG_ENDIAN_BITFIELD
2856 uint64_t reserved_32_63:32;
2857 uint64_t en:32;
2858 #else
2859 uint64_t en:32;
2860 uint64_t reserved_32_63:32;
2861 #endif
2862 } s;
2863 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
2864 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
2865 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
2866 struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
2867 };
2868
2869 union cvmx_gmxx_rxx_adr_cam_en {
2870 uint64_t u64;
2871 struct cvmx_gmxx_rxx_adr_cam_en_s {
2872 #ifdef __BIG_ENDIAN_BITFIELD
2873 uint64_t reserved_8_63:56;
2874 uint64_t en:8;
2875 #else
2876 uint64_t en:8;
2877 uint64_t reserved_8_63:56;
2878 #endif
2879 } s;
2880 struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
2881 struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
2882 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
2883 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
2884 struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
2885 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
2886 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
2887 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
2888 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
2889 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
2890 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
2891 struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;
2892 struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;
2893 struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;
2894 struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;
2895 struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;
2896 struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;
2897 struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;
2898 };
2899
2900 union cvmx_gmxx_rxx_adr_ctl {
2901 uint64_t u64;
2902 struct cvmx_gmxx_rxx_adr_ctl_s {
2903 #ifdef __BIG_ENDIAN_BITFIELD
2904 uint64_t reserved_4_63:60;
2905 uint64_t cam_mode:1;
2906 uint64_t mcst:2;
2907 uint64_t bcst:1;
2908 #else
2909 uint64_t bcst:1;
2910 uint64_t mcst:2;
2911 uint64_t cam_mode:1;
2912 uint64_t reserved_4_63:60;
2913 #endif
2914 } s;
2915 struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
2916 struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
2917 struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
2918 struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
2919 struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
2920 struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
2921 struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
2922 struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
2923 struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
2924 struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
2925 struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
2926 struct cvmx_gmxx_rxx_adr_ctl_s cn61xx;
2927 struct cvmx_gmxx_rxx_adr_ctl_s cn63xx;
2928 struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;
2929 struct cvmx_gmxx_rxx_adr_ctl_s cn66xx;
2930 struct cvmx_gmxx_rxx_adr_ctl_s cn68xx;
2931 struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;
2932 struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;
2933 };
2934
2935 union cvmx_gmxx_rxx_decision {
2936 uint64_t u64;
2937 struct cvmx_gmxx_rxx_decision_s {
2938 #ifdef __BIG_ENDIAN_BITFIELD
2939 uint64_t reserved_5_63:59;
2940 uint64_t cnt:5;
2941 #else
2942 uint64_t cnt:5;
2943 uint64_t reserved_5_63:59;
2944 #endif
2945 } s;
2946 struct cvmx_gmxx_rxx_decision_s cn30xx;
2947 struct cvmx_gmxx_rxx_decision_s cn31xx;
2948 struct cvmx_gmxx_rxx_decision_s cn38xx;
2949 struct cvmx_gmxx_rxx_decision_s cn38xxp2;
2950 struct cvmx_gmxx_rxx_decision_s cn50xx;
2951 struct cvmx_gmxx_rxx_decision_s cn52xx;
2952 struct cvmx_gmxx_rxx_decision_s cn52xxp1;
2953 struct cvmx_gmxx_rxx_decision_s cn56xx;
2954 struct cvmx_gmxx_rxx_decision_s cn56xxp1;
2955 struct cvmx_gmxx_rxx_decision_s cn58xx;
2956 struct cvmx_gmxx_rxx_decision_s cn58xxp1;
2957 struct cvmx_gmxx_rxx_decision_s cn61xx;
2958 struct cvmx_gmxx_rxx_decision_s cn63xx;
2959 struct cvmx_gmxx_rxx_decision_s cn63xxp1;
2960 struct cvmx_gmxx_rxx_decision_s cn66xx;
2961 struct cvmx_gmxx_rxx_decision_s cn68xx;
2962 struct cvmx_gmxx_rxx_decision_s cn68xxp1;
2963 struct cvmx_gmxx_rxx_decision_s cnf71xx;
2964 };
2965
2966 union cvmx_gmxx_rxx_frm_chk {
2967 uint64_t u64;
2968 struct cvmx_gmxx_rxx_frm_chk_s {
2969 #ifdef __BIG_ENDIAN_BITFIELD
2970 uint64_t reserved_10_63:54;
2971 uint64_t niberr:1;
2972 uint64_t skperr:1;
2973 uint64_t rcverr:1;
2974 uint64_t lenerr:1;
2975 uint64_t alnerr:1;
2976 uint64_t fcserr:1;
2977 uint64_t jabber:1;
2978 uint64_t maxerr:1;
2979 uint64_t carext:1;
2980 uint64_t minerr:1;
2981 #else
2982 uint64_t minerr:1;
2983 uint64_t carext:1;
2984 uint64_t maxerr:1;
2985 uint64_t jabber:1;
2986 uint64_t fcserr:1;
2987 uint64_t alnerr:1;
2988 uint64_t lenerr:1;
2989 uint64_t rcverr:1;
2990 uint64_t skperr:1;
2991 uint64_t niberr:1;
2992 uint64_t reserved_10_63:54;
2993 #endif
2994 } s;
2995 struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
2996 struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
2997 struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
2998 struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
2999 struct cvmx_gmxx_rxx_frm_chk_cn50xx {
3000 #ifdef __BIG_ENDIAN_BITFIELD
3001 uint64_t reserved_10_63:54;
3002 uint64_t niberr:1;
3003 uint64_t skperr:1;
3004 uint64_t rcverr:1;
3005 uint64_t reserved_6_6:1;
3006 uint64_t alnerr:1;
3007 uint64_t fcserr:1;
3008 uint64_t jabber:1;
3009 uint64_t reserved_2_2:1;
3010 uint64_t carext:1;
3011 uint64_t reserved_0_0:1;
3012 #else
3013 uint64_t reserved_0_0:1;
3014 uint64_t carext:1;
3015 uint64_t reserved_2_2:1;
3016 uint64_t jabber:1;
3017 uint64_t fcserr:1;
3018 uint64_t alnerr:1;
3019 uint64_t reserved_6_6:1;
3020 uint64_t rcverr:1;
3021 uint64_t skperr:1;
3022 uint64_t niberr:1;
3023 uint64_t reserved_10_63:54;
3024 #endif
3025 } cn50xx;
3026 struct cvmx_gmxx_rxx_frm_chk_cn52xx {
3027 #ifdef __BIG_ENDIAN_BITFIELD
3028 uint64_t reserved_9_63:55;
3029 uint64_t skperr:1;
3030 uint64_t rcverr:1;
3031 uint64_t reserved_5_6:2;
3032 uint64_t fcserr:1;
3033 uint64_t jabber:1;
3034 uint64_t reserved_2_2:1;
3035 uint64_t carext:1;
3036 uint64_t reserved_0_0:1;
3037 #else
3038 uint64_t reserved_0_0:1;
3039 uint64_t carext:1;
3040 uint64_t reserved_2_2:1;
3041 uint64_t jabber:1;
3042 uint64_t fcserr:1;
3043 uint64_t reserved_5_6:2;
3044 uint64_t rcverr:1;
3045 uint64_t skperr:1;
3046 uint64_t reserved_9_63:55;
3047 #endif
3048 } cn52xx;
3049 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
3050 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
3051 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
3052 struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
3053 struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
3054 struct cvmx_gmxx_rxx_frm_chk_cn61xx {
3055 #ifdef __BIG_ENDIAN_BITFIELD
3056 uint64_t reserved_9_63:55;
3057 uint64_t skperr:1;
3058 uint64_t rcverr:1;
3059 uint64_t reserved_5_6:2;
3060 uint64_t fcserr:1;
3061 uint64_t jabber:1;
3062 uint64_t reserved_2_2:1;
3063 uint64_t carext:1;
3064 uint64_t minerr:1;
3065 #else
3066 uint64_t minerr:1;
3067 uint64_t carext:1;
3068 uint64_t reserved_2_2:1;
3069 uint64_t jabber:1;
3070 uint64_t fcserr:1;
3071 uint64_t reserved_5_6:2;
3072 uint64_t rcverr:1;
3073 uint64_t skperr:1;
3074 uint64_t reserved_9_63:55;
3075 #endif
3076 } cn61xx;
3077 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;
3078 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;
3079 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;
3080 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;
3081 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;
3082 struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;
3083 };
3084
3085 union cvmx_gmxx_rxx_frm_ctl {
3086 uint64_t u64;
3087 struct cvmx_gmxx_rxx_frm_ctl_s {
3088 #ifdef __BIG_ENDIAN_BITFIELD
3089 uint64_t reserved_13_63:51;
3090 uint64_t ptp_mode:1;
3091 uint64_t reserved_11_11:1;
3092 uint64_t null_dis:1;
3093 uint64_t pre_align:1;
3094 uint64_t pad_len:1;
3095 uint64_t vlan_len:1;
3096 uint64_t pre_free:1;
3097 uint64_t ctl_smac:1;
3098 uint64_t ctl_mcst:1;
3099 uint64_t ctl_bck:1;
3100 uint64_t ctl_drp:1;
3101 uint64_t pre_strp:1;
3102 uint64_t pre_chk:1;
3103 #else
3104 uint64_t pre_chk:1;
3105 uint64_t pre_strp:1;
3106 uint64_t ctl_drp:1;
3107 uint64_t ctl_bck:1;
3108 uint64_t ctl_mcst:1;
3109 uint64_t ctl_smac:1;
3110 uint64_t pre_free:1;
3111 uint64_t vlan_len:1;
3112 uint64_t pad_len:1;
3113 uint64_t pre_align:1;
3114 uint64_t null_dis:1;
3115 uint64_t reserved_11_11:1;
3116 uint64_t ptp_mode:1;
3117 uint64_t reserved_13_63:51;
3118 #endif
3119 } s;
3120 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
3121 #ifdef __BIG_ENDIAN_BITFIELD
3122 uint64_t reserved_9_63:55;
3123 uint64_t pad_len:1;
3124 uint64_t vlan_len:1;
3125 uint64_t pre_free:1;
3126 uint64_t ctl_smac:1;
3127 uint64_t ctl_mcst:1;
3128 uint64_t ctl_bck:1;
3129 uint64_t ctl_drp:1;
3130 uint64_t pre_strp:1;
3131 uint64_t pre_chk:1;
3132 #else
3133 uint64_t pre_chk:1;
3134 uint64_t pre_strp:1;
3135 uint64_t ctl_drp:1;
3136 uint64_t ctl_bck:1;
3137 uint64_t ctl_mcst:1;
3138 uint64_t ctl_smac:1;
3139 uint64_t pre_free:1;
3140 uint64_t vlan_len:1;
3141 uint64_t pad_len:1;
3142 uint64_t reserved_9_63:55;
3143 #endif
3144 } cn30xx;
3145 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
3146 #ifdef __BIG_ENDIAN_BITFIELD
3147 uint64_t reserved_8_63:56;
3148 uint64_t vlan_len:1;
3149 uint64_t pre_free:1;
3150 uint64_t ctl_smac:1;
3151 uint64_t ctl_mcst:1;
3152 uint64_t ctl_bck:1;
3153 uint64_t ctl_drp:1;
3154 uint64_t pre_strp:1;
3155 uint64_t pre_chk:1;
3156 #else
3157 uint64_t pre_chk:1;
3158 uint64_t pre_strp:1;
3159 uint64_t ctl_drp:1;
3160 uint64_t ctl_bck:1;
3161 uint64_t ctl_mcst:1;
3162 uint64_t ctl_smac:1;
3163 uint64_t pre_free:1;
3164 uint64_t vlan_len:1;
3165 uint64_t reserved_8_63:56;
3166 #endif
3167 } cn31xx;
3168 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
3169 struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
3170 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
3171 #ifdef __BIG_ENDIAN_BITFIELD
3172 uint64_t reserved_11_63:53;
3173 uint64_t null_dis:1;
3174 uint64_t pre_align:1;
3175 uint64_t reserved_7_8:2;
3176 uint64_t pre_free:1;
3177 uint64_t ctl_smac:1;
3178 uint64_t ctl_mcst:1;
3179 uint64_t ctl_bck:1;
3180 uint64_t ctl_drp:1;
3181 uint64_t pre_strp:1;
3182 uint64_t pre_chk:1;
3183 #else
3184 uint64_t pre_chk:1;
3185 uint64_t pre_strp:1;
3186 uint64_t ctl_drp:1;
3187 uint64_t ctl_bck:1;
3188 uint64_t ctl_mcst:1;
3189 uint64_t ctl_smac:1;
3190 uint64_t pre_free:1;
3191 uint64_t reserved_7_8:2;
3192 uint64_t pre_align:1;
3193 uint64_t null_dis:1;
3194 uint64_t reserved_11_63:53;
3195 #endif
3196 } cn50xx;
3197 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
3198 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
3199 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
3200 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
3201 #ifdef __BIG_ENDIAN_BITFIELD
3202 uint64_t reserved_10_63:54;
3203 uint64_t pre_align:1;
3204 uint64_t reserved_7_8:2;
3205 uint64_t pre_free:1;
3206 uint64_t ctl_smac:1;
3207 uint64_t ctl_mcst:1;
3208 uint64_t ctl_bck:1;
3209 uint64_t ctl_drp:1;
3210 uint64_t pre_strp:1;
3211 uint64_t pre_chk:1;
3212 #else
3213 uint64_t pre_chk:1;
3214 uint64_t pre_strp:1;
3215 uint64_t ctl_drp:1;
3216 uint64_t ctl_bck:1;
3217 uint64_t ctl_mcst:1;
3218 uint64_t ctl_smac:1;
3219 uint64_t pre_free:1;
3220 uint64_t reserved_7_8:2;
3221 uint64_t pre_align:1;
3222 uint64_t reserved_10_63:54;
3223 #endif
3224 } cn56xxp1;
3225 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
3226 #ifdef __BIG_ENDIAN_BITFIELD
3227 uint64_t reserved_11_63:53;
3228 uint64_t null_dis:1;
3229 uint64_t pre_align:1;
3230 uint64_t pad_len:1;
3231 uint64_t vlan_len:1;
3232 uint64_t pre_free:1;
3233 uint64_t ctl_smac:1;
3234 uint64_t ctl_mcst:1;
3235 uint64_t ctl_bck:1;
3236 uint64_t ctl_drp:1;
3237 uint64_t pre_strp:1;
3238 uint64_t pre_chk:1;
3239 #else
3240 uint64_t pre_chk:1;
3241 uint64_t pre_strp:1;
3242 uint64_t ctl_drp:1;
3243 uint64_t ctl_bck:1;
3244 uint64_t ctl_mcst:1;
3245 uint64_t ctl_smac:1;
3246 uint64_t pre_free:1;
3247 uint64_t vlan_len:1;
3248 uint64_t pad_len:1;
3249 uint64_t pre_align:1;
3250 uint64_t null_dis:1;
3251 uint64_t reserved_11_63:53;
3252 #endif
3253 } cn58xx;
3254 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
3255 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
3256 #ifdef __BIG_ENDIAN_BITFIELD
3257 uint64_t reserved_13_63:51;
3258 uint64_t ptp_mode:1;
3259 uint64_t reserved_11_11:1;
3260 uint64_t null_dis:1;
3261 uint64_t pre_align:1;
3262 uint64_t reserved_7_8:2;
3263 uint64_t pre_free:1;
3264 uint64_t ctl_smac:1;
3265 uint64_t ctl_mcst:1;
3266 uint64_t ctl_bck:1;
3267 uint64_t ctl_drp:1;
3268 uint64_t pre_strp:1;
3269 uint64_t pre_chk:1;
3270 #else
3271 uint64_t pre_chk:1;
3272 uint64_t pre_strp:1;
3273 uint64_t ctl_drp:1;
3274 uint64_t ctl_bck:1;
3275 uint64_t ctl_mcst:1;
3276 uint64_t ctl_smac:1;
3277 uint64_t pre_free:1;
3278 uint64_t reserved_7_8:2;
3279 uint64_t pre_align:1;
3280 uint64_t null_dis:1;
3281 uint64_t reserved_11_11:1;
3282 uint64_t ptp_mode:1;
3283 uint64_t reserved_13_63:51;
3284 #endif
3285 } cn61xx;
3286 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;
3287 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;
3288 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;
3289 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;
3290 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;
3291 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;
3292 };
3293
3294 union cvmx_gmxx_rxx_frm_max {
3295 uint64_t u64;
3296 struct cvmx_gmxx_rxx_frm_max_s {
3297 #ifdef __BIG_ENDIAN_BITFIELD
3298 uint64_t reserved_16_63:48;
3299 uint64_t len:16;
3300 #else
3301 uint64_t len:16;
3302 uint64_t reserved_16_63:48;
3303 #endif
3304 } s;
3305 struct cvmx_gmxx_rxx_frm_max_s cn30xx;
3306 struct cvmx_gmxx_rxx_frm_max_s cn31xx;
3307 struct cvmx_gmxx_rxx_frm_max_s cn38xx;
3308 struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
3309 struct cvmx_gmxx_rxx_frm_max_s cn58xx;
3310 struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
3311 };
3312
3313 union cvmx_gmxx_rxx_frm_min {
3314 uint64_t u64;
3315 struct cvmx_gmxx_rxx_frm_min_s {
3316 #ifdef __BIG_ENDIAN_BITFIELD
3317 uint64_t reserved_16_63:48;
3318 uint64_t len:16;
3319 #else
3320 uint64_t len:16;
3321 uint64_t reserved_16_63:48;
3322 #endif
3323 } s;
3324 struct cvmx_gmxx_rxx_frm_min_s cn30xx;
3325 struct cvmx_gmxx_rxx_frm_min_s cn31xx;
3326 struct cvmx_gmxx_rxx_frm_min_s cn38xx;
3327 struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
3328 struct cvmx_gmxx_rxx_frm_min_s cn58xx;
3329 struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
3330 };
3331
3332 union cvmx_gmxx_rxx_ifg {
3333 uint64_t u64;
3334 struct cvmx_gmxx_rxx_ifg_s {
3335 #ifdef __BIG_ENDIAN_BITFIELD
3336 uint64_t reserved_4_63:60;
3337 uint64_t ifg:4;
3338 #else
3339 uint64_t ifg:4;
3340 uint64_t reserved_4_63:60;
3341 #endif
3342 } s;
3343 struct cvmx_gmxx_rxx_ifg_s cn30xx;
3344 struct cvmx_gmxx_rxx_ifg_s cn31xx;
3345 struct cvmx_gmxx_rxx_ifg_s cn38xx;
3346 struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
3347 struct cvmx_gmxx_rxx_ifg_s cn50xx;
3348 struct cvmx_gmxx_rxx_ifg_s cn52xx;
3349 struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
3350 struct cvmx_gmxx_rxx_ifg_s cn56xx;
3351 struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
3352 struct cvmx_gmxx_rxx_ifg_s cn58xx;
3353 struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
3354 struct cvmx_gmxx_rxx_ifg_s cn61xx;
3355 struct cvmx_gmxx_rxx_ifg_s cn63xx;
3356 struct cvmx_gmxx_rxx_ifg_s cn63xxp1;
3357 struct cvmx_gmxx_rxx_ifg_s cn66xx;
3358 struct cvmx_gmxx_rxx_ifg_s cn68xx;
3359 struct cvmx_gmxx_rxx_ifg_s cn68xxp1;
3360 struct cvmx_gmxx_rxx_ifg_s cnf71xx;
3361 };
3362
3363 union cvmx_gmxx_rxx_int_en {
3364 uint64_t u64;
3365 struct cvmx_gmxx_rxx_int_en_s {
3366 #ifdef __BIG_ENDIAN_BITFIELD
3367 uint64_t reserved_29_63:35;
3368 uint64_t hg2cc:1;
3369 uint64_t hg2fld:1;
3370 uint64_t undat:1;
3371 uint64_t uneop:1;
3372 uint64_t unsop:1;
3373 uint64_t bad_term:1;
3374 uint64_t bad_seq:1;
3375 uint64_t rem_fault:1;
3376 uint64_t loc_fault:1;
3377 uint64_t pause_drp:1;
3378 uint64_t phy_dupx:1;
3379 uint64_t phy_spd:1;
3380 uint64_t phy_link:1;
3381 uint64_t ifgerr:1;
3382 uint64_t coldet:1;
3383 uint64_t falerr:1;
3384 uint64_t rsverr:1;
3385 uint64_t pcterr:1;
3386 uint64_t ovrerr:1;
3387 uint64_t niberr:1;
3388 uint64_t skperr:1;
3389 uint64_t rcverr:1;
3390 uint64_t lenerr:1;
3391 uint64_t alnerr:1;
3392 uint64_t fcserr:1;
3393 uint64_t jabber:1;
3394 uint64_t maxerr:1;
3395 uint64_t carext:1;
3396 uint64_t minerr:1;
3397 #else
3398 uint64_t minerr:1;
3399 uint64_t carext:1;
3400 uint64_t maxerr:1;
3401 uint64_t jabber:1;
3402 uint64_t fcserr:1;
3403 uint64_t alnerr:1;
3404 uint64_t lenerr:1;
3405 uint64_t rcverr:1;
3406 uint64_t skperr:1;
3407 uint64_t niberr:1;
3408 uint64_t ovrerr:1;
3409 uint64_t pcterr:1;
3410 uint64_t rsverr:1;
3411 uint64_t falerr:1;
3412 uint64_t coldet:1;
3413 uint64_t ifgerr:1;
3414 uint64_t phy_link:1;
3415 uint64_t phy_spd:1;
3416 uint64_t phy_dupx:1;
3417 uint64_t pause_drp:1;
3418 uint64_t loc_fault:1;
3419 uint64_t rem_fault:1;
3420 uint64_t bad_seq:1;
3421 uint64_t bad_term:1;
3422 uint64_t unsop:1;
3423 uint64_t uneop:1;
3424 uint64_t undat:1;
3425 uint64_t hg2fld:1;
3426 uint64_t hg2cc:1;
3427 uint64_t reserved_29_63:35;
3428 #endif
3429 } s;
3430 struct cvmx_gmxx_rxx_int_en_cn30xx {
3431 #ifdef __BIG_ENDIAN_BITFIELD
3432 uint64_t reserved_19_63:45;
3433 uint64_t phy_dupx:1;
3434 uint64_t phy_spd:1;
3435 uint64_t phy_link:1;
3436 uint64_t ifgerr:1;
3437 uint64_t coldet:1;
3438 uint64_t falerr:1;
3439 uint64_t rsverr:1;
3440 uint64_t pcterr:1;
3441 uint64_t ovrerr:1;
3442 uint64_t niberr:1;
3443 uint64_t skperr:1;
3444 uint64_t rcverr:1;
3445 uint64_t lenerr:1;
3446 uint64_t alnerr:1;
3447 uint64_t fcserr:1;
3448 uint64_t jabber:1;
3449 uint64_t maxerr:1;
3450 uint64_t carext:1;
3451 uint64_t minerr:1;
3452 #else
3453 uint64_t minerr:1;
3454 uint64_t carext:1;
3455 uint64_t maxerr:1;
3456 uint64_t jabber:1;
3457 uint64_t fcserr:1;
3458 uint64_t alnerr:1;
3459 uint64_t lenerr:1;
3460 uint64_t rcverr:1;
3461 uint64_t skperr:1;
3462 uint64_t niberr:1;
3463 uint64_t ovrerr:1;
3464 uint64_t pcterr:1;
3465 uint64_t rsverr:1;
3466 uint64_t falerr:1;
3467 uint64_t coldet:1;
3468 uint64_t ifgerr:1;
3469 uint64_t phy_link:1;
3470 uint64_t phy_spd:1;
3471 uint64_t phy_dupx:1;
3472 uint64_t reserved_19_63:45;
3473 #endif
3474 } cn30xx;
3475 struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
3476 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
3477 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
3478 struct cvmx_gmxx_rxx_int_en_cn50xx {
3479 #ifdef __BIG_ENDIAN_BITFIELD
3480 uint64_t reserved_20_63:44;
3481 uint64_t pause_drp:1;
3482 uint64_t phy_dupx:1;
3483 uint64_t phy_spd:1;
3484 uint64_t phy_link:1;
3485 uint64_t ifgerr:1;
3486 uint64_t coldet:1;
3487 uint64_t falerr:1;
3488 uint64_t rsverr:1;
3489 uint64_t pcterr:1;
3490 uint64_t ovrerr:1;
3491 uint64_t niberr:1;
3492 uint64_t skperr:1;
3493 uint64_t rcverr:1;
3494 uint64_t reserved_6_6:1;
3495 uint64_t alnerr:1;
3496 uint64_t fcserr:1;
3497 uint64_t jabber:1;
3498 uint64_t reserved_2_2:1;
3499 uint64_t carext:1;
3500 uint64_t reserved_0_0:1;
3501 #else
3502 uint64_t reserved_0_0:1;
3503 uint64_t carext:1;
3504 uint64_t reserved_2_2:1;
3505 uint64_t jabber:1;
3506 uint64_t fcserr:1;
3507 uint64_t alnerr:1;
3508 uint64_t reserved_6_6:1;
3509 uint64_t rcverr:1;
3510 uint64_t skperr:1;
3511 uint64_t niberr:1;
3512 uint64_t ovrerr:1;
3513 uint64_t pcterr:1;
3514 uint64_t rsverr:1;
3515 uint64_t falerr:1;
3516 uint64_t coldet:1;
3517 uint64_t ifgerr:1;
3518 uint64_t phy_link:1;
3519 uint64_t phy_spd:1;
3520 uint64_t phy_dupx:1;
3521 uint64_t pause_drp:1;
3522 uint64_t reserved_20_63:44;
3523 #endif
3524 } cn50xx;
3525 struct cvmx_gmxx_rxx_int_en_cn52xx {
3526 #ifdef __BIG_ENDIAN_BITFIELD
3527 uint64_t reserved_29_63:35;
3528 uint64_t hg2cc:1;
3529 uint64_t hg2fld:1;
3530 uint64_t undat:1;
3531 uint64_t uneop:1;
3532 uint64_t unsop:1;
3533 uint64_t bad_term:1;
3534 uint64_t bad_seq:1;
3535 uint64_t rem_fault:1;
3536 uint64_t loc_fault:1;
3537 uint64_t pause_drp:1;
3538 uint64_t reserved_16_18:3;
3539 uint64_t ifgerr:1;
3540 uint64_t coldet:1;
3541 uint64_t falerr:1;
3542 uint64_t rsverr:1;
3543 uint64_t pcterr:1;
3544 uint64_t ovrerr:1;
3545 uint64_t reserved_9_9:1;
3546 uint64_t skperr:1;
3547 uint64_t rcverr:1;
3548 uint64_t reserved_5_6:2;
3549 uint64_t fcserr:1;
3550 uint64_t jabber:1;
3551 uint64_t reserved_2_2:1;
3552 uint64_t carext:1;
3553 uint64_t reserved_0_0:1;
3554 #else
3555 uint64_t reserved_0_0:1;
3556 uint64_t carext:1;
3557 uint64_t reserved_2_2:1;
3558 uint64_t jabber:1;
3559 uint64_t fcserr:1;
3560 uint64_t reserved_5_6:2;
3561 uint64_t rcverr:1;
3562 uint64_t skperr:1;
3563 uint64_t reserved_9_9:1;
3564 uint64_t ovrerr:1;
3565 uint64_t pcterr:1;
3566 uint64_t rsverr:1;
3567 uint64_t falerr:1;
3568 uint64_t coldet:1;
3569 uint64_t ifgerr:1;
3570 uint64_t reserved_16_18:3;
3571 uint64_t pause_drp:1;
3572 uint64_t loc_fault:1;
3573 uint64_t rem_fault:1;
3574 uint64_t bad_seq:1;
3575 uint64_t bad_term:1;
3576 uint64_t unsop:1;
3577 uint64_t uneop:1;
3578 uint64_t undat:1;
3579 uint64_t hg2fld:1;
3580 uint64_t hg2cc:1;
3581 uint64_t reserved_29_63:35;
3582 #endif
3583 } cn52xx;
3584 struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
3585 struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
3586 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
3587 #ifdef __BIG_ENDIAN_BITFIELD
3588 uint64_t reserved_27_63:37;
3589 uint64_t undat:1;
3590 uint64_t uneop:1;
3591 uint64_t unsop:1;
3592 uint64_t bad_term:1;
3593 uint64_t bad_seq:1;
3594 uint64_t rem_fault:1;
3595 uint64_t loc_fault:1;
3596 uint64_t pause_drp:1;
3597 uint64_t reserved_16_18:3;
3598 uint64_t ifgerr:1;
3599 uint64_t coldet:1;
3600 uint64_t falerr:1;
3601 uint64_t rsverr:1;
3602 uint64_t pcterr:1;
3603 uint64_t ovrerr:1;
3604 uint64_t reserved_9_9:1;
3605 uint64_t skperr:1;
3606 uint64_t rcverr:1;
3607 uint64_t reserved_5_6:2;
3608 uint64_t fcserr:1;
3609 uint64_t jabber:1;
3610 uint64_t reserved_2_2:1;
3611 uint64_t carext:1;
3612 uint64_t reserved_0_0:1;
3613 #else
3614 uint64_t reserved_0_0:1;
3615 uint64_t carext:1;
3616 uint64_t reserved_2_2:1;
3617 uint64_t jabber:1;
3618 uint64_t fcserr:1;
3619 uint64_t reserved_5_6:2;
3620 uint64_t rcverr:1;
3621 uint64_t skperr:1;
3622 uint64_t reserved_9_9:1;
3623 uint64_t ovrerr:1;
3624 uint64_t pcterr:1;
3625 uint64_t rsverr:1;
3626 uint64_t falerr:1;
3627 uint64_t coldet:1;
3628 uint64_t ifgerr:1;
3629 uint64_t reserved_16_18:3;
3630 uint64_t pause_drp:1;
3631 uint64_t loc_fault:1;
3632 uint64_t rem_fault:1;
3633 uint64_t bad_seq:1;
3634 uint64_t bad_term:1;
3635 uint64_t unsop:1;
3636 uint64_t uneop:1;
3637 uint64_t undat:1;
3638 uint64_t reserved_27_63:37;
3639 #endif
3640 } cn56xxp1;
3641 struct cvmx_gmxx_rxx_int_en_cn58xx {
3642 #ifdef __BIG_ENDIAN_BITFIELD
3643 uint64_t reserved_20_63:44;
3644 uint64_t pause_drp:1;
3645 uint64_t phy_dupx:1;
3646 uint64_t phy_spd:1;
3647 uint64_t phy_link:1;
3648 uint64_t ifgerr:1;
3649 uint64_t coldet:1;
3650 uint64_t falerr:1;
3651 uint64_t rsverr:1;
3652 uint64_t pcterr:1;
3653 uint64_t ovrerr:1;
3654 uint64_t niberr:1;
3655 uint64_t skperr:1;
3656 uint64_t rcverr:1;
3657 uint64_t lenerr:1;
3658 uint64_t alnerr:1;
3659 uint64_t fcserr:1;
3660 uint64_t jabber:1;
3661 uint64_t maxerr:1;
3662 uint64_t carext:1;
3663 uint64_t minerr:1;
3664 #else
3665 uint64_t minerr:1;
3666 uint64_t carext:1;
3667 uint64_t maxerr:1;
3668 uint64_t jabber:1;
3669 uint64_t fcserr:1;
3670 uint64_t alnerr:1;
3671 uint64_t lenerr:1;
3672 uint64_t rcverr:1;
3673 uint64_t skperr:1;
3674 uint64_t niberr:1;
3675 uint64_t ovrerr:1;
3676 uint64_t pcterr:1;
3677 uint64_t rsverr:1;
3678 uint64_t falerr:1;
3679 uint64_t coldet:1;
3680 uint64_t ifgerr:1;
3681 uint64_t phy_link:1;
3682 uint64_t phy_spd:1;
3683 uint64_t phy_dupx:1;
3684 uint64_t pause_drp:1;
3685 uint64_t reserved_20_63:44;
3686 #endif
3687 } cn58xx;
3688 struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
3689 struct cvmx_gmxx_rxx_int_en_cn61xx {
3690 #ifdef __BIG_ENDIAN_BITFIELD
3691 uint64_t reserved_29_63:35;
3692 uint64_t hg2cc:1;
3693 uint64_t hg2fld:1;
3694 uint64_t undat:1;
3695 uint64_t uneop:1;
3696 uint64_t unsop:1;
3697 uint64_t bad_term:1;
3698 uint64_t bad_seq:1;
3699 uint64_t rem_fault:1;
3700 uint64_t loc_fault:1;
3701 uint64_t pause_drp:1;
3702 uint64_t reserved_16_18:3;
3703 uint64_t ifgerr:1;
3704 uint64_t coldet:1;
3705 uint64_t falerr:1;
3706 uint64_t rsverr:1;
3707 uint64_t pcterr:1;
3708 uint64_t ovrerr:1;
3709 uint64_t reserved_9_9:1;
3710 uint64_t skperr:1;
3711 uint64_t rcverr:1;
3712 uint64_t reserved_5_6:2;
3713 uint64_t fcserr:1;
3714 uint64_t jabber:1;
3715 uint64_t reserved_2_2:1;
3716 uint64_t carext:1;
3717 uint64_t minerr:1;
3718 #else
3719 uint64_t minerr:1;
3720 uint64_t carext:1;
3721 uint64_t reserved_2_2:1;
3722 uint64_t jabber:1;
3723 uint64_t fcserr:1;
3724 uint64_t reserved_5_6:2;
3725 uint64_t rcverr:1;
3726 uint64_t skperr:1;
3727 uint64_t reserved_9_9:1;
3728 uint64_t ovrerr:1;
3729 uint64_t pcterr:1;
3730 uint64_t rsverr:1;
3731 uint64_t falerr:1;
3732 uint64_t coldet:1;
3733 uint64_t ifgerr:1;
3734 uint64_t reserved_16_18:3;
3735 uint64_t pause_drp:1;
3736 uint64_t loc_fault:1;
3737 uint64_t rem_fault:1;
3738 uint64_t bad_seq:1;
3739 uint64_t bad_term:1;
3740 uint64_t unsop:1;
3741 uint64_t uneop:1;
3742 uint64_t undat:1;
3743 uint64_t hg2fld:1;
3744 uint64_t hg2cc:1;
3745 uint64_t reserved_29_63:35;
3746 #endif
3747 } cn61xx;
3748 struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;
3749 struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;
3750 struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;
3751 struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;
3752 struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;
3753 struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;
3754 };
3755
3756 union cvmx_gmxx_rxx_int_reg {
3757 uint64_t u64;
3758 struct cvmx_gmxx_rxx_int_reg_s {
3759 #ifdef __BIG_ENDIAN_BITFIELD
3760 uint64_t reserved_29_63:35;
3761 uint64_t hg2cc:1;
3762 uint64_t hg2fld:1;
3763 uint64_t undat:1;
3764 uint64_t uneop:1;
3765 uint64_t unsop:1;
3766 uint64_t bad_term:1;
3767 uint64_t bad_seq:1;
3768 uint64_t rem_fault:1;
3769 uint64_t loc_fault:1;
3770 uint64_t pause_drp:1;
3771 uint64_t phy_dupx:1;
3772 uint64_t phy_spd:1;
3773 uint64_t phy_link:1;
3774 uint64_t ifgerr:1;
3775 uint64_t coldet:1;
3776 uint64_t falerr:1;
3777 uint64_t rsverr:1;
3778 uint64_t pcterr:1;
3779 uint64_t ovrerr:1;
3780 uint64_t niberr:1;
3781 uint64_t skperr:1;
3782 uint64_t rcverr:1;
3783 uint64_t lenerr:1;
3784 uint64_t alnerr:1;
3785 uint64_t fcserr:1;
3786 uint64_t jabber:1;
3787 uint64_t maxerr:1;
3788 uint64_t carext:1;
3789 uint64_t minerr:1;
3790 #else
3791 uint64_t minerr:1;
3792 uint64_t carext:1;
3793 uint64_t maxerr:1;
3794 uint64_t jabber:1;
3795 uint64_t fcserr:1;
3796 uint64_t alnerr:1;
3797 uint64_t lenerr:1;
3798 uint64_t rcverr:1;
3799 uint64_t skperr:1;
3800 uint64_t niberr:1;
3801 uint64_t ovrerr:1;
3802 uint64_t pcterr:1;
3803 uint64_t rsverr:1;
3804 uint64_t falerr:1;
3805 uint64_t coldet:1;
3806 uint64_t ifgerr:1;
3807 uint64_t phy_link:1;
3808 uint64_t phy_spd:1;
3809 uint64_t phy_dupx:1;
3810 uint64_t pause_drp:1;
3811 uint64_t loc_fault:1;
3812 uint64_t rem_fault:1;
3813 uint64_t bad_seq:1;
3814 uint64_t bad_term:1;
3815 uint64_t unsop:1;
3816 uint64_t uneop:1;
3817 uint64_t undat:1;
3818 uint64_t hg2fld:1;
3819 uint64_t hg2cc:1;
3820 uint64_t reserved_29_63:35;
3821 #endif
3822 } s;
3823 struct cvmx_gmxx_rxx_int_reg_cn30xx {
3824 #ifdef __BIG_ENDIAN_BITFIELD
3825 uint64_t reserved_19_63:45;
3826 uint64_t phy_dupx:1;
3827 uint64_t phy_spd:1;
3828 uint64_t phy_link:1;
3829 uint64_t ifgerr:1;
3830 uint64_t coldet:1;
3831 uint64_t falerr:1;
3832 uint64_t rsverr:1;
3833 uint64_t pcterr:1;
3834 uint64_t ovrerr:1;
3835 uint64_t niberr:1;
3836 uint64_t skperr:1;
3837 uint64_t rcverr:1;
3838 uint64_t lenerr:1;
3839 uint64_t alnerr:1;
3840 uint64_t fcserr:1;
3841 uint64_t jabber:1;
3842 uint64_t maxerr:1;
3843 uint64_t carext:1;
3844 uint64_t minerr:1;
3845 #else
3846 uint64_t minerr:1;
3847 uint64_t carext:1;
3848 uint64_t maxerr:1;
3849 uint64_t jabber:1;
3850 uint64_t fcserr:1;
3851 uint64_t alnerr:1;
3852 uint64_t lenerr:1;
3853 uint64_t rcverr:1;
3854 uint64_t skperr:1;
3855 uint64_t niberr:1;
3856 uint64_t ovrerr:1;
3857 uint64_t pcterr:1;
3858 uint64_t rsverr:1;
3859 uint64_t falerr:1;
3860 uint64_t coldet:1;
3861 uint64_t ifgerr:1;
3862 uint64_t phy_link:1;
3863 uint64_t phy_spd:1;
3864 uint64_t phy_dupx:1;
3865 uint64_t reserved_19_63:45;
3866 #endif
3867 } cn30xx;
3868 struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
3869 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
3870 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
3871 struct cvmx_gmxx_rxx_int_reg_cn50xx {
3872 #ifdef __BIG_ENDIAN_BITFIELD
3873 uint64_t reserved_20_63:44;
3874 uint64_t pause_drp:1;
3875 uint64_t phy_dupx:1;
3876 uint64_t phy_spd:1;
3877 uint64_t phy_link:1;
3878 uint64_t ifgerr:1;
3879 uint64_t coldet:1;
3880 uint64_t falerr:1;
3881 uint64_t rsverr:1;
3882 uint64_t pcterr:1;
3883 uint64_t ovrerr:1;
3884 uint64_t niberr:1;
3885 uint64_t skperr:1;
3886 uint64_t rcverr:1;
3887 uint64_t reserved_6_6:1;
3888 uint64_t alnerr:1;
3889 uint64_t fcserr:1;
3890 uint64_t jabber:1;
3891 uint64_t reserved_2_2:1;
3892 uint64_t carext:1;
3893 uint64_t reserved_0_0:1;
3894 #else
3895 uint64_t reserved_0_0:1;
3896 uint64_t carext:1;
3897 uint64_t reserved_2_2:1;
3898 uint64_t jabber:1;
3899 uint64_t fcserr:1;
3900 uint64_t alnerr:1;
3901 uint64_t reserved_6_6:1;
3902 uint64_t rcverr:1;
3903 uint64_t skperr:1;
3904 uint64_t niberr:1;
3905 uint64_t ovrerr:1;
3906 uint64_t pcterr:1;
3907 uint64_t rsverr:1;
3908 uint64_t falerr:1;
3909 uint64_t coldet:1;
3910 uint64_t ifgerr:1;
3911 uint64_t phy_link:1;
3912 uint64_t phy_spd:1;
3913 uint64_t phy_dupx:1;
3914 uint64_t pause_drp:1;
3915 uint64_t reserved_20_63:44;
3916 #endif
3917 } cn50xx;
3918 struct cvmx_gmxx_rxx_int_reg_cn52xx {
3919 #ifdef __BIG_ENDIAN_BITFIELD
3920 uint64_t reserved_29_63:35;
3921 uint64_t hg2cc:1;
3922 uint64_t hg2fld:1;
3923 uint64_t undat:1;
3924 uint64_t uneop:1;
3925 uint64_t unsop:1;
3926 uint64_t bad_term:1;
3927 uint64_t bad_seq:1;
3928 uint64_t rem_fault:1;
3929 uint64_t loc_fault:1;
3930 uint64_t pause_drp:1;
3931 uint64_t reserved_16_18:3;
3932 uint64_t ifgerr:1;
3933 uint64_t coldet:1;
3934 uint64_t falerr:1;
3935 uint64_t rsverr:1;
3936 uint64_t pcterr:1;
3937 uint64_t ovrerr:1;
3938 uint64_t reserved_9_9:1;
3939 uint64_t skperr:1;
3940 uint64_t rcverr:1;
3941 uint64_t reserved_5_6:2;
3942 uint64_t fcserr:1;
3943 uint64_t jabber:1;
3944 uint64_t reserved_2_2:1;
3945 uint64_t carext:1;
3946 uint64_t reserved_0_0:1;
3947 #else
3948 uint64_t reserved_0_0:1;
3949 uint64_t carext:1;
3950 uint64_t reserved_2_2:1;
3951 uint64_t jabber:1;
3952 uint64_t fcserr:1;
3953 uint64_t reserved_5_6:2;
3954 uint64_t rcverr:1;
3955 uint64_t skperr:1;
3956 uint64_t reserved_9_9:1;
3957 uint64_t ovrerr:1;
3958 uint64_t pcterr:1;
3959 uint64_t rsverr:1;
3960 uint64_t falerr:1;
3961 uint64_t coldet:1;
3962 uint64_t ifgerr:1;
3963 uint64_t reserved_16_18:3;
3964 uint64_t pause_drp:1;
3965 uint64_t loc_fault:1;
3966 uint64_t rem_fault:1;
3967 uint64_t bad_seq:1;
3968 uint64_t bad_term:1;
3969 uint64_t unsop:1;
3970 uint64_t uneop:1;
3971 uint64_t undat:1;
3972 uint64_t hg2fld:1;
3973 uint64_t hg2cc:1;
3974 uint64_t reserved_29_63:35;
3975 #endif
3976 } cn52xx;
3977 struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
3978 struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
3979 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
3980 #ifdef __BIG_ENDIAN_BITFIELD
3981 uint64_t reserved_27_63:37;
3982 uint64_t undat:1;
3983 uint64_t uneop:1;
3984 uint64_t unsop:1;
3985 uint64_t bad_term:1;
3986 uint64_t bad_seq:1;
3987 uint64_t rem_fault:1;
3988 uint64_t loc_fault:1;
3989 uint64_t pause_drp:1;
3990 uint64_t reserved_16_18:3;
3991 uint64_t ifgerr:1;
3992 uint64_t coldet:1;
3993 uint64_t falerr:1;
3994 uint64_t rsverr:1;
3995 uint64_t pcterr:1;
3996 uint64_t ovrerr:1;
3997 uint64_t reserved_9_9:1;
3998 uint64_t skperr:1;
3999 uint64_t rcverr:1;
4000 uint64_t reserved_5_6:2;
4001 uint64_t fcserr:1;
4002 uint64_t jabber:1;
4003 uint64_t reserved_2_2:1;
4004 uint64_t carext:1;
4005 uint64_t reserved_0_0:1;
4006 #else
4007 uint64_t reserved_0_0:1;
4008 uint64_t carext:1;
4009 uint64_t reserved_2_2:1;
4010 uint64_t jabber:1;
4011 uint64_t fcserr:1;
4012 uint64_t reserved_5_6:2;
4013 uint64_t rcverr:1;
4014 uint64_t skperr:1;
4015 uint64_t reserved_9_9:1;
4016 uint64_t ovrerr:1;
4017 uint64_t pcterr:1;
4018 uint64_t rsverr:1;
4019 uint64_t falerr:1;
4020 uint64_t coldet:1;
4021 uint64_t ifgerr:1;
4022 uint64_t reserved_16_18:3;
4023 uint64_t pause_drp:1;
4024 uint64_t loc_fault:1;
4025 uint64_t rem_fault:1;
4026 uint64_t bad_seq:1;
4027 uint64_t bad_term:1;
4028 uint64_t unsop:1;
4029 uint64_t uneop:1;
4030 uint64_t undat:1;
4031 uint64_t reserved_27_63:37;
4032 #endif
4033 } cn56xxp1;
4034 struct cvmx_gmxx_rxx_int_reg_cn58xx {
4035 #ifdef __BIG_ENDIAN_BITFIELD
4036 uint64_t reserved_20_63:44;
4037 uint64_t pause_drp:1;
4038 uint64_t phy_dupx:1;
4039 uint64_t phy_spd:1;
4040 uint64_t phy_link:1;
4041 uint64_t ifgerr:1;
4042 uint64_t coldet:1;
4043 uint64_t falerr:1;
4044 uint64_t rsverr:1;
4045 uint64_t pcterr:1;
4046 uint64_t ovrerr:1;
4047 uint64_t niberr:1;
4048 uint64_t skperr:1;
4049 uint64_t rcverr:1;
4050 uint64_t lenerr:1;
4051 uint64_t alnerr:1;
4052 uint64_t fcserr:1;
4053 uint64_t jabber:1;
4054 uint64_t maxerr:1;
4055 uint64_t carext:1;
4056 uint64_t minerr:1;
4057 #else
4058 uint64_t minerr:1;
4059 uint64_t carext:1;
4060 uint64_t maxerr:1;
4061 uint64_t jabber:1;
4062 uint64_t fcserr:1;
4063 uint64_t alnerr:1;
4064 uint64_t lenerr:1;
4065 uint64_t rcverr:1;
4066 uint64_t skperr:1;
4067 uint64_t niberr:1;
4068 uint64_t ovrerr:1;
4069 uint64_t pcterr:1;
4070 uint64_t rsverr:1;
4071 uint64_t falerr:1;
4072 uint64_t coldet:1;
4073 uint64_t ifgerr:1;
4074 uint64_t phy_link:1;
4075 uint64_t phy_spd:1;
4076 uint64_t phy_dupx:1;
4077 uint64_t pause_drp:1;
4078 uint64_t reserved_20_63:44;
4079 #endif
4080 } cn58xx;
4081 struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
4082 struct cvmx_gmxx_rxx_int_reg_cn61xx {
4083 #ifdef __BIG_ENDIAN_BITFIELD
4084 uint64_t reserved_29_63:35;
4085 uint64_t hg2cc:1;
4086 uint64_t hg2fld:1;
4087 uint64_t undat:1;
4088 uint64_t uneop:1;
4089 uint64_t unsop:1;
4090 uint64_t bad_term:1;
4091 uint64_t bad_seq:1;
4092 uint64_t rem_fault:1;
4093 uint64_t loc_fault:1;
4094 uint64_t pause_drp:1;
4095 uint64_t reserved_16_18:3;
4096 uint64_t ifgerr:1;
4097 uint64_t coldet:1;
4098 uint64_t falerr:1;
4099 uint64_t rsverr:1;
4100 uint64_t pcterr:1;
4101 uint64_t ovrerr:1;
4102 uint64_t reserved_9_9:1;
4103 uint64_t skperr:1;
4104 uint64_t rcverr:1;
4105 uint64_t reserved_5_6:2;
4106 uint64_t fcserr:1;
4107 uint64_t jabber:1;
4108 uint64_t reserved_2_2:1;
4109 uint64_t carext:1;
4110 uint64_t minerr:1;
4111 #else
4112 uint64_t minerr:1;
4113 uint64_t carext:1;
4114 uint64_t reserved_2_2:1;
4115 uint64_t jabber:1;
4116 uint64_t fcserr:1;
4117 uint64_t reserved_5_6:2;
4118 uint64_t rcverr:1;
4119 uint64_t skperr:1;
4120 uint64_t reserved_9_9:1;
4121 uint64_t ovrerr:1;
4122 uint64_t pcterr:1;
4123 uint64_t rsverr:1;
4124 uint64_t falerr:1;
4125 uint64_t coldet:1;
4126 uint64_t ifgerr:1;
4127 uint64_t reserved_16_18:3;
4128 uint64_t pause_drp:1;
4129 uint64_t loc_fault:1;
4130 uint64_t rem_fault:1;
4131 uint64_t bad_seq:1;
4132 uint64_t bad_term:1;
4133 uint64_t unsop:1;
4134 uint64_t uneop:1;
4135 uint64_t undat:1;
4136 uint64_t hg2fld:1;
4137 uint64_t hg2cc:1;
4138 uint64_t reserved_29_63:35;
4139 #endif
4140 } cn61xx;
4141 struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx;
4142 struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1;
4143 struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx;
4144 struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx;
4145 struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1;
4146 struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx;
4147 };
4148
4149 union cvmx_gmxx_rxx_jabber {
4150 uint64_t u64;
4151 struct cvmx_gmxx_rxx_jabber_s {
4152 #ifdef __BIG_ENDIAN_BITFIELD
4153 uint64_t reserved_16_63:48;
4154 uint64_t cnt:16;
4155 #else
4156 uint64_t cnt:16;
4157 uint64_t reserved_16_63:48;
4158 #endif
4159 } s;
4160 struct cvmx_gmxx_rxx_jabber_s cn30xx;
4161 struct cvmx_gmxx_rxx_jabber_s cn31xx;
4162 struct cvmx_gmxx_rxx_jabber_s cn38xx;
4163 struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
4164 struct cvmx_gmxx_rxx_jabber_s cn50xx;
4165 struct cvmx_gmxx_rxx_jabber_s cn52xx;
4166 struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
4167 struct cvmx_gmxx_rxx_jabber_s cn56xx;
4168 struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
4169 struct cvmx_gmxx_rxx_jabber_s cn58xx;
4170 struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
4171 struct cvmx_gmxx_rxx_jabber_s cn61xx;
4172 struct cvmx_gmxx_rxx_jabber_s cn63xx;
4173 struct cvmx_gmxx_rxx_jabber_s cn63xxp1;
4174 struct cvmx_gmxx_rxx_jabber_s cn66xx;
4175 struct cvmx_gmxx_rxx_jabber_s cn68xx;
4176 struct cvmx_gmxx_rxx_jabber_s cn68xxp1;
4177 struct cvmx_gmxx_rxx_jabber_s cnf71xx;
4178 };
4179
4180 union cvmx_gmxx_rxx_pause_drop_time {
4181 uint64_t u64;
4182 struct cvmx_gmxx_rxx_pause_drop_time_s {
4183 #ifdef __BIG_ENDIAN_BITFIELD
4184 uint64_t reserved_16_63:48;
4185 uint64_t status:16;
4186 #else
4187 uint64_t status:16;
4188 uint64_t reserved_16_63:48;
4189 #endif
4190 } s;
4191 struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
4192 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
4193 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
4194 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
4195 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
4196 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
4197 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
4198 struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;
4199 struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
4200 struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
4201 struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;
4202 struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;
4203 struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;
4204 struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;
4205 };
4206
4207 union cvmx_gmxx_rxx_rx_inbnd {
4208 uint64_t u64;
4209 struct cvmx_gmxx_rxx_rx_inbnd_s {
4210 #ifdef __BIG_ENDIAN_BITFIELD
4211 uint64_t reserved_4_63:60;
4212 uint64_t duplex:1;
4213 uint64_t speed:2;
4214 uint64_t status:1;
4215 #else
4216 uint64_t status:1;
4217 uint64_t speed:2;
4218 uint64_t duplex:1;
4219 uint64_t reserved_4_63:60;
4220 #endif
4221 } s;
4222 struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
4223 struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
4224 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
4225 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
4226 struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
4227 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
4228 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
4229 };
4230
4231 union cvmx_gmxx_rxx_stats_ctl {
4232 uint64_t u64;
4233 struct cvmx_gmxx_rxx_stats_ctl_s {
4234 #ifdef __BIG_ENDIAN_BITFIELD
4235 uint64_t reserved_1_63:63;
4236 uint64_t rd_clr:1;
4237 #else
4238 uint64_t rd_clr:1;
4239 uint64_t reserved_1_63:63;
4240 #endif
4241 } s;
4242 struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
4243 struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
4244 struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
4245 struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
4246 struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
4247 struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
4248 struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
4249 struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
4250 struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
4251 struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
4252 struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
4253 struct cvmx_gmxx_rxx_stats_ctl_s cn61xx;
4254 struct cvmx_gmxx_rxx_stats_ctl_s cn63xx;
4255 struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1;
4256 struct cvmx_gmxx_rxx_stats_ctl_s cn66xx;
4257 struct cvmx_gmxx_rxx_stats_ctl_s cn68xx;
4258 struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1;
4259 struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx;
4260 };
4261
4262 union cvmx_gmxx_rxx_stats_octs {
4263 uint64_t u64;
4264 struct cvmx_gmxx_rxx_stats_octs_s {
4265 #ifdef __BIG_ENDIAN_BITFIELD
4266 uint64_t reserved_48_63:16;
4267 uint64_t cnt:48;
4268 #else
4269 uint64_t cnt:48;
4270 uint64_t reserved_48_63:16;
4271 #endif
4272 } s;
4273 struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
4274 struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
4275 struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
4276 struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
4277 struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
4278 struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
4279 struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
4280 struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
4281 struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
4282 struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
4283 struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
4284 struct cvmx_gmxx_rxx_stats_octs_s cn61xx;
4285 struct cvmx_gmxx_rxx_stats_octs_s cn63xx;
4286 struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1;
4287 struct cvmx_gmxx_rxx_stats_octs_s cn66xx;
4288 struct cvmx_gmxx_rxx_stats_octs_s cn68xx;
4289 struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1;
4290 struct cvmx_gmxx_rxx_stats_octs_s cnf71xx;
4291 };
4292
4293 union cvmx_gmxx_rxx_stats_octs_ctl {
4294 uint64_t u64;
4295 struct cvmx_gmxx_rxx_stats_octs_ctl_s {
4296 #ifdef __BIG_ENDIAN_BITFIELD
4297 uint64_t reserved_48_63:16;
4298 uint64_t cnt:48;
4299 #else
4300 uint64_t cnt:48;
4301 uint64_t reserved_48_63:16;
4302 #endif
4303 } s;
4304 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
4305 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
4306 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
4307 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
4308 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
4309 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
4310 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
4311 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
4312 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
4313 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
4314 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
4315 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;
4316 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
4317 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
4318 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;
4319 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;
4320 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;
4321 struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;
4322 };
4323
4324 union cvmx_gmxx_rxx_stats_octs_dmac {
4325 uint64_t u64;
4326 struct cvmx_gmxx_rxx_stats_octs_dmac_s {
4327 #ifdef __BIG_ENDIAN_BITFIELD
4328 uint64_t reserved_48_63:16;
4329 uint64_t cnt:48;
4330 #else
4331 uint64_t cnt:48;
4332 uint64_t reserved_48_63:16;
4333 #endif
4334 } s;
4335 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
4336 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
4337 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
4338 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
4339 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
4340 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
4341 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
4342 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
4343 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
4344 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
4345 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
4346 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;
4347 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
4348 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
4349 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;
4350 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;
4351 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;
4352 struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;
4353 };
4354
4355 union cvmx_gmxx_rxx_stats_octs_drp {
4356 uint64_t u64;
4357 struct cvmx_gmxx_rxx_stats_octs_drp_s {
4358 #ifdef __BIG_ENDIAN_BITFIELD
4359 uint64_t reserved_48_63:16;
4360 uint64_t cnt:48;
4361 #else
4362 uint64_t cnt:48;
4363 uint64_t reserved_48_63:16;
4364 #endif
4365 } s;
4366 struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
4367 struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
4368 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
4369 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
4370 struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
4371 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
4372 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
4373 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
4374 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
4375 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
4376 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
4377 struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;
4378 struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
4379 struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
4380 struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;
4381 struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;
4382 struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;
4383 struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;
4384 };
4385
4386 union cvmx_gmxx_rxx_stats_pkts {
4387 uint64_t u64;
4388 struct cvmx_gmxx_rxx_stats_pkts_s {
4389 #ifdef __BIG_ENDIAN_BITFIELD
4390 uint64_t reserved_32_63:32;
4391 uint64_t cnt:32;
4392 #else
4393 uint64_t cnt:32;
4394 uint64_t reserved_32_63:32;
4395 #endif
4396 } s;
4397 struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
4398 struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
4399 struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
4400 struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
4401 struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
4402 struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
4403 struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
4404 struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
4405 struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
4406 struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
4407 struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
4408 struct cvmx_gmxx_rxx_stats_pkts_s cn61xx;
4409 struct cvmx_gmxx_rxx_stats_pkts_s cn63xx;
4410 struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1;
4411 struct cvmx_gmxx_rxx_stats_pkts_s cn66xx;
4412 struct cvmx_gmxx_rxx_stats_pkts_s cn68xx;
4413 struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1;
4414 struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx;
4415 };
4416
4417 union cvmx_gmxx_rxx_stats_pkts_bad {
4418 uint64_t u64;
4419 struct cvmx_gmxx_rxx_stats_pkts_bad_s {
4420 #ifdef __BIG_ENDIAN_BITFIELD
4421 uint64_t reserved_32_63:32;
4422 uint64_t cnt:32;
4423 #else
4424 uint64_t cnt:32;
4425 uint64_t reserved_32_63:32;
4426 #endif
4427 } s;
4428 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
4429 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
4430 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
4431 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
4432 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
4433 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
4434 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
4435 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
4436 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
4437 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
4438 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
4439 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;
4440 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
4441 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
4442 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;
4443 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;
4444 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;
4445 struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;
4446 };
4447
4448 union cvmx_gmxx_rxx_stats_pkts_ctl {
4449 uint64_t u64;
4450 struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
4451 #ifdef __BIG_ENDIAN_BITFIELD
4452 uint64_t reserved_32_63:32;
4453 uint64_t cnt:32;
4454 #else
4455 uint64_t cnt:32;
4456 uint64_t reserved_32_63:32;
4457 #endif
4458 } s;
4459 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
4460 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
4461 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
4462 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
4463 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
4464 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
4465 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
4466 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
4467 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
4468 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
4469 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
4470 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;
4471 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
4472 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
4473 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;
4474 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;
4475 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;
4476 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;
4477 };
4478
4479 union cvmx_gmxx_rxx_stats_pkts_dmac {
4480 uint64_t u64;
4481 struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
4482 #ifdef __BIG_ENDIAN_BITFIELD
4483 uint64_t reserved_32_63:32;
4484 uint64_t cnt:32;
4485 #else
4486 uint64_t cnt:32;
4487 uint64_t reserved_32_63:32;
4488 #endif
4489 } s;
4490 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
4491 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
4492 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
4493 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
4494 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
4495 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
4496 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
4497 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
4498 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
4499 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
4500 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
4501 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;
4502 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
4503 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
4504 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;
4505 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;
4506 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;
4507 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;
4508 };
4509
4510 union cvmx_gmxx_rxx_stats_pkts_drp {
4511 uint64_t u64;
4512 struct cvmx_gmxx_rxx_stats_pkts_drp_s {
4513 #ifdef __BIG_ENDIAN_BITFIELD
4514 uint64_t reserved_32_63:32;
4515 uint64_t cnt:32;
4516 #else
4517 uint64_t cnt:32;
4518 uint64_t reserved_32_63:32;
4519 #endif
4520 } s;
4521 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
4522 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
4523 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
4524 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
4525 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
4526 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
4527 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
4528 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
4529 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
4530 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
4531 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
4532 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;
4533 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
4534 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
4535 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;
4536 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;
4537 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;
4538 struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;
4539 };
4540
4541 union cvmx_gmxx_rxx_udd_skp {
4542 uint64_t u64;
4543 struct cvmx_gmxx_rxx_udd_skp_s {
4544 #ifdef __BIG_ENDIAN_BITFIELD
4545 uint64_t reserved_9_63:55;
4546 uint64_t fcssel:1;
4547 uint64_t reserved_7_7:1;
4548 uint64_t len:7;
4549 #else
4550 uint64_t len:7;
4551 uint64_t reserved_7_7:1;
4552 uint64_t fcssel:1;
4553 uint64_t reserved_9_63:55;
4554 #endif
4555 } s;
4556 struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
4557 struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
4558 struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
4559 struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
4560 struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
4561 struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
4562 struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
4563 struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
4564 struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
4565 struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
4566 struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
4567 struct cvmx_gmxx_rxx_udd_skp_s cn61xx;
4568 struct cvmx_gmxx_rxx_udd_skp_s cn63xx;
4569 struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1;
4570 struct cvmx_gmxx_rxx_udd_skp_s cn66xx;
4571 struct cvmx_gmxx_rxx_udd_skp_s cn68xx;
4572 struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1;
4573 struct cvmx_gmxx_rxx_udd_skp_s cnf71xx;
4574 };
4575
4576 union cvmx_gmxx_rx_bp_dropx {
4577 uint64_t u64;
4578 struct cvmx_gmxx_rx_bp_dropx_s {
4579 #ifdef __BIG_ENDIAN_BITFIELD
4580 uint64_t reserved_6_63:58;
4581 uint64_t mark:6;
4582 #else
4583 uint64_t mark:6;
4584 uint64_t reserved_6_63:58;
4585 #endif
4586 } s;
4587 struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
4588 struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
4589 struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
4590 struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
4591 struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
4592 struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
4593 struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
4594 struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
4595 struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
4596 struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
4597 struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
4598 struct cvmx_gmxx_rx_bp_dropx_s cn61xx;
4599 struct cvmx_gmxx_rx_bp_dropx_s cn63xx;
4600 struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1;
4601 struct cvmx_gmxx_rx_bp_dropx_s cn66xx;
4602 struct cvmx_gmxx_rx_bp_dropx_s cn68xx;
4603 struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1;
4604 struct cvmx_gmxx_rx_bp_dropx_s cnf71xx;
4605 };
4606
4607 union cvmx_gmxx_rx_bp_offx {
4608 uint64_t u64;
4609 struct cvmx_gmxx_rx_bp_offx_s {
4610 #ifdef __BIG_ENDIAN_BITFIELD
4611 uint64_t reserved_6_63:58;
4612 uint64_t mark:6;
4613 #else
4614 uint64_t mark:6;
4615 uint64_t reserved_6_63:58;
4616 #endif
4617 } s;
4618 struct cvmx_gmxx_rx_bp_offx_s cn30xx;
4619 struct cvmx_gmxx_rx_bp_offx_s cn31xx;
4620 struct cvmx_gmxx_rx_bp_offx_s cn38xx;
4621 struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
4622 struct cvmx_gmxx_rx_bp_offx_s cn50xx;
4623 struct cvmx_gmxx_rx_bp_offx_s cn52xx;
4624 struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
4625 struct cvmx_gmxx_rx_bp_offx_s cn56xx;
4626 struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
4627 struct cvmx_gmxx_rx_bp_offx_s cn58xx;
4628 struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
4629 struct cvmx_gmxx_rx_bp_offx_s cn61xx;
4630 struct cvmx_gmxx_rx_bp_offx_s cn63xx;
4631 struct cvmx_gmxx_rx_bp_offx_s cn63xxp1;
4632 struct cvmx_gmxx_rx_bp_offx_s cn66xx;
4633 struct cvmx_gmxx_rx_bp_offx_s cn68xx;
4634 struct cvmx_gmxx_rx_bp_offx_s cn68xxp1;
4635 struct cvmx_gmxx_rx_bp_offx_s cnf71xx;
4636 };
4637
4638 union cvmx_gmxx_rx_bp_onx {
4639 uint64_t u64;
4640 struct cvmx_gmxx_rx_bp_onx_s {
4641 #ifdef __BIG_ENDIAN_BITFIELD
4642 uint64_t reserved_11_63:53;
4643 uint64_t mark:11;
4644 #else
4645 uint64_t mark:11;
4646 uint64_t reserved_11_63:53;
4647 #endif
4648 } s;
4649 struct cvmx_gmxx_rx_bp_onx_cn30xx {
4650 #ifdef __BIG_ENDIAN_BITFIELD
4651 uint64_t reserved_9_63:55;
4652 uint64_t mark:9;
4653 #else
4654 uint64_t mark:9;
4655 uint64_t reserved_9_63:55;
4656 #endif
4657 } cn30xx;
4658 struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx;
4659 struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx;
4660 struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2;
4661 struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx;
4662 struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx;
4663 struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1;
4664 struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx;
4665 struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1;
4666 struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx;
4667 struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1;
4668 struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx;
4669 struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx;
4670 struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1;
4671 struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx;
4672 struct cvmx_gmxx_rx_bp_onx_s cn68xx;
4673 struct cvmx_gmxx_rx_bp_onx_s cn68xxp1;
4674 struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx;
4675 };
4676
4677 union cvmx_gmxx_rx_hg2_status {
4678 uint64_t u64;
4679 struct cvmx_gmxx_rx_hg2_status_s {
4680 #ifdef __BIG_ENDIAN_BITFIELD
4681 uint64_t reserved_48_63:16;
4682 uint64_t phtim2go:16;
4683 uint64_t xof:16;
4684 uint64_t lgtim2go:16;
4685 #else
4686 uint64_t lgtim2go:16;
4687 uint64_t xof:16;
4688 uint64_t phtim2go:16;
4689 uint64_t reserved_48_63:16;
4690 #endif
4691 } s;
4692 struct cvmx_gmxx_rx_hg2_status_s cn52xx;
4693 struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
4694 struct cvmx_gmxx_rx_hg2_status_s cn56xx;
4695 struct cvmx_gmxx_rx_hg2_status_s cn61xx;
4696 struct cvmx_gmxx_rx_hg2_status_s cn63xx;
4697 struct cvmx_gmxx_rx_hg2_status_s cn63xxp1;
4698 struct cvmx_gmxx_rx_hg2_status_s cn66xx;
4699 struct cvmx_gmxx_rx_hg2_status_s cn68xx;
4700 struct cvmx_gmxx_rx_hg2_status_s cn68xxp1;
4701 struct cvmx_gmxx_rx_hg2_status_s cnf71xx;
4702 };
4703
4704 union cvmx_gmxx_rx_pass_en {
4705 uint64_t u64;
4706 struct cvmx_gmxx_rx_pass_en_s {
4707 #ifdef __BIG_ENDIAN_BITFIELD
4708 uint64_t reserved_16_63:48;
4709 uint64_t en:16;
4710 #else
4711 uint64_t en:16;
4712 uint64_t reserved_16_63:48;
4713 #endif
4714 } s;
4715 struct cvmx_gmxx_rx_pass_en_s cn38xx;
4716 struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
4717 struct cvmx_gmxx_rx_pass_en_s cn58xx;
4718 struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
4719 };
4720
4721 union cvmx_gmxx_rx_pass_mapx {
4722 uint64_t u64;
4723 struct cvmx_gmxx_rx_pass_mapx_s {
4724 #ifdef __BIG_ENDIAN_BITFIELD
4725 uint64_t reserved_4_63:60;
4726 uint64_t dprt:4;
4727 #else
4728 uint64_t dprt:4;
4729 uint64_t reserved_4_63:60;
4730 #endif
4731 } s;
4732 struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
4733 struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
4734 struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
4735 struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
4736 };
4737
4738 union cvmx_gmxx_rx_prt_info {
4739 uint64_t u64;
4740 struct cvmx_gmxx_rx_prt_info_s {
4741 #ifdef __BIG_ENDIAN_BITFIELD
4742 uint64_t reserved_32_63:32;
4743 uint64_t drop:16;
4744 uint64_t commit:16;
4745 #else
4746 uint64_t commit:16;
4747 uint64_t drop:16;
4748 uint64_t reserved_32_63:32;
4749 #endif
4750 } s;
4751 struct cvmx_gmxx_rx_prt_info_cn30xx {
4752 #ifdef __BIG_ENDIAN_BITFIELD
4753 uint64_t reserved_19_63:45;
4754 uint64_t drop:3;
4755 uint64_t reserved_3_15:13;
4756 uint64_t commit:3;
4757 #else
4758 uint64_t commit:3;
4759 uint64_t reserved_3_15:13;
4760 uint64_t drop:3;
4761 uint64_t reserved_19_63:45;
4762 #endif
4763 } cn30xx;
4764 struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
4765 struct cvmx_gmxx_rx_prt_info_s cn38xx;
4766 struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
4767 struct cvmx_gmxx_rx_prt_info_cn52xx {
4768 #ifdef __BIG_ENDIAN_BITFIELD
4769 uint64_t reserved_20_63:44;
4770 uint64_t drop:4;
4771 uint64_t reserved_4_15:12;
4772 uint64_t commit:4;
4773 #else
4774 uint64_t commit:4;
4775 uint64_t reserved_4_15:12;
4776 uint64_t drop:4;
4777 uint64_t reserved_20_63:44;
4778 #endif
4779 } cn52xx;
4780 struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
4781 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
4782 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
4783 struct cvmx_gmxx_rx_prt_info_s cn58xx;
4784 struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
4785 struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx;
4786 struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx;
4787 struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1;
4788 struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx;
4789 struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx;
4790 struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1;
4791 struct cvmx_gmxx_rx_prt_info_cnf71xx {
4792 #ifdef __BIG_ENDIAN_BITFIELD
4793 uint64_t reserved_18_63:46;
4794 uint64_t drop:2;
4795 uint64_t reserved_2_15:14;
4796 uint64_t commit:2;
4797 #else
4798 uint64_t commit:2;
4799 uint64_t reserved_2_15:14;
4800 uint64_t drop:2;
4801 uint64_t reserved_18_63:46;
4802 #endif
4803 } cnf71xx;
4804 };
4805
4806 union cvmx_gmxx_rx_prts {
4807 uint64_t u64;
4808 struct cvmx_gmxx_rx_prts_s {
4809 #ifdef __BIG_ENDIAN_BITFIELD
4810 uint64_t reserved_3_63:61;
4811 uint64_t prts:3;
4812 #else
4813 uint64_t prts:3;
4814 uint64_t reserved_3_63:61;
4815 #endif
4816 } s;
4817 struct cvmx_gmxx_rx_prts_s cn30xx;
4818 struct cvmx_gmxx_rx_prts_s cn31xx;
4819 struct cvmx_gmxx_rx_prts_s cn38xx;
4820 struct cvmx_gmxx_rx_prts_s cn38xxp2;
4821 struct cvmx_gmxx_rx_prts_s cn50xx;
4822 struct cvmx_gmxx_rx_prts_s cn52xx;
4823 struct cvmx_gmxx_rx_prts_s cn52xxp1;
4824 struct cvmx_gmxx_rx_prts_s cn56xx;
4825 struct cvmx_gmxx_rx_prts_s cn56xxp1;
4826 struct cvmx_gmxx_rx_prts_s cn58xx;
4827 struct cvmx_gmxx_rx_prts_s cn58xxp1;
4828 struct cvmx_gmxx_rx_prts_s cn61xx;
4829 struct cvmx_gmxx_rx_prts_s cn63xx;
4830 struct cvmx_gmxx_rx_prts_s cn63xxp1;
4831 struct cvmx_gmxx_rx_prts_s cn66xx;
4832 struct cvmx_gmxx_rx_prts_s cn68xx;
4833 struct cvmx_gmxx_rx_prts_s cn68xxp1;
4834 struct cvmx_gmxx_rx_prts_s cnf71xx;
4835 };
4836
4837 union cvmx_gmxx_rx_tx_status {
4838 uint64_t u64;
4839 struct cvmx_gmxx_rx_tx_status_s {
4840 #ifdef __BIG_ENDIAN_BITFIELD
4841 uint64_t reserved_7_63:57;
4842 uint64_t tx:3;
4843 uint64_t reserved_3_3:1;
4844 uint64_t rx:3;
4845 #else
4846 uint64_t rx:3;
4847 uint64_t reserved_3_3:1;
4848 uint64_t tx:3;
4849 uint64_t reserved_7_63:57;
4850 #endif
4851 } s;
4852 struct cvmx_gmxx_rx_tx_status_s cn30xx;
4853 struct cvmx_gmxx_rx_tx_status_s cn31xx;
4854 struct cvmx_gmxx_rx_tx_status_s cn50xx;
4855 };
4856
4857 union cvmx_gmxx_rx_xaui_bad_col {
4858 uint64_t u64;
4859 struct cvmx_gmxx_rx_xaui_bad_col_s {
4860 #ifdef __BIG_ENDIAN_BITFIELD
4861 uint64_t reserved_40_63:24;
4862 uint64_t val:1;
4863 uint64_t state:3;
4864 uint64_t lane_rxc:4;
4865 uint64_t lane_rxd:32;
4866 #else
4867 uint64_t lane_rxd:32;
4868 uint64_t lane_rxc:4;
4869 uint64_t state:3;
4870 uint64_t val:1;
4871 uint64_t reserved_40_63:24;
4872 #endif
4873 } s;
4874 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
4875 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
4876 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
4877 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
4878 struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx;
4879 struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx;
4880 struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1;
4881 struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx;
4882 struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx;
4883 struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1;
4884 struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx;
4885 };
4886
4887 union cvmx_gmxx_rx_xaui_ctl {
4888 uint64_t u64;
4889 struct cvmx_gmxx_rx_xaui_ctl_s {
4890 #ifdef __BIG_ENDIAN_BITFIELD
4891 uint64_t reserved_2_63:62;
4892 uint64_t status:2;
4893 #else
4894 uint64_t status:2;
4895 uint64_t reserved_2_63:62;
4896 #endif
4897 } s;
4898 struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
4899 struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
4900 struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
4901 struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
4902 struct cvmx_gmxx_rx_xaui_ctl_s cn61xx;
4903 struct cvmx_gmxx_rx_xaui_ctl_s cn63xx;
4904 struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1;
4905 struct cvmx_gmxx_rx_xaui_ctl_s cn66xx;
4906 struct cvmx_gmxx_rx_xaui_ctl_s cn68xx;
4907 struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1;
4908 struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx;
4909 };
4910
4911 union cvmx_gmxx_rxaui_ctl {
4912 uint64_t u64;
4913 struct cvmx_gmxx_rxaui_ctl_s {
4914 #ifdef __BIG_ENDIAN_BITFIELD
4915 uint64_t reserved_1_63:63;
4916 uint64_t disparity:1;
4917 #else
4918 uint64_t disparity:1;
4919 uint64_t reserved_1_63:63;
4920 #endif
4921 } s;
4922 struct cvmx_gmxx_rxaui_ctl_s cn68xx;
4923 struct cvmx_gmxx_rxaui_ctl_s cn68xxp1;
4924 };
4925
4926 union cvmx_gmxx_smacx {
4927 uint64_t u64;
4928 struct cvmx_gmxx_smacx_s {
4929 #ifdef __BIG_ENDIAN_BITFIELD
4930 uint64_t reserved_48_63:16;
4931 uint64_t smac:48;
4932 #else
4933 uint64_t smac:48;
4934 uint64_t reserved_48_63:16;
4935 #endif
4936 } s;
4937 struct cvmx_gmxx_smacx_s cn30xx;
4938 struct cvmx_gmxx_smacx_s cn31xx;
4939 struct cvmx_gmxx_smacx_s cn38xx;
4940 struct cvmx_gmxx_smacx_s cn38xxp2;
4941 struct cvmx_gmxx_smacx_s cn50xx;
4942 struct cvmx_gmxx_smacx_s cn52xx;
4943 struct cvmx_gmxx_smacx_s cn52xxp1;
4944 struct cvmx_gmxx_smacx_s cn56xx;
4945 struct cvmx_gmxx_smacx_s cn56xxp1;
4946 struct cvmx_gmxx_smacx_s cn58xx;
4947 struct cvmx_gmxx_smacx_s cn58xxp1;
4948 struct cvmx_gmxx_smacx_s cn61xx;
4949 struct cvmx_gmxx_smacx_s cn63xx;
4950 struct cvmx_gmxx_smacx_s cn63xxp1;
4951 struct cvmx_gmxx_smacx_s cn66xx;
4952 struct cvmx_gmxx_smacx_s cn68xx;
4953 struct cvmx_gmxx_smacx_s cn68xxp1;
4954 struct cvmx_gmxx_smacx_s cnf71xx;
4955 };
4956
4957 union cvmx_gmxx_soft_bist {
4958 uint64_t u64;
4959 struct cvmx_gmxx_soft_bist_s {
4960 #ifdef __BIG_ENDIAN_BITFIELD
4961 uint64_t reserved_2_63:62;
4962 uint64_t start_bist:1;
4963 uint64_t clear_bist:1;
4964 #else
4965 uint64_t clear_bist:1;
4966 uint64_t start_bist:1;
4967 uint64_t reserved_2_63:62;
4968 #endif
4969 } s;
4970 struct cvmx_gmxx_soft_bist_s cn63xx;
4971 struct cvmx_gmxx_soft_bist_s cn63xxp1;
4972 struct cvmx_gmxx_soft_bist_s cn66xx;
4973 struct cvmx_gmxx_soft_bist_s cn68xx;
4974 struct cvmx_gmxx_soft_bist_s cn68xxp1;
4975 };
4976
4977 union cvmx_gmxx_stat_bp {
4978 uint64_t u64;
4979 struct cvmx_gmxx_stat_bp_s {
4980 #ifdef __BIG_ENDIAN_BITFIELD
4981 uint64_t reserved_17_63:47;
4982 uint64_t bp:1;
4983 uint64_t cnt:16;
4984 #else
4985 uint64_t cnt:16;
4986 uint64_t bp:1;
4987 uint64_t reserved_17_63:47;
4988 #endif
4989 } s;
4990 struct cvmx_gmxx_stat_bp_s cn30xx;
4991 struct cvmx_gmxx_stat_bp_s cn31xx;
4992 struct cvmx_gmxx_stat_bp_s cn38xx;
4993 struct cvmx_gmxx_stat_bp_s cn38xxp2;
4994 struct cvmx_gmxx_stat_bp_s cn50xx;
4995 struct cvmx_gmxx_stat_bp_s cn52xx;
4996 struct cvmx_gmxx_stat_bp_s cn52xxp1;
4997 struct cvmx_gmxx_stat_bp_s cn56xx;
4998 struct cvmx_gmxx_stat_bp_s cn56xxp1;
4999 struct cvmx_gmxx_stat_bp_s cn58xx;
5000 struct cvmx_gmxx_stat_bp_s cn58xxp1;
5001 struct cvmx_gmxx_stat_bp_s cn61xx;
5002 struct cvmx_gmxx_stat_bp_s cn63xx;
5003 struct cvmx_gmxx_stat_bp_s cn63xxp1;
5004 struct cvmx_gmxx_stat_bp_s cn66xx;
5005 struct cvmx_gmxx_stat_bp_s cn68xx;
5006 struct cvmx_gmxx_stat_bp_s cn68xxp1;
5007 struct cvmx_gmxx_stat_bp_s cnf71xx;
5008 };
5009
5010 union cvmx_gmxx_tb_reg {
5011 uint64_t u64;
5012 struct cvmx_gmxx_tb_reg_s {
5013 #ifdef __BIG_ENDIAN_BITFIELD
5014 uint64_t reserved_1_63:63;
5015 uint64_t wr_magic:1;
5016 #else
5017 uint64_t wr_magic:1;
5018 uint64_t reserved_1_63:63;
5019 #endif
5020 } s;
5021 struct cvmx_gmxx_tb_reg_s cn61xx;
5022 struct cvmx_gmxx_tb_reg_s cn66xx;
5023 struct cvmx_gmxx_tb_reg_s cn68xx;
5024 struct cvmx_gmxx_tb_reg_s cnf71xx;
5025 };
5026
5027 union cvmx_gmxx_txx_append {
5028 uint64_t u64;
5029 struct cvmx_gmxx_txx_append_s {
5030 #ifdef __BIG_ENDIAN_BITFIELD
5031 uint64_t reserved_4_63:60;
5032 uint64_t force_fcs:1;
5033 uint64_t fcs:1;
5034 uint64_t pad:1;
5035 uint64_t preamble:1;
5036 #else
5037 uint64_t preamble:1;
5038 uint64_t pad:1;
5039 uint64_t fcs:1;
5040 uint64_t force_fcs:1;
5041 uint64_t reserved_4_63:60;
5042 #endif
5043 } s;
5044 struct cvmx_gmxx_txx_append_s cn30xx;
5045 struct cvmx_gmxx_txx_append_s cn31xx;
5046 struct cvmx_gmxx_txx_append_s cn38xx;
5047 struct cvmx_gmxx_txx_append_s cn38xxp2;
5048 struct cvmx_gmxx_txx_append_s cn50xx;
5049 struct cvmx_gmxx_txx_append_s cn52xx;
5050 struct cvmx_gmxx_txx_append_s cn52xxp1;
5051 struct cvmx_gmxx_txx_append_s cn56xx;
5052 struct cvmx_gmxx_txx_append_s cn56xxp1;
5053 struct cvmx_gmxx_txx_append_s cn58xx;
5054 struct cvmx_gmxx_txx_append_s cn58xxp1;
5055 struct cvmx_gmxx_txx_append_s cn61xx;
5056 struct cvmx_gmxx_txx_append_s cn63xx;
5057 struct cvmx_gmxx_txx_append_s cn63xxp1;
5058 struct cvmx_gmxx_txx_append_s cn66xx;
5059 struct cvmx_gmxx_txx_append_s cn68xx;
5060 struct cvmx_gmxx_txx_append_s cn68xxp1;
5061 struct cvmx_gmxx_txx_append_s cnf71xx;
5062 };
5063
5064 union cvmx_gmxx_txx_burst {
5065 uint64_t u64;
5066 struct cvmx_gmxx_txx_burst_s {
5067 #ifdef __BIG_ENDIAN_BITFIELD
5068 uint64_t reserved_16_63:48;
5069 uint64_t burst:16;
5070 #else
5071 uint64_t burst:16;
5072 uint64_t reserved_16_63:48;
5073 #endif
5074 } s;
5075 struct cvmx_gmxx_txx_burst_s cn30xx;
5076 struct cvmx_gmxx_txx_burst_s cn31xx;
5077 struct cvmx_gmxx_txx_burst_s cn38xx;
5078 struct cvmx_gmxx_txx_burst_s cn38xxp2;
5079 struct cvmx_gmxx_txx_burst_s cn50xx;
5080 struct cvmx_gmxx_txx_burst_s cn52xx;
5081 struct cvmx_gmxx_txx_burst_s cn52xxp1;
5082 struct cvmx_gmxx_txx_burst_s cn56xx;
5083 struct cvmx_gmxx_txx_burst_s cn56xxp1;
5084 struct cvmx_gmxx_txx_burst_s cn58xx;
5085 struct cvmx_gmxx_txx_burst_s cn58xxp1;
5086 struct cvmx_gmxx_txx_burst_s cn61xx;
5087 struct cvmx_gmxx_txx_burst_s cn63xx;
5088 struct cvmx_gmxx_txx_burst_s cn63xxp1;
5089 struct cvmx_gmxx_txx_burst_s cn66xx;
5090 struct cvmx_gmxx_txx_burst_s cn68xx;
5091 struct cvmx_gmxx_txx_burst_s cn68xxp1;
5092 struct cvmx_gmxx_txx_burst_s cnf71xx;
5093 };
5094
5095 union cvmx_gmxx_txx_cbfc_xoff {
5096 uint64_t u64;
5097 struct cvmx_gmxx_txx_cbfc_xoff_s {
5098 #ifdef __BIG_ENDIAN_BITFIELD
5099 uint64_t reserved_16_63:48;
5100 uint64_t xoff:16;
5101 #else
5102 uint64_t xoff:16;
5103 uint64_t reserved_16_63:48;
5104 #endif
5105 } s;
5106 struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
5107 struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
5108 struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx;
5109 struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx;
5110 struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1;
5111 struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx;
5112 struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx;
5113 struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1;
5114 struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx;
5115 };
5116
5117 union cvmx_gmxx_txx_cbfc_xon {
5118 uint64_t u64;
5119 struct cvmx_gmxx_txx_cbfc_xon_s {
5120 #ifdef __BIG_ENDIAN_BITFIELD
5121 uint64_t reserved_16_63:48;
5122 uint64_t xon:16;
5123 #else
5124 uint64_t xon:16;
5125 uint64_t reserved_16_63:48;
5126 #endif
5127 } s;
5128 struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
5129 struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
5130 struct cvmx_gmxx_txx_cbfc_xon_s cn61xx;
5131 struct cvmx_gmxx_txx_cbfc_xon_s cn63xx;
5132 struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1;
5133 struct cvmx_gmxx_txx_cbfc_xon_s cn66xx;
5134 struct cvmx_gmxx_txx_cbfc_xon_s cn68xx;
5135 struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1;
5136 struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx;
5137 };
5138
5139 union cvmx_gmxx_txx_clk {
5140 uint64_t u64;
5141 struct cvmx_gmxx_txx_clk_s {
5142 #ifdef __BIG_ENDIAN_BITFIELD
5143 uint64_t reserved_6_63:58;
5144 uint64_t clk_cnt:6;
5145 #else
5146 uint64_t clk_cnt:6;
5147 uint64_t reserved_6_63:58;
5148 #endif
5149 } s;
5150 struct cvmx_gmxx_txx_clk_s cn30xx;
5151 struct cvmx_gmxx_txx_clk_s cn31xx;
5152 struct cvmx_gmxx_txx_clk_s cn38xx;
5153 struct cvmx_gmxx_txx_clk_s cn38xxp2;
5154 struct cvmx_gmxx_txx_clk_s cn50xx;
5155 struct cvmx_gmxx_txx_clk_s cn58xx;
5156 struct cvmx_gmxx_txx_clk_s cn58xxp1;
5157 };
5158
5159 union cvmx_gmxx_txx_ctl {
5160 uint64_t u64;
5161 struct cvmx_gmxx_txx_ctl_s {
5162 #ifdef __BIG_ENDIAN_BITFIELD
5163 uint64_t reserved_2_63:62;
5164 uint64_t xsdef_en:1;
5165 uint64_t xscol_en:1;
5166 #else
5167 uint64_t xscol_en:1;
5168 uint64_t xsdef_en:1;
5169 uint64_t reserved_2_63:62;
5170 #endif
5171 } s;
5172 struct cvmx_gmxx_txx_ctl_s cn30xx;
5173 struct cvmx_gmxx_txx_ctl_s cn31xx;
5174 struct cvmx_gmxx_txx_ctl_s cn38xx;
5175 struct cvmx_gmxx_txx_ctl_s cn38xxp2;
5176 struct cvmx_gmxx_txx_ctl_s cn50xx;
5177 struct cvmx_gmxx_txx_ctl_s cn52xx;
5178 struct cvmx_gmxx_txx_ctl_s cn52xxp1;
5179 struct cvmx_gmxx_txx_ctl_s cn56xx;
5180 struct cvmx_gmxx_txx_ctl_s cn56xxp1;
5181 struct cvmx_gmxx_txx_ctl_s cn58xx;
5182 struct cvmx_gmxx_txx_ctl_s cn58xxp1;
5183 struct cvmx_gmxx_txx_ctl_s cn61xx;
5184 struct cvmx_gmxx_txx_ctl_s cn63xx;
5185 struct cvmx_gmxx_txx_ctl_s cn63xxp1;
5186 struct cvmx_gmxx_txx_ctl_s cn66xx;
5187 struct cvmx_gmxx_txx_ctl_s cn68xx;
5188 struct cvmx_gmxx_txx_ctl_s cn68xxp1;
5189 struct cvmx_gmxx_txx_ctl_s cnf71xx;
5190 };
5191
5192 union cvmx_gmxx_txx_min_pkt {
5193 uint64_t u64;
5194 struct cvmx_gmxx_txx_min_pkt_s {
5195 #ifdef __BIG_ENDIAN_BITFIELD
5196 uint64_t reserved_8_63:56;
5197 uint64_t min_size:8;
5198 #else
5199 uint64_t min_size:8;
5200 uint64_t reserved_8_63:56;
5201 #endif
5202 } s;
5203 struct cvmx_gmxx_txx_min_pkt_s cn30xx;
5204 struct cvmx_gmxx_txx_min_pkt_s cn31xx;
5205 struct cvmx_gmxx_txx_min_pkt_s cn38xx;
5206 struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
5207 struct cvmx_gmxx_txx_min_pkt_s cn50xx;
5208 struct cvmx_gmxx_txx_min_pkt_s cn52xx;
5209 struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
5210 struct cvmx_gmxx_txx_min_pkt_s cn56xx;
5211 struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
5212 struct cvmx_gmxx_txx_min_pkt_s cn58xx;
5213 struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
5214 struct cvmx_gmxx_txx_min_pkt_s cn61xx;
5215 struct cvmx_gmxx_txx_min_pkt_s cn63xx;
5216 struct cvmx_gmxx_txx_min_pkt_s cn63xxp1;
5217 struct cvmx_gmxx_txx_min_pkt_s cn66xx;
5218 struct cvmx_gmxx_txx_min_pkt_s cn68xx;
5219 struct cvmx_gmxx_txx_min_pkt_s cn68xxp1;
5220 struct cvmx_gmxx_txx_min_pkt_s cnf71xx;
5221 };
5222
5223 union cvmx_gmxx_txx_pause_pkt_interval {
5224 uint64_t u64;
5225 struct cvmx_gmxx_txx_pause_pkt_interval_s {
5226 #ifdef __BIG_ENDIAN_BITFIELD
5227 uint64_t reserved_16_63:48;
5228 uint64_t interval:16;
5229 #else
5230 uint64_t interval:16;
5231 uint64_t reserved_16_63:48;
5232 #endif
5233 } s;
5234 struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
5235 struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
5236 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
5237 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
5238 struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
5239 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
5240 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
5241 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
5242 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
5243 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
5244 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
5245 struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;
5246 struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
5247 struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
5248 struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;
5249 struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;
5250 struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;
5251 struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;
5252 };
5253
5254 union cvmx_gmxx_txx_pause_pkt_time {
5255 uint64_t u64;
5256 struct cvmx_gmxx_txx_pause_pkt_time_s {
5257 #ifdef __BIG_ENDIAN_BITFIELD
5258 uint64_t reserved_16_63:48;
5259 uint64_t time:16;
5260 #else
5261 uint64_t time:16;
5262 uint64_t reserved_16_63:48;
5263 #endif
5264 } s;
5265 struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
5266 struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
5267 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
5268 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
5269 struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
5270 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
5271 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
5272 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
5273 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
5274 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
5275 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
5276 struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;
5277 struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
5278 struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
5279 struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;
5280 struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;
5281 struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;
5282 struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;
5283 };
5284
5285 union cvmx_gmxx_txx_pause_togo {
5286 uint64_t u64;
5287 struct cvmx_gmxx_txx_pause_togo_s {
5288 #ifdef __BIG_ENDIAN_BITFIELD
5289 uint64_t reserved_32_63:32;
5290 uint64_t msg_time:16;
5291 uint64_t time:16;
5292 #else
5293 uint64_t time:16;
5294 uint64_t msg_time:16;
5295 uint64_t reserved_32_63:32;
5296 #endif
5297 } s;
5298 struct cvmx_gmxx_txx_pause_togo_cn30xx {
5299 #ifdef __BIG_ENDIAN_BITFIELD
5300 uint64_t reserved_16_63:48;
5301 uint64_t time:16;
5302 #else
5303 uint64_t time:16;
5304 uint64_t reserved_16_63:48;
5305 #endif
5306 } cn30xx;
5307 struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
5308 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
5309 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
5310 struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
5311 struct cvmx_gmxx_txx_pause_togo_s cn52xx;
5312 struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
5313 struct cvmx_gmxx_txx_pause_togo_s cn56xx;
5314 struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
5315 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
5316 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
5317 struct cvmx_gmxx_txx_pause_togo_s cn61xx;
5318 struct cvmx_gmxx_txx_pause_togo_s cn63xx;
5319 struct cvmx_gmxx_txx_pause_togo_s cn63xxp1;
5320 struct cvmx_gmxx_txx_pause_togo_s cn66xx;
5321 struct cvmx_gmxx_txx_pause_togo_s cn68xx;
5322 struct cvmx_gmxx_txx_pause_togo_s cn68xxp1;
5323 struct cvmx_gmxx_txx_pause_togo_s cnf71xx;
5324 };
5325
5326 union cvmx_gmxx_txx_pause_zero {
5327 uint64_t u64;
5328 struct cvmx_gmxx_txx_pause_zero_s {
5329 #ifdef __BIG_ENDIAN_BITFIELD
5330 uint64_t reserved_1_63:63;
5331 uint64_t send:1;
5332 #else
5333 uint64_t send:1;
5334 uint64_t reserved_1_63:63;
5335 #endif
5336 } s;
5337 struct cvmx_gmxx_txx_pause_zero_s cn30xx;
5338 struct cvmx_gmxx_txx_pause_zero_s cn31xx;
5339 struct cvmx_gmxx_txx_pause_zero_s cn38xx;
5340 struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
5341 struct cvmx_gmxx_txx_pause_zero_s cn50xx;
5342 struct cvmx_gmxx_txx_pause_zero_s cn52xx;
5343 struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
5344 struct cvmx_gmxx_txx_pause_zero_s cn56xx;
5345 struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
5346 struct cvmx_gmxx_txx_pause_zero_s cn58xx;
5347 struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
5348 struct cvmx_gmxx_txx_pause_zero_s cn61xx;
5349 struct cvmx_gmxx_txx_pause_zero_s cn63xx;
5350 struct cvmx_gmxx_txx_pause_zero_s cn63xxp1;
5351 struct cvmx_gmxx_txx_pause_zero_s cn66xx;
5352 struct cvmx_gmxx_txx_pause_zero_s cn68xx;
5353 struct cvmx_gmxx_txx_pause_zero_s cn68xxp1;
5354 struct cvmx_gmxx_txx_pause_zero_s cnf71xx;
5355 };
5356
5357 union cvmx_gmxx_txx_pipe {
5358 uint64_t u64;
5359 struct cvmx_gmxx_txx_pipe_s {
5360 #ifdef __BIG_ENDIAN_BITFIELD
5361 uint64_t reserved_33_63:31;
5362 uint64_t ign_bp:1;
5363 uint64_t reserved_21_31:11;
5364 uint64_t nump:5;
5365 uint64_t reserved_7_15:9;
5366 uint64_t base:7;
5367 #else
5368 uint64_t base:7;
5369 uint64_t reserved_7_15:9;
5370 uint64_t nump:5;
5371 uint64_t reserved_21_31:11;
5372 uint64_t ign_bp:1;
5373 uint64_t reserved_33_63:31;
5374 #endif
5375 } s;
5376 struct cvmx_gmxx_txx_pipe_s cn68xx;
5377 struct cvmx_gmxx_txx_pipe_s cn68xxp1;
5378 };
5379
5380 union cvmx_gmxx_txx_sgmii_ctl {
5381 uint64_t u64;
5382 struct cvmx_gmxx_txx_sgmii_ctl_s {
5383 #ifdef __BIG_ENDIAN_BITFIELD
5384 uint64_t reserved_1_63:63;
5385 uint64_t align:1;
5386 #else
5387 uint64_t align:1;
5388 uint64_t reserved_1_63:63;
5389 #endif
5390 } s;
5391 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
5392 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
5393 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
5394 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
5395 struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx;
5396 struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx;
5397 struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1;
5398 struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx;
5399 struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx;
5400 struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1;
5401 struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx;
5402 };
5403
5404 union cvmx_gmxx_txx_slot {
5405 uint64_t u64;
5406 struct cvmx_gmxx_txx_slot_s {
5407 #ifdef __BIG_ENDIAN_BITFIELD
5408 uint64_t reserved_10_63:54;
5409 uint64_t slot:10;
5410 #else
5411 uint64_t slot:10;
5412 uint64_t reserved_10_63:54;
5413 #endif
5414 } s;
5415 struct cvmx_gmxx_txx_slot_s cn30xx;
5416 struct cvmx_gmxx_txx_slot_s cn31xx;
5417 struct cvmx_gmxx_txx_slot_s cn38xx;
5418 struct cvmx_gmxx_txx_slot_s cn38xxp2;
5419 struct cvmx_gmxx_txx_slot_s cn50xx;
5420 struct cvmx_gmxx_txx_slot_s cn52xx;
5421 struct cvmx_gmxx_txx_slot_s cn52xxp1;
5422 struct cvmx_gmxx_txx_slot_s cn56xx;
5423 struct cvmx_gmxx_txx_slot_s cn56xxp1;
5424 struct cvmx_gmxx_txx_slot_s cn58xx;
5425 struct cvmx_gmxx_txx_slot_s cn58xxp1;
5426 struct cvmx_gmxx_txx_slot_s cn61xx;
5427 struct cvmx_gmxx_txx_slot_s cn63xx;
5428 struct cvmx_gmxx_txx_slot_s cn63xxp1;
5429 struct cvmx_gmxx_txx_slot_s cn66xx;
5430 struct cvmx_gmxx_txx_slot_s cn68xx;
5431 struct cvmx_gmxx_txx_slot_s cn68xxp1;
5432 struct cvmx_gmxx_txx_slot_s cnf71xx;
5433 };
5434
5435 union cvmx_gmxx_txx_soft_pause {
5436 uint64_t u64;
5437 struct cvmx_gmxx_txx_soft_pause_s {
5438 #ifdef __BIG_ENDIAN_BITFIELD
5439 uint64_t reserved_16_63:48;
5440 uint64_t time:16;
5441 #else
5442 uint64_t time:16;
5443 uint64_t reserved_16_63:48;
5444 #endif
5445 } s;
5446 struct cvmx_gmxx_txx_soft_pause_s cn30xx;
5447 struct cvmx_gmxx_txx_soft_pause_s cn31xx;
5448 struct cvmx_gmxx_txx_soft_pause_s cn38xx;
5449 struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
5450 struct cvmx_gmxx_txx_soft_pause_s cn50xx;
5451 struct cvmx_gmxx_txx_soft_pause_s cn52xx;
5452 struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
5453 struct cvmx_gmxx_txx_soft_pause_s cn56xx;
5454 struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
5455 struct cvmx_gmxx_txx_soft_pause_s cn58xx;
5456 struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
5457 struct cvmx_gmxx_txx_soft_pause_s cn61xx;
5458 struct cvmx_gmxx_txx_soft_pause_s cn63xx;
5459 struct cvmx_gmxx_txx_soft_pause_s cn63xxp1;
5460 struct cvmx_gmxx_txx_soft_pause_s cn66xx;
5461 struct cvmx_gmxx_txx_soft_pause_s cn68xx;
5462 struct cvmx_gmxx_txx_soft_pause_s cn68xxp1;
5463 struct cvmx_gmxx_txx_soft_pause_s cnf71xx;
5464 };
5465
5466 union cvmx_gmxx_txx_stat0 {
5467 uint64_t u64;
5468 struct cvmx_gmxx_txx_stat0_s {
5469 #ifdef __BIG_ENDIAN_BITFIELD
5470 uint64_t xsdef:32;
5471 uint64_t xscol:32;
5472 #else
5473 uint64_t xscol:32;
5474 uint64_t xsdef:32;
5475 #endif
5476 } s;
5477 struct cvmx_gmxx_txx_stat0_s cn30xx;
5478 struct cvmx_gmxx_txx_stat0_s cn31xx;
5479 struct cvmx_gmxx_txx_stat0_s cn38xx;
5480 struct cvmx_gmxx_txx_stat0_s cn38xxp2;
5481 struct cvmx_gmxx_txx_stat0_s cn50xx;
5482 struct cvmx_gmxx_txx_stat0_s cn52xx;
5483 struct cvmx_gmxx_txx_stat0_s cn52xxp1;
5484 struct cvmx_gmxx_txx_stat0_s cn56xx;
5485 struct cvmx_gmxx_txx_stat0_s cn56xxp1;
5486 struct cvmx_gmxx_txx_stat0_s cn58xx;
5487 struct cvmx_gmxx_txx_stat0_s cn58xxp1;
5488 struct cvmx_gmxx_txx_stat0_s cn61xx;
5489 struct cvmx_gmxx_txx_stat0_s cn63xx;
5490 struct cvmx_gmxx_txx_stat0_s cn63xxp1;
5491 struct cvmx_gmxx_txx_stat0_s cn66xx;
5492 struct cvmx_gmxx_txx_stat0_s cn68xx;
5493 struct cvmx_gmxx_txx_stat0_s cn68xxp1;
5494 struct cvmx_gmxx_txx_stat0_s cnf71xx;
5495 };
5496
5497 union cvmx_gmxx_txx_stat1 {
5498 uint64_t u64;
5499 struct cvmx_gmxx_txx_stat1_s {
5500 #ifdef __BIG_ENDIAN_BITFIELD
5501 uint64_t scol:32;
5502 uint64_t mcol:32;
5503 #else
5504 uint64_t mcol:32;
5505 uint64_t scol:32;
5506 #endif
5507 } s;
5508 struct cvmx_gmxx_txx_stat1_s cn30xx;
5509 struct cvmx_gmxx_txx_stat1_s cn31xx;
5510 struct cvmx_gmxx_txx_stat1_s cn38xx;
5511 struct cvmx_gmxx_txx_stat1_s cn38xxp2;
5512 struct cvmx_gmxx_txx_stat1_s cn50xx;
5513 struct cvmx_gmxx_txx_stat1_s cn52xx;
5514 struct cvmx_gmxx_txx_stat1_s cn52xxp1;
5515 struct cvmx_gmxx_txx_stat1_s cn56xx;
5516 struct cvmx_gmxx_txx_stat1_s cn56xxp1;
5517 struct cvmx_gmxx_txx_stat1_s cn58xx;
5518 struct cvmx_gmxx_txx_stat1_s cn58xxp1;
5519 struct cvmx_gmxx_txx_stat1_s cn61xx;
5520 struct cvmx_gmxx_txx_stat1_s cn63xx;
5521 struct cvmx_gmxx_txx_stat1_s cn63xxp1;
5522 struct cvmx_gmxx_txx_stat1_s cn66xx;
5523 struct cvmx_gmxx_txx_stat1_s cn68xx;
5524 struct cvmx_gmxx_txx_stat1_s cn68xxp1;
5525 struct cvmx_gmxx_txx_stat1_s cnf71xx;
5526 };
5527
5528 union cvmx_gmxx_txx_stat2 {
5529 uint64_t u64;
5530 struct cvmx_gmxx_txx_stat2_s {
5531 #ifdef __BIG_ENDIAN_BITFIELD
5532 uint64_t reserved_48_63:16;
5533 uint64_t octs:48;
5534 #else
5535 uint64_t octs:48;
5536 uint64_t reserved_48_63:16;
5537 #endif
5538 } s;
5539 struct cvmx_gmxx_txx_stat2_s cn30xx;
5540 struct cvmx_gmxx_txx_stat2_s cn31xx;
5541 struct cvmx_gmxx_txx_stat2_s cn38xx;
5542 struct cvmx_gmxx_txx_stat2_s cn38xxp2;
5543 struct cvmx_gmxx_txx_stat2_s cn50xx;
5544 struct cvmx_gmxx_txx_stat2_s cn52xx;
5545 struct cvmx_gmxx_txx_stat2_s cn52xxp1;
5546 struct cvmx_gmxx_txx_stat2_s cn56xx;
5547 struct cvmx_gmxx_txx_stat2_s cn56xxp1;
5548 struct cvmx_gmxx_txx_stat2_s cn58xx;
5549 struct cvmx_gmxx_txx_stat2_s cn58xxp1;
5550 struct cvmx_gmxx_txx_stat2_s cn61xx;
5551 struct cvmx_gmxx_txx_stat2_s cn63xx;
5552 struct cvmx_gmxx_txx_stat2_s cn63xxp1;
5553 struct cvmx_gmxx_txx_stat2_s cn66xx;
5554 struct cvmx_gmxx_txx_stat2_s cn68xx;
5555 struct cvmx_gmxx_txx_stat2_s cn68xxp1;
5556 struct cvmx_gmxx_txx_stat2_s cnf71xx;
5557 };
5558
5559 union cvmx_gmxx_txx_stat3 {
5560 uint64_t u64;
5561 struct cvmx_gmxx_txx_stat3_s {
5562 #ifdef __BIG_ENDIAN_BITFIELD
5563 uint64_t reserved_32_63:32;
5564 uint64_t pkts:32;
5565 #else
5566 uint64_t pkts:32;
5567 uint64_t reserved_32_63:32;
5568 #endif
5569 } s;
5570 struct cvmx_gmxx_txx_stat3_s cn30xx;
5571 struct cvmx_gmxx_txx_stat3_s cn31xx;
5572 struct cvmx_gmxx_txx_stat3_s cn38xx;
5573 struct cvmx_gmxx_txx_stat3_s cn38xxp2;
5574 struct cvmx_gmxx_txx_stat3_s cn50xx;
5575 struct cvmx_gmxx_txx_stat3_s cn52xx;
5576 struct cvmx_gmxx_txx_stat3_s cn52xxp1;
5577 struct cvmx_gmxx_txx_stat3_s cn56xx;
5578 struct cvmx_gmxx_txx_stat3_s cn56xxp1;
5579 struct cvmx_gmxx_txx_stat3_s cn58xx;
5580 struct cvmx_gmxx_txx_stat3_s cn58xxp1;
5581 struct cvmx_gmxx_txx_stat3_s cn61xx;
5582 struct cvmx_gmxx_txx_stat3_s cn63xx;
5583 struct cvmx_gmxx_txx_stat3_s cn63xxp1;
5584 struct cvmx_gmxx_txx_stat3_s cn66xx;
5585 struct cvmx_gmxx_txx_stat3_s cn68xx;
5586 struct cvmx_gmxx_txx_stat3_s cn68xxp1;
5587 struct cvmx_gmxx_txx_stat3_s cnf71xx;
5588 };
5589
5590 union cvmx_gmxx_txx_stat4 {
5591 uint64_t u64;
5592 struct cvmx_gmxx_txx_stat4_s {
5593 #ifdef __BIG_ENDIAN_BITFIELD
5594 uint64_t hist1:32;
5595 uint64_t hist0:32;
5596 #else
5597 uint64_t hist0:32;
5598 uint64_t hist1:32;
5599 #endif
5600 } s;
5601 struct cvmx_gmxx_txx_stat4_s cn30xx;
5602 struct cvmx_gmxx_txx_stat4_s cn31xx;
5603 struct cvmx_gmxx_txx_stat4_s cn38xx;
5604 struct cvmx_gmxx_txx_stat4_s cn38xxp2;
5605 struct cvmx_gmxx_txx_stat4_s cn50xx;
5606 struct cvmx_gmxx_txx_stat4_s cn52xx;
5607 struct cvmx_gmxx_txx_stat4_s cn52xxp1;
5608 struct cvmx_gmxx_txx_stat4_s cn56xx;
5609 struct cvmx_gmxx_txx_stat4_s cn56xxp1;
5610 struct cvmx_gmxx_txx_stat4_s cn58xx;
5611 struct cvmx_gmxx_txx_stat4_s cn58xxp1;
5612 struct cvmx_gmxx_txx_stat4_s cn61xx;
5613 struct cvmx_gmxx_txx_stat4_s cn63xx;
5614 struct cvmx_gmxx_txx_stat4_s cn63xxp1;
5615 struct cvmx_gmxx_txx_stat4_s cn66xx;
5616 struct cvmx_gmxx_txx_stat4_s cn68xx;
5617 struct cvmx_gmxx_txx_stat4_s cn68xxp1;
5618 struct cvmx_gmxx_txx_stat4_s cnf71xx;
5619 };
5620
5621 union cvmx_gmxx_txx_stat5 {
5622 uint64_t u64;
5623 struct cvmx_gmxx_txx_stat5_s {
5624 #ifdef __BIG_ENDIAN_BITFIELD
5625 uint64_t hist3:32;
5626 uint64_t hist2:32;
5627 #else
5628 uint64_t hist2:32;
5629 uint64_t hist3:32;
5630 #endif
5631 } s;
5632 struct cvmx_gmxx_txx_stat5_s cn30xx;
5633 struct cvmx_gmxx_txx_stat5_s cn31xx;
5634 struct cvmx_gmxx_txx_stat5_s cn38xx;
5635 struct cvmx_gmxx_txx_stat5_s cn38xxp2;
5636 struct cvmx_gmxx_txx_stat5_s cn50xx;
5637 struct cvmx_gmxx_txx_stat5_s cn52xx;
5638 struct cvmx_gmxx_txx_stat5_s cn52xxp1;
5639 struct cvmx_gmxx_txx_stat5_s cn56xx;
5640 struct cvmx_gmxx_txx_stat5_s cn56xxp1;
5641 struct cvmx_gmxx_txx_stat5_s cn58xx;
5642 struct cvmx_gmxx_txx_stat5_s cn58xxp1;
5643 struct cvmx_gmxx_txx_stat5_s cn61xx;
5644 struct cvmx_gmxx_txx_stat5_s cn63xx;
5645 struct cvmx_gmxx_txx_stat5_s cn63xxp1;
5646 struct cvmx_gmxx_txx_stat5_s cn66xx;
5647 struct cvmx_gmxx_txx_stat5_s cn68xx;
5648 struct cvmx_gmxx_txx_stat5_s cn68xxp1;
5649 struct cvmx_gmxx_txx_stat5_s cnf71xx;
5650 };
5651
5652 union cvmx_gmxx_txx_stat6 {
5653 uint64_t u64;
5654 struct cvmx_gmxx_txx_stat6_s {
5655 #ifdef __BIG_ENDIAN_BITFIELD
5656 uint64_t hist5:32;
5657 uint64_t hist4:32;
5658 #else
5659 uint64_t hist4:32;
5660 uint64_t hist5:32;
5661 #endif
5662 } s;
5663 struct cvmx_gmxx_txx_stat6_s cn30xx;
5664 struct cvmx_gmxx_txx_stat6_s cn31xx;
5665 struct cvmx_gmxx_txx_stat6_s cn38xx;
5666 struct cvmx_gmxx_txx_stat6_s cn38xxp2;
5667 struct cvmx_gmxx_txx_stat6_s cn50xx;
5668 struct cvmx_gmxx_txx_stat6_s cn52xx;
5669 struct cvmx_gmxx_txx_stat6_s cn52xxp1;
5670 struct cvmx_gmxx_txx_stat6_s cn56xx;
5671 struct cvmx_gmxx_txx_stat6_s cn56xxp1;
5672 struct cvmx_gmxx_txx_stat6_s cn58xx;
5673 struct cvmx_gmxx_txx_stat6_s cn58xxp1;
5674 struct cvmx_gmxx_txx_stat6_s cn61xx;
5675 struct cvmx_gmxx_txx_stat6_s cn63xx;
5676 struct cvmx_gmxx_txx_stat6_s cn63xxp1;
5677 struct cvmx_gmxx_txx_stat6_s cn66xx;
5678 struct cvmx_gmxx_txx_stat6_s cn68xx;
5679 struct cvmx_gmxx_txx_stat6_s cn68xxp1;
5680 struct cvmx_gmxx_txx_stat6_s cnf71xx;
5681 };
5682
5683 union cvmx_gmxx_txx_stat7 {
5684 uint64_t u64;
5685 struct cvmx_gmxx_txx_stat7_s {
5686 #ifdef __BIG_ENDIAN_BITFIELD
5687 uint64_t hist7:32;
5688 uint64_t hist6:32;
5689 #else
5690 uint64_t hist6:32;
5691 uint64_t hist7:32;
5692 #endif
5693 } s;
5694 struct cvmx_gmxx_txx_stat7_s cn30xx;
5695 struct cvmx_gmxx_txx_stat7_s cn31xx;
5696 struct cvmx_gmxx_txx_stat7_s cn38xx;
5697 struct cvmx_gmxx_txx_stat7_s cn38xxp2;
5698 struct cvmx_gmxx_txx_stat7_s cn50xx;
5699 struct cvmx_gmxx_txx_stat7_s cn52xx;
5700 struct cvmx_gmxx_txx_stat7_s cn52xxp1;
5701 struct cvmx_gmxx_txx_stat7_s cn56xx;
5702 struct cvmx_gmxx_txx_stat7_s cn56xxp1;
5703 struct cvmx_gmxx_txx_stat7_s cn58xx;
5704 struct cvmx_gmxx_txx_stat7_s cn58xxp1;
5705 struct cvmx_gmxx_txx_stat7_s cn61xx;
5706 struct cvmx_gmxx_txx_stat7_s cn63xx;
5707 struct cvmx_gmxx_txx_stat7_s cn63xxp1;
5708 struct cvmx_gmxx_txx_stat7_s cn66xx;
5709 struct cvmx_gmxx_txx_stat7_s cn68xx;
5710 struct cvmx_gmxx_txx_stat7_s cn68xxp1;
5711 struct cvmx_gmxx_txx_stat7_s cnf71xx;
5712 };
5713
5714 union cvmx_gmxx_txx_stat8 {
5715 uint64_t u64;
5716 struct cvmx_gmxx_txx_stat8_s {
5717 #ifdef __BIG_ENDIAN_BITFIELD
5718 uint64_t mcst:32;
5719 uint64_t bcst:32;
5720 #else
5721 uint64_t bcst:32;
5722 uint64_t mcst:32;
5723 #endif
5724 } s;
5725 struct cvmx_gmxx_txx_stat8_s cn30xx;
5726 struct cvmx_gmxx_txx_stat8_s cn31xx;
5727 struct cvmx_gmxx_txx_stat8_s cn38xx;
5728 struct cvmx_gmxx_txx_stat8_s cn38xxp2;
5729 struct cvmx_gmxx_txx_stat8_s cn50xx;
5730 struct cvmx_gmxx_txx_stat8_s cn52xx;
5731 struct cvmx_gmxx_txx_stat8_s cn52xxp1;
5732 struct cvmx_gmxx_txx_stat8_s cn56xx;
5733 struct cvmx_gmxx_txx_stat8_s cn56xxp1;
5734 struct cvmx_gmxx_txx_stat8_s cn58xx;
5735 struct cvmx_gmxx_txx_stat8_s cn58xxp1;
5736 struct cvmx_gmxx_txx_stat8_s cn61xx;
5737 struct cvmx_gmxx_txx_stat8_s cn63xx;
5738 struct cvmx_gmxx_txx_stat8_s cn63xxp1;
5739 struct cvmx_gmxx_txx_stat8_s cn66xx;
5740 struct cvmx_gmxx_txx_stat8_s cn68xx;
5741 struct cvmx_gmxx_txx_stat8_s cn68xxp1;
5742 struct cvmx_gmxx_txx_stat8_s cnf71xx;
5743 };
5744
5745 union cvmx_gmxx_txx_stat9 {
5746 uint64_t u64;
5747 struct cvmx_gmxx_txx_stat9_s {
5748 #ifdef __BIG_ENDIAN_BITFIELD
5749 uint64_t undflw:32;
5750 uint64_t ctl:32;
5751 #else
5752 uint64_t ctl:32;
5753 uint64_t undflw:32;
5754 #endif
5755 } s;
5756 struct cvmx_gmxx_txx_stat9_s cn30xx;
5757 struct cvmx_gmxx_txx_stat9_s cn31xx;
5758 struct cvmx_gmxx_txx_stat9_s cn38xx;
5759 struct cvmx_gmxx_txx_stat9_s cn38xxp2;
5760 struct cvmx_gmxx_txx_stat9_s cn50xx;
5761 struct cvmx_gmxx_txx_stat9_s cn52xx;
5762 struct cvmx_gmxx_txx_stat9_s cn52xxp1;
5763 struct cvmx_gmxx_txx_stat9_s cn56xx;
5764 struct cvmx_gmxx_txx_stat9_s cn56xxp1;
5765 struct cvmx_gmxx_txx_stat9_s cn58xx;
5766 struct cvmx_gmxx_txx_stat9_s cn58xxp1;
5767 struct cvmx_gmxx_txx_stat9_s cn61xx;
5768 struct cvmx_gmxx_txx_stat9_s cn63xx;
5769 struct cvmx_gmxx_txx_stat9_s cn63xxp1;
5770 struct cvmx_gmxx_txx_stat9_s cn66xx;
5771 struct cvmx_gmxx_txx_stat9_s cn68xx;
5772 struct cvmx_gmxx_txx_stat9_s cn68xxp1;
5773 struct cvmx_gmxx_txx_stat9_s cnf71xx;
5774 };
5775
5776 union cvmx_gmxx_txx_stats_ctl {
5777 uint64_t u64;
5778 struct cvmx_gmxx_txx_stats_ctl_s {
5779 #ifdef __BIG_ENDIAN_BITFIELD
5780 uint64_t reserved_1_63:63;
5781 uint64_t rd_clr:1;
5782 #else
5783 uint64_t rd_clr:1;
5784 uint64_t reserved_1_63:63;
5785 #endif
5786 } s;
5787 struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
5788 struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
5789 struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
5790 struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
5791 struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
5792 struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
5793 struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
5794 struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
5795 struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
5796 struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
5797 struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
5798 struct cvmx_gmxx_txx_stats_ctl_s cn61xx;
5799 struct cvmx_gmxx_txx_stats_ctl_s cn63xx;
5800 struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1;
5801 struct cvmx_gmxx_txx_stats_ctl_s cn66xx;
5802 struct cvmx_gmxx_txx_stats_ctl_s cn68xx;
5803 struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1;
5804 struct cvmx_gmxx_txx_stats_ctl_s cnf71xx;
5805 };
5806
5807 union cvmx_gmxx_txx_thresh {
5808 uint64_t u64;
5809 struct cvmx_gmxx_txx_thresh_s {
5810 #ifdef __BIG_ENDIAN_BITFIELD
5811 uint64_t reserved_10_63:54;
5812 uint64_t cnt:10;
5813 #else
5814 uint64_t cnt:10;
5815 uint64_t reserved_10_63:54;
5816 #endif
5817 } s;
5818 struct cvmx_gmxx_txx_thresh_cn30xx {
5819 #ifdef __BIG_ENDIAN_BITFIELD
5820 uint64_t reserved_7_63:57;
5821 uint64_t cnt:7;
5822 #else
5823 uint64_t cnt:7;
5824 uint64_t reserved_7_63:57;
5825 #endif
5826 } cn30xx;
5827 struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
5828 struct cvmx_gmxx_txx_thresh_cn38xx {
5829 #ifdef __BIG_ENDIAN_BITFIELD
5830 uint64_t reserved_9_63:55;
5831 uint64_t cnt:9;
5832 #else
5833 uint64_t cnt:9;
5834 uint64_t reserved_9_63:55;
5835 #endif
5836 } cn38xx;
5837 struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2;
5838 struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
5839 struct cvmx_gmxx_txx_thresh_cn38xx cn52xx;
5840 struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1;
5841 struct cvmx_gmxx_txx_thresh_cn38xx cn56xx;
5842 struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1;
5843 struct cvmx_gmxx_txx_thresh_cn38xx cn58xx;
5844 struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1;
5845 struct cvmx_gmxx_txx_thresh_cn38xx cn61xx;
5846 struct cvmx_gmxx_txx_thresh_cn38xx cn63xx;
5847 struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1;
5848 struct cvmx_gmxx_txx_thresh_cn38xx cn66xx;
5849 struct cvmx_gmxx_txx_thresh_s cn68xx;
5850 struct cvmx_gmxx_txx_thresh_s cn68xxp1;
5851 struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx;
5852 };
5853
5854 union cvmx_gmxx_tx_bp {
5855 uint64_t u64;
5856 struct cvmx_gmxx_tx_bp_s {
5857 #ifdef __BIG_ENDIAN_BITFIELD
5858 uint64_t reserved_4_63:60;
5859 uint64_t bp:4;
5860 #else
5861 uint64_t bp:4;
5862 uint64_t reserved_4_63:60;
5863 #endif
5864 } s;
5865 struct cvmx_gmxx_tx_bp_cn30xx {
5866 #ifdef __BIG_ENDIAN_BITFIELD
5867 uint64_t reserved_3_63:61;
5868 uint64_t bp:3;
5869 #else
5870 uint64_t bp:3;
5871 uint64_t reserved_3_63:61;
5872 #endif
5873 } cn30xx;
5874 struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
5875 struct cvmx_gmxx_tx_bp_s cn38xx;
5876 struct cvmx_gmxx_tx_bp_s cn38xxp2;
5877 struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
5878 struct cvmx_gmxx_tx_bp_s cn52xx;
5879 struct cvmx_gmxx_tx_bp_s cn52xxp1;
5880 struct cvmx_gmxx_tx_bp_s cn56xx;
5881 struct cvmx_gmxx_tx_bp_s cn56xxp1;
5882 struct cvmx_gmxx_tx_bp_s cn58xx;
5883 struct cvmx_gmxx_tx_bp_s cn58xxp1;
5884 struct cvmx_gmxx_tx_bp_s cn61xx;
5885 struct cvmx_gmxx_tx_bp_s cn63xx;
5886 struct cvmx_gmxx_tx_bp_s cn63xxp1;
5887 struct cvmx_gmxx_tx_bp_s cn66xx;
5888 struct cvmx_gmxx_tx_bp_s cn68xx;
5889 struct cvmx_gmxx_tx_bp_s cn68xxp1;
5890 struct cvmx_gmxx_tx_bp_cnf71xx {
5891 #ifdef __BIG_ENDIAN_BITFIELD
5892 uint64_t reserved_2_63:62;
5893 uint64_t bp:2;
5894 #else
5895 uint64_t bp:2;
5896 uint64_t reserved_2_63:62;
5897 #endif
5898 } cnf71xx;
5899 };
5900
5901 union cvmx_gmxx_tx_clk_mskx {
5902 uint64_t u64;
5903 struct cvmx_gmxx_tx_clk_mskx_s {
5904 #ifdef __BIG_ENDIAN_BITFIELD
5905 uint64_t reserved_1_63:63;
5906 uint64_t msk:1;
5907 #else
5908 uint64_t msk:1;
5909 uint64_t reserved_1_63:63;
5910 #endif
5911 } s;
5912 struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
5913 struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
5914 };
5915
5916 union cvmx_gmxx_tx_col_attempt {
5917 uint64_t u64;
5918 struct cvmx_gmxx_tx_col_attempt_s {
5919 #ifdef __BIG_ENDIAN_BITFIELD
5920 uint64_t reserved_5_63:59;
5921 uint64_t limit:5;
5922 #else
5923 uint64_t limit:5;
5924 uint64_t reserved_5_63:59;
5925 #endif
5926 } s;
5927 struct cvmx_gmxx_tx_col_attempt_s cn30xx;
5928 struct cvmx_gmxx_tx_col_attempt_s cn31xx;
5929 struct cvmx_gmxx_tx_col_attempt_s cn38xx;
5930 struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
5931 struct cvmx_gmxx_tx_col_attempt_s cn50xx;
5932 struct cvmx_gmxx_tx_col_attempt_s cn52xx;
5933 struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
5934 struct cvmx_gmxx_tx_col_attempt_s cn56xx;
5935 struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
5936 struct cvmx_gmxx_tx_col_attempt_s cn58xx;
5937 struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
5938 struct cvmx_gmxx_tx_col_attempt_s cn61xx;
5939 struct cvmx_gmxx_tx_col_attempt_s cn63xx;
5940 struct cvmx_gmxx_tx_col_attempt_s cn63xxp1;
5941 struct cvmx_gmxx_tx_col_attempt_s cn66xx;
5942 struct cvmx_gmxx_tx_col_attempt_s cn68xx;
5943 struct cvmx_gmxx_tx_col_attempt_s cn68xxp1;
5944 struct cvmx_gmxx_tx_col_attempt_s cnf71xx;
5945 };
5946
5947 union cvmx_gmxx_tx_corrupt {
5948 uint64_t u64;
5949 struct cvmx_gmxx_tx_corrupt_s {
5950 #ifdef __BIG_ENDIAN_BITFIELD
5951 uint64_t reserved_4_63:60;
5952 uint64_t corrupt:4;
5953 #else
5954 uint64_t corrupt:4;
5955 uint64_t reserved_4_63:60;
5956 #endif
5957 } s;
5958 struct cvmx_gmxx_tx_corrupt_cn30xx {
5959 #ifdef __BIG_ENDIAN_BITFIELD
5960 uint64_t reserved_3_63:61;
5961 uint64_t corrupt:3;
5962 #else
5963 uint64_t corrupt:3;
5964 uint64_t reserved_3_63:61;
5965 #endif
5966 } cn30xx;
5967 struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
5968 struct cvmx_gmxx_tx_corrupt_s cn38xx;
5969 struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
5970 struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
5971 struct cvmx_gmxx_tx_corrupt_s cn52xx;
5972 struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
5973 struct cvmx_gmxx_tx_corrupt_s cn56xx;
5974 struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
5975 struct cvmx_gmxx_tx_corrupt_s cn58xx;
5976 struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
5977 struct cvmx_gmxx_tx_corrupt_s cn61xx;
5978 struct cvmx_gmxx_tx_corrupt_s cn63xx;
5979 struct cvmx_gmxx_tx_corrupt_s cn63xxp1;
5980 struct cvmx_gmxx_tx_corrupt_s cn66xx;
5981 struct cvmx_gmxx_tx_corrupt_s cn68xx;
5982 struct cvmx_gmxx_tx_corrupt_s cn68xxp1;
5983 struct cvmx_gmxx_tx_corrupt_cnf71xx {
5984 #ifdef __BIG_ENDIAN_BITFIELD
5985 uint64_t reserved_2_63:62;
5986 uint64_t corrupt:2;
5987 #else
5988 uint64_t corrupt:2;
5989 uint64_t reserved_2_63:62;
5990 #endif
5991 } cnf71xx;
5992 };
5993
5994 union cvmx_gmxx_tx_hg2_reg1 {
5995 uint64_t u64;
5996 struct cvmx_gmxx_tx_hg2_reg1_s {
5997 #ifdef __BIG_ENDIAN_BITFIELD
5998 uint64_t reserved_16_63:48;
5999 uint64_t tx_xof:16;
6000 #else
6001 uint64_t tx_xof:16;
6002 uint64_t reserved_16_63:48;
6003 #endif
6004 } s;
6005 struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
6006 struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
6007 struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
6008 struct cvmx_gmxx_tx_hg2_reg1_s cn61xx;
6009 struct cvmx_gmxx_tx_hg2_reg1_s cn63xx;
6010 struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1;
6011 struct cvmx_gmxx_tx_hg2_reg1_s cn66xx;
6012 struct cvmx_gmxx_tx_hg2_reg1_s cn68xx;
6013 struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1;
6014 struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx;
6015 };
6016
6017 union cvmx_gmxx_tx_hg2_reg2 {
6018 uint64_t u64;
6019 struct cvmx_gmxx_tx_hg2_reg2_s {
6020 #ifdef __BIG_ENDIAN_BITFIELD
6021 uint64_t reserved_16_63:48;
6022 uint64_t tx_xon:16;
6023 #else
6024 uint64_t tx_xon:16;
6025 uint64_t reserved_16_63:48;
6026 #endif
6027 } s;
6028 struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
6029 struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
6030 struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
6031 struct cvmx_gmxx_tx_hg2_reg2_s cn61xx;
6032 struct cvmx_gmxx_tx_hg2_reg2_s cn63xx;
6033 struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1;
6034 struct cvmx_gmxx_tx_hg2_reg2_s cn66xx;
6035 struct cvmx_gmxx_tx_hg2_reg2_s cn68xx;
6036 struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1;
6037 struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx;
6038 };
6039
6040 union cvmx_gmxx_tx_ifg {
6041 uint64_t u64;
6042 struct cvmx_gmxx_tx_ifg_s {
6043 #ifdef __BIG_ENDIAN_BITFIELD
6044 uint64_t reserved_8_63:56;
6045 uint64_t ifg2:4;
6046 uint64_t ifg1:4;
6047 #else
6048 uint64_t ifg1:4;
6049 uint64_t ifg2:4;
6050 uint64_t reserved_8_63:56;
6051 #endif
6052 } s;
6053 struct cvmx_gmxx_tx_ifg_s cn30xx;
6054 struct cvmx_gmxx_tx_ifg_s cn31xx;
6055 struct cvmx_gmxx_tx_ifg_s cn38xx;
6056 struct cvmx_gmxx_tx_ifg_s cn38xxp2;
6057 struct cvmx_gmxx_tx_ifg_s cn50xx;
6058 struct cvmx_gmxx_tx_ifg_s cn52xx;
6059 struct cvmx_gmxx_tx_ifg_s cn52xxp1;
6060 struct cvmx_gmxx_tx_ifg_s cn56xx;
6061 struct cvmx_gmxx_tx_ifg_s cn56xxp1;
6062 struct cvmx_gmxx_tx_ifg_s cn58xx;
6063 struct cvmx_gmxx_tx_ifg_s cn58xxp1;
6064 struct cvmx_gmxx_tx_ifg_s cn61xx;
6065 struct cvmx_gmxx_tx_ifg_s cn63xx;
6066 struct cvmx_gmxx_tx_ifg_s cn63xxp1;
6067 struct cvmx_gmxx_tx_ifg_s cn66xx;
6068 struct cvmx_gmxx_tx_ifg_s cn68xx;
6069 struct cvmx_gmxx_tx_ifg_s cn68xxp1;
6070 struct cvmx_gmxx_tx_ifg_s cnf71xx;
6071 };
6072
6073 union cvmx_gmxx_tx_int_en {
6074 uint64_t u64;
6075 struct cvmx_gmxx_tx_int_en_s {
6076 #ifdef __BIG_ENDIAN_BITFIELD
6077 uint64_t reserved_25_63:39;
6078 uint64_t xchange:1;
6079 uint64_t ptp_lost:4;
6080 uint64_t late_col:4;
6081 uint64_t xsdef:4;
6082 uint64_t xscol:4;
6083 uint64_t reserved_6_7:2;
6084 uint64_t undflw:4;
6085 uint64_t reserved_1_1:1;
6086 uint64_t pko_nxa:1;
6087 #else
6088 uint64_t pko_nxa:1;
6089 uint64_t reserved_1_1:1;
6090 uint64_t undflw:4;
6091 uint64_t reserved_6_7:2;
6092 uint64_t xscol:4;
6093 uint64_t xsdef:4;
6094 uint64_t late_col:4;
6095 uint64_t ptp_lost:4;
6096 uint64_t xchange:1;
6097 uint64_t reserved_25_63:39;
6098 #endif
6099 } s;
6100 struct cvmx_gmxx_tx_int_en_cn30xx {
6101 #ifdef __BIG_ENDIAN_BITFIELD
6102 uint64_t reserved_19_63:45;
6103 uint64_t late_col:3;
6104 uint64_t reserved_15_15:1;
6105 uint64_t xsdef:3;
6106 uint64_t reserved_11_11:1;
6107 uint64_t xscol:3;
6108 uint64_t reserved_5_7:3;
6109 uint64_t undflw:3;
6110 uint64_t reserved_1_1:1;
6111 uint64_t pko_nxa:1;
6112 #else
6113 uint64_t pko_nxa:1;
6114 uint64_t reserved_1_1:1;
6115 uint64_t undflw:3;
6116 uint64_t reserved_5_7:3;
6117 uint64_t xscol:3;
6118 uint64_t reserved_11_11:1;
6119 uint64_t xsdef:3;
6120 uint64_t reserved_15_15:1;
6121 uint64_t late_col:3;
6122 uint64_t reserved_19_63:45;
6123 #endif
6124 } cn30xx;
6125 struct cvmx_gmxx_tx_int_en_cn31xx {
6126 #ifdef __BIG_ENDIAN_BITFIELD
6127 uint64_t reserved_15_63:49;
6128 uint64_t xsdef:3;
6129 uint64_t reserved_11_11:1;
6130 uint64_t xscol:3;
6131 uint64_t reserved_5_7:3;
6132 uint64_t undflw:3;
6133 uint64_t reserved_1_1:1;
6134 uint64_t pko_nxa:1;
6135 #else
6136 uint64_t pko_nxa:1;
6137 uint64_t reserved_1_1:1;
6138 uint64_t undflw:3;
6139 uint64_t reserved_5_7:3;
6140 uint64_t xscol:3;
6141 uint64_t reserved_11_11:1;
6142 uint64_t xsdef:3;
6143 uint64_t reserved_15_63:49;
6144 #endif
6145 } cn31xx;
6146 struct cvmx_gmxx_tx_int_en_cn38xx {
6147 #ifdef __BIG_ENDIAN_BITFIELD
6148 uint64_t reserved_20_63:44;
6149 uint64_t late_col:4;
6150 uint64_t xsdef:4;
6151 uint64_t xscol:4;
6152 uint64_t reserved_6_7:2;
6153 uint64_t undflw:4;
6154 uint64_t ncb_nxa:1;
6155 uint64_t pko_nxa:1;
6156 #else
6157 uint64_t pko_nxa:1;
6158 uint64_t ncb_nxa:1;
6159 uint64_t undflw:4;
6160 uint64_t reserved_6_7:2;
6161 uint64_t xscol:4;
6162 uint64_t xsdef:4;
6163 uint64_t late_col:4;
6164 uint64_t reserved_20_63:44;
6165 #endif
6166 } cn38xx;
6167 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
6168 #ifdef __BIG_ENDIAN_BITFIELD
6169 uint64_t reserved_16_63:48;
6170 uint64_t xsdef:4;
6171 uint64_t xscol:4;
6172 uint64_t reserved_6_7:2;
6173 uint64_t undflw:4;
6174 uint64_t ncb_nxa:1;
6175 uint64_t pko_nxa:1;
6176 #else
6177 uint64_t pko_nxa:1;
6178 uint64_t ncb_nxa:1;
6179 uint64_t undflw:4;
6180 uint64_t reserved_6_7:2;
6181 uint64_t xscol:4;
6182 uint64_t xsdef:4;
6183 uint64_t reserved_16_63:48;
6184 #endif
6185 } cn38xxp2;
6186 struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
6187 struct cvmx_gmxx_tx_int_en_cn52xx {
6188 #ifdef __BIG_ENDIAN_BITFIELD
6189 uint64_t reserved_20_63:44;
6190 uint64_t late_col:4;
6191 uint64_t xsdef:4;
6192 uint64_t xscol:4;
6193 uint64_t reserved_6_7:2;
6194 uint64_t undflw:4;
6195 uint64_t reserved_1_1:1;
6196 uint64_t pko_nxa:1;
6197 #else
6198 uint64_t pko_nxa:1;
6199 uint64_t reserved_1_1:1;
6200 uint64_t undflw:4;
6201 uint64_t reserved_6_7:2;
6202 uint64_t xscol:4;
6203 uint64_t xsdef:4;
6204 uint64_t late_col:4;
6205 uint64_t reserved_20_63:44;
6206 #endif
6207 } cn52xx;
6208 struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
6209 struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
6210 struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
6211 struct cvmx_gmxx_tx_int_en_cn38xx cn58xx;
6212 struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1;
6213 struct cvmx_gmxx_tx_int_en_s cn61xx;
6214 struct cvmx_gmxx_tx_int_en_cn63xx {
6215 #ifdef __BIG_ENDIAN_BITFIELD
6216 uint64_t reserved_24_63:40;
6217 uint64_t ptp_lost:4;
6218 uint64_t late_col:4;
6219 uint64_t xsdef:4;
6220 uint64_t xscol:4;
6221 uint64_t reserved_6_7:2;
6222 uint64_t undflw:4;
6223 uint64_t reserved_1_1:1;
6224 uint64_t pko_nxa:1;
6225 #else
6226 uint64_t pko_nxa:1;
6227 uint64_t reserved_1_1:1;
6228 uint64_t undflw:4;
6229 uint64_t reserved_6_7:2;
6230 uint64_t xscol:4;
6231 uint64_t xsdef:4;
6232 uint64_t late_col:4;
6233 uint64_t ptp_lost:4;
6234 uint64_t reserved_24_63:40;
6235 #endif
6236 } cn63xx;
6237 struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1;
6238 struct cvmx_gmxx_tx_int_en_s cn66xx;
6239 struct cvmx_gmxx_tx_int_en_cn68xx {
6240 #ifdef __BIG_ENDIAN_BITFIELD
6241 uint64_t reserved_25_63:39;
6242 uint64_t xchange:1;
6243 uint64_t ptp_lost:4;
6244 uint64_t late_col:4;
6245 uint64_t xsdef:4;
6246 uint64_t xscol:4;
6247 uint64_t reserved_6_7:2;
6248 uint64_t undflw:4;
6249 uint64_t pko_nxp:1;
6250 uint64_t pko_nxa:1;
6251 #else
6252 uint64_t pko_nxa:1;
6253 uint64_t pko_nxp:1;
6254 uint64_t undflw:4;
6255 uint64_t reserved_6_7:2;
6256 uint64_t xscol:4;
6257 uint64_t xsdef:4;
6258 uint64_t late_col:4;
6259 uint64_t ptp_lost:4;
6260 uint64_t xchange:1;
6261 uint64_t reserved_25_63:39;
6262 #endif
6263 } cn68xx;
6264 struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1;
6265 struct cvmx_gmxx_tx_int_en_cnf71xx {
6266 #ifdef __BIG_ENDIAN_BITFIELD
6267 uint64_t reserved_25_63:39;
6268 uint64_t xchange:1;
6269 uint64_t reserved_22_23:2;
6270 uint64_t ptp_lost:2;
6271 uint64_t reserved_18_19:2;
6272 uint64_t late_col:2;
6273 uint64_t reserved_14_15:2;
6274 uint64_t xsdef:2;
6275 uint64_t reserved_10_11:2;
6276 uint64_t xscol:2;
6277 uint64_t reserved_4_7:4;
6278 uint64_t undflw:2;
6279 uint64_t reserved_1_1:1;
6280 uint64_t pko_nxa:1;
6281 #else
6282 uint64_t pko_nxa:1;
6283 uint64_t reserved_1_1:1;
6284 uint64_t undflw:2;
6285 uint64_t reserved_4_7:4;
6286 uint64_t xscol:2;
6287 uint64_t reserved_10_11:2;
6288 uint64_t xsdef:2;
6289 uint64_t reserved_14_15:2;
6290 uint64_t late_col:2;
6291 uint64_t reserved_18_19:2;
6292 uint64_t ptp_lost:2;
6293 uint64_t reserved_22_23:2;
6294 uint64_t xchange:1;
6295 uint64_t reserved_25_63:39;
6296 #endif
6297 } cnf71xx;
6298 };
6299
6300 union cvmx_gmxx_tx_int_reg {
6301 uint64_t u64;
6302 struct cvmx_gmxx_tx_int_reg_s {
6303 #ifdef __BIG_ENDIAN_BITFIELD
6304 uint64_t reserved_25_63:39;
6305 uint64_t xchange:1;
6306 uint64_t ptp_lost:4;
6307 uint64_t late_col:4;
6308 uint64_t xsdef:4;
6309 uint64_t xscol:4;
6310 uint64_t reserved_6_7:2;
6311 uint64_t undflw:4;
6312 uint64_t reserved_1_1:1;
6313 uint64_t pko_nxa:1;
6314 #else
6315 uint64_t pko_nxa:1;
6316 uint64_t reserved_1_1:1;
6317 uint64_t undflw:4;
6318 uint64_t reserved_6_7:2;
6319 uint64_t xscol:4;
6320 uint64_t xsdef:4;
6321 uint64_t late_col:4;
6322 uint64_t ptp_lost:4;
6323 uint64_t xchange:1;
6324 uint64_t reserved_25_63:39;
6325 #endif
6326 } s;
6327 struct cvmx_gmxx_tx_int_reg_cn30xx {
6328 #ifdef __BIG_ENDIAN_BITFIELD
6329 uint64_t reserved_19_63:45;
6330 uint64_t late_col:3;
6331 uint64_t reserved_15_15:1;
6332 uint64_t xsdef:3;
6333 uint64_t reserved_11_11:1;
6334 uint64_t xscol:3;
6335 uint64_t reserved_5_7:3;
6336 uint64_t undflw:3;
6337 uint64_t reserved_1_1:1;
6338 uint64_t pko_nxa:1;
6339 #else
6340 uint64_t pko_nxa:1;
6341 uint64_t reserved_1_1:1;
6342 uint64_t undflw:3;
6343 uint64_t reserved_5_7:3;
6344 uint64_t xscol:3;
6345 uint64_t reserved_11_11:1;
6346 uint64_t xsdef:3;
6347 uint64_t reserved_15_15:1;
6348 uint64_t late_col:3;
6349 uint64_t reserved_19_63:45;
6350 #endif
6351 } cn30xx;
6352 struct cvmx_gmxx_tx_int_reg_cn31xx {
6353 #ifdef __BIG_ENDIAN_BITFIELD
6354 uint64_t reserved_15_63:49;
6355 uint64_t xsdef:3;
6356 uint64_t reserved_11_11:1;
6357 uint64_t xscol:3;
6358 uint64_t reserved_5_7:3;
6359 uint64_t undflw:3;
6360 uint64_t reserved_1_1:1;
6361 uint64_t pko_nxa:1;
6362 #else
6363 uint64_t pko_nxa:1;
6364 uint64_t reserved_1_1:1;
6365 uint64_t undflw:3;
6366 uint64_t reserved_5_7:3;
6367 uint64_t xscol:3;
6368 uint64_t reserved_11_11:1;
6369 uint64_t xsdef:3;
6370 uint64_t reserved_15_63:49;
6371 #endif
6372 } cn31xx;
6373 struct cvmx_gmxx_tx_int_reg_cn38xx {
6374 #ifdef __BIG_ENDIAN_BITFIELD
6375 uint64_t reserved_20_63:44;
6376 uint64_t late_col:4;
6377 uint64_t xsdef:4;
6378 uint64_t xscol:4;
6379 uint64_t reserved_6_7:2;
6380 uint64_t undflw:4;
6381 uint64_t ncb_nxa:1;
6382 uint64_t pko_nxa:1;
6383 #else
6384 uint64_t pko_nxa:1;
6385 uint64_t ncb_nxa:1;
6386 uint64_t undflw:4;
6387 uint64_t reserved_6_7:2;
6388 uint64_t xscol:4;
6389 uint64_t xsdef:4;
6390 uint64_t late_col:4;
6391 uint64_t reserved_20_63:44;
6392 #endif
6393 } cn38xx;
6394 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
6395 #ifdef __BIG_ENDIAN_BITFIELD
6396 uint64_t reserved_16_63:48;
6397 uint64_t xsdef:4;
6398 uint64_t xscol:4;
6399 uint64_t reserved_6_7:2;
6400 uint64_t undflw:4;
6401 uint64_t ncb_nxa:1;
6402 uint64_t pko_nxa:1;
6403 #else
6404 uint64_t pko_nxa:1;
6405 uint64_t ncb_nxa:1;
6406 uint64_t undflw:4;
6407 uint64_t reserved_6_7:2;
6408 uint64_t xscol:4;
6409 uint64_t xsdef:4;
6410 uint64_t reserved_16_63:48;
6411 #endif
6412 } cn38xxp2;
6413 struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
6414 struct cvmx_gmxx_tx_int_reg_cn52xx {
6415 #ifdef __BIG_ENDIAN_BITFIELD
6416 uint64_t reserved_20_63:44;
6417 uint64_t late_col:4;
6418 uint64_t xsdef:4;
6419 uint64_t xscol:4;
6420 uint64_t reserved_6_7:2;
6421 uint64_t undflw:4;
6422 uint64_t reserved_1_1:1;
6423 uint64_t pko_nxa:1;
6424 #else
6425 uint64_t pko_nxa:1;
6426 uint64_t reserved_1_1:1;
6427 uint64_t undflw:4;
6428 uint64_t reserved_6_7:2;
6429 uint64_t xscol:4;
6430 uint64_t xsdef:4;
6431 uint64_t late_col:4;
6432 uint64_t reserved_20_63:44;
6433 #endif
6434 } cn52xx;
6435 struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
6436 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
6437 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
6438 struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx;
6439 struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1;
6440 struct cvmx_gmxx_tx_int_reg_s cn61xx;
6441 struct cvmx_gmxx_tx_int_reg_cn63xx {
6442 #ifdef __BIG_ENDIAN_BITFIELD
6443 uint64_t reserved_24_63:40;
6444 uint64_t ptp_lost:4;
6445 uint64_t late_col:4;
6446 uint64_t xsdef:4;
6447 uint64_t xscol:4;
6448 uint64_t reserved_6_7:2;
6449 uint64_t undflw:4;
6450 uint64_t reserved_1_1:1;
6451 uint64_t pko_nxa:1;
6452 #else
6453 uint64_t pko_nxa:1;
6454 uint64_t reserved_1_1:1;
6455 uint64_t undflw:4;
6456 uint64_t reserved_6_7:2;
6457 uint64_t xscol:4;
6458 uint64_t xsdef:4;
6459 uint64_t late_col:4;
6460 uint64_t ptp_lost:4;
6461 uint64_t reserved_24_63:40;
6462 #endif
6463 } cn63xx;
6464 struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1;
6465 struct cvmx_gmxx_tx_int_reg_s cn66xx;
6466 struct cvmx_gmxx_tx_int_reg_cn68xx {
6467 #ifdef __BIG_ENDIAN_BITFIELD
6468 uint64_t reserved_25_63:39;
6469 uint64_t xchange:1;
6470 uint64_t ptp_lost:4;
6471 uint64_t late_col:4;
6472 uint64_t xsdef:4;
6473 uint64_t xscol:4;
6474 uint64_t reserved_6_7:2;
6475 uint64_t undflw:4;
6476 uint64_t pko_nxp:1;
6477 uint64_t pko_nxa:1;
6478 #else
6479 uint64_t pko_nxa:1;
6480 uint64_t pko_nxp:1;
6481 uint64_t undflw:4;
6482 uint64_t reserved_6_7:2;
6483 uint64_t xscol:4;
6484 uint64_t xsdef:4;
6485 uint64_t late_col:4;
6486 uint64_t ptp_lost:4;
6487 uint64_t xchange:1;
6488 uint64_t reserved_25_63:39;
6489 #endif
6490 } cn68xx;
6491 struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1;
6492 struct cvmx_gmxx_tx_int_reg_cnf71xx {
6493 #ifdef __BIG_ENDIAN_BITFIELD
6494 uint64_t reserved_25_63:39;
6495 uint64_t xchange:1;
6496 uint64_t reserved_22_23:2;
6497 uint64_t ptp_lost:2;
6498 uint64_t reserved_18_19:2;
6499 uint64_t late_col:2;
6500 uint64_t reserved_14_15:2;
6501 uint64_t xsdef:2;
6502 uint64_t reserved_10_11:2;
6503 uint64_t xscol:2;
6504 uint64_t reserved_4_7:4;
6505 uint64_t undflw:2;
6506 uint64_t reserved_1_1:1;
6507 uint64_t pko_nxa:1;
6508 #else
6509 uint64_t pko_nxa:1;
6510 uint64_t reserved_1_1:1;
6511 uint64_t undflw:2;
6512 uint64_t reserved_4_7:4;
6513 uint64_t xscol:2;
6514 uint64_t reserved_10_11:2;
6515 uint64_t xsdef:2;
6516 uint64_t reserved_14_15:2;
6517 uint64_t late_col:2;
6518 uint64_t reserved_18_19:2;
6519 uint64_t ptp_lost:2;
6520 uint64_t reserved_22_23:2;
6521 uint64_t xchange:1;
6522 uint64_t reserved_25_63:39;
6523 #endif
6524 } cnf71xx;
6525 };
6526
6527 union cvmx_gmxx_tx_jam {
6528 uint64_t u64;
6529 struct cvmx_gmxx_tx_jam_s {
6530 #ifdef __BIG_ENDIAN_BITFIELD
6531 uint64_t reserved_8_63:56;
6532 uint64_t jam:8;
6533 #else
6534 uint64_t jam:8;
6535 uint64_t reserved_8_63:56;
6536 #endif
6537 } s;
6538 struct cvmx_gmxx_tx_jam_s cn30xx;
6539 struct cvmx_gmxx_tx_jam_s cn31xx;
6540 struct cvmx_gmxx_tx_jam_s cn38xx;
6541 struct cvmx_gmxx_tx_jam_s cn38xxp2;
6542 struct cvmx_gmxx_tx_jam_s cn50xx;
6543 struct cvmx_gmxx_tx_jam_s cn52xx;
6544 struct cvmx_gmxx_tx_jam_s cn52xxp1;
6545 struct cvmx_gmxx_tx_jam_s cn56xx;
6546 struct cvmx_gmxx_tx_jam_s cn56xxp1;
6547 struct cvmx_gmxx_tx_jam_s cn58xx;
6548 struct cvmx_gmxx_tx_jam_s cn58xxp1;
6549 struct cvmx_gmxx_tx_jam_s cn61xx;
6550 struct cvmx_gmxx_tx_jam_s cn63xx;
6551 struct cvmx_gmxx_tx_jam_s cn63xxp1;
6552 struct cvmx_gmxx_tx_jam_s cn66xx;
6553 struct cvmx_gmxx_tx_jam_s cn68xx;
6554 struct cvmx_gmxx_tx_jam_s cn68xxp1;
6555 struct cvmx_gmxx_tx_jam_s cnf71xx;
6556 };
6557
6558 union cvmx_gmxx_tx_lfsr {
6559 uint64_t u64;
6560 struct cvmx_gmxx_tx_lfsr_s {
6561 #ifdef __BIG_ENDIAN_BITFIELD
6562 uint64_t reserved_16_63:48;
6563 uint64_t lfsr:16;
6564 #else
6565 uint64_t lfsr:16;
6566 uint64_t reserved_16_63:48;
6567 #endif
6568 } s;
6569 struct cvmx_gmxx_tx_lfsr_s cn30xx;
6570 struct cvmx_gmxx_tx_lfsr_s cn31xx;
6571 struct cvmx_gmxx_tx_lfsr_s cn38xx;
6572 struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
6573 struct cvmx_gmxx_tx_lfsr_s cn50xx;
6574 struct cvmx_gmxx_tx_lfsr_s cn52xx;
6575 struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
6576 struct cvmx_gmxx_tx_lfsr_s cn56xx;
6577 struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
6578 struct cvmx_gmxx_tx_lfsr_s cn58xx;
6579 struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
6580 struct cvmx_gmxx_tx_lfsr_s cn61xx;
6581 struct cvmx_gmxx_tx_lfsr_s cn63xx;
6582 struct cvmx_gmxx_tx_lfsr_s cn63xxp1;
6583 struct cvmx_gmxx_tx_lfsr_s cn66xx;
6584 struct cvmx_gmxx_tx_lfsr_s cn68xx;
6585 struct cvmx_gmxx_tx_lfsr_s cn68xxp1;
6586 struct cvmx_gmxx_tx_lfsr_s cnf71xx;
6587 };
6588
6589 union cvmx_gmxx_tx_ovr_bp {
6590 uint64_t u64;
6591 struct cvmx_gmxx_tx_ovr_bp_s {
6592 #ifdef __BIG_ENDIAN_BITFIELD
6593 uint64_t reserved_48_63:16;
6594 uint64_t tx_prt_bp:16;
6595 uint64_t reserved_12_31:20;
6596 uint64_t en:4;
6597 uint64_t bp:4;
6598 uint64_t ign_full:4;
6599 #else
6600 uint64_t ign_full:4;
6601 uint64_t bp:4;
6602 uint64_t en:4;
6603 uint64_t reserved_12_31:20;
6604 uint64_t tx_prt_bp:16;
6605 uint64_t reserved_48_63:16;
6606 #endif
6607 } s;
6608 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
6609 #ifdef __BIG_ENDIAN_BITFIELD
6610 uint64_t reserved_11_63:53;
6611 uint64_t en:3;
6612 uint64_t reserved_7_7:1;
6613 uint64_t bp:3;
6614 uint64_t reserved_3_3:1;
6615 uint64_t ign_full:3;
6616 #else
6617 uint64_t ign_full:3;
6618 uint64_t reserved_3_3:1;
6619 uint64_t bp:3;
6620 uint64_t reserved_7_7:1;
6621 uint64_t en:3;
6622 uint64_t reserved_11_63:53;
6623 #endif
6624 } cn30xx;
6625 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
6626 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
6627 #ifdef __BIG_ENDIAN_BITFIELD
6628 uint64_t reserved_12_63:52;
6629 uint64_t en:4;
6630 uint64_t bp:4;
6631 uint64_t ign_full:4;
6632 #else
6633 uint64_t ign_full:4;
6634 uint64_t bp:4;
6635 uint64_t en:4;
6636 uint64_t reserved_12_63:52;
6637 #endif
6638 } cn38xx;
6639 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
6640 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
6641 struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
6642 struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
6643 struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
6644 struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
6645 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
6646 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
6647 struct cvmx_gmxx_tx_ovr_bp_s cn61xx;
6648 struct cvmx_gmxx_tx_ovr_bp_s cn63xx;
6649 struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1;
6650 struct cvmx_gmxx_tx_ovr_bp_s cn66xx;
6651 struct cvmx_gmxx_tx_ovr_bp_s cn68xx;
6652 struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1;
6653 struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
6654 #ifdef __BIG_ENDIAN_BITFIELD
6655 uint64_t reserved_48_63:16;
6656 uint64_t tx_prt_bp:16;
6657 uint64_t reserved_10_31:22;
6658 uint64_t en:2;
6659 uint64_t reserved_6_7:2;
6660 uint64_t bp:2;
6661 uint64_t reserved_2_3:2;
6662 uint64_t ign_full:2;
6663 #else
6664 uint64_t ign_full:2;
6665 uint64_t reserved_2_3:2;
6666 uint64_t bp:2;
6667 uint64_t reserved_6_7:2;
6668 uint64_t en:2;
6669 uint64_t reserved_10_31:22;
6670 uint64_t tx_prt_bp:16;
6671 uint64_t reserved_48_63:16;
6672 #endif
6673 } cnf71xx;
6674 };
6675
6676 union cvmx_gmxx_tx_pause_pkt_dmac {
6677 uint64_t u64;
6678 struct cvmx_gmxx_tx_pause_pkt_dmac_s {
6679 #ifdef __BIG_ENDIAN_BITFIELD
6680 uint64_t reserved_48_63:16;
6681 uint64_t dmac:48;
6682 #else
6683 uint64_t dmac:48;
6684 uint64_t reserved_48_63:16;
6685 #endif
6686 } s;
6687 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
6688 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
6689 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
6690 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
6691 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
6692 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
6693 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
6694 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
6695 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
6696 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
6697 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
6698 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx;
6699 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx;
6700 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1;
6701 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx;
6702 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx;
6703 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1;
6704 struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx;
6705 };
6706
6707 union cvmx_gmxx_tx_pause_pkt_type {
6708 uint64_t u64;
6709 struct cvmx_gmxx_tx_pause_pkt_type_s {
6710 #ifdef __BIG_ENDIAN_BITFIELD
6711 uint64_t reserved_16_63:48;
6712 uint64_t type:16;
6713 #else
6714 uint64_t type:16;
6715 uint64_t reserved_16_63:48;
6716 #endif
6717 } s;
6718 struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
6719 struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
6720 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
6721 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
6722 struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
6723 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
6724 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
6725 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
6726 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
6727 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
6728 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
6729 struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx;
6730 struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx;
6731 struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1;
6732 struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx;
6733 struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx;
6734 struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1;
6735 struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx;
6736 };
6737
6738 union cvmx_gmxx_tx_prts {
6739 uint64_t u64;
6740 struct cvmx_gmxx_tx_prts_s {
6741 #ifdef __BIG_ENDIAN_BITFIELD
6742 uint64_t reserved_5_63:59;
6743 uint64_t prts:5;
6744 #else
6745 uint64_t prts:5;
6746 uint64_t reserved_5_63:59;
6747 #endif
6748 } s;
6749 struct cvmx_gmxx_tx_prts_s cn30xx;
6750 struct cvmx_gmxx_tx_prts_s cn31xx;
6751 struct cvmx_gmxx_tx_prts_s cn38xx;
6752 struct cvmx_gmxx_tx_prts_s cn38xxp2;
6753 struct cvmx_gmxx_tx_prts_s cn50xx;
6754 struct cvmx_gmxx_tx_prts_s cn52xx;
6755 struct cvmx_gmxx_tx_prts_s cn52xxp1;
6756 struct cvmx_gmxx_tx_prts_s cn56xx;
6757 struct cvmx_gmxx_tx_prts_s cn56xxp1;
6758 struct cvmx_gmxx_tx_prts_s cn58xx;
6759 struct cvmx_gmxx_tx_prts_s cn58xxp1;
6760 struct cvmx_gmxx_tx_prts_s cn61xx;
6761 struct cvmx_gmxx_tx_prts_s cn63xx;
6762 struct cvmx_gmxx_tx_prts_s cn63xxp1;
6763 struct cvmx_gmxx_tx_prts_s cn66xx;
6764 struct cvmx_gmxx_tx_prts_s cn68xx;
6765 struct cvmx_gmxx_tx_prts_s cn68xxp1;
6766 struct cvmx_gmxx_tx_prts_s cnf71xx;
6767 };
6768
6769 union cvmx_gmxx_tx_spi_ctl {
6770 uint64_t u64;
6771 struct cvmx_gmxx_tx_spi_ctl_s {
6772 #ifdef __BIG_ENDIAN_BITFIELD
6773 uint64_t reserved_2_63:62;
6774 uint64_t tpa_clr:1;
6775 uint64_t cont_pkt:1;
6776 #else
6777 uint64_t cont_pkt:1;
6778 uint64_t tpa_clr:1;
6779 uint64_t reserved_2_63:62;
6780 #endif
6781 } s;
6782 struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
6783 struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
6784 struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
6785 struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
6786 };
6787
6788 union cvmx_gmxx_tx_spi_drain {
6789 uint64_t u64;
6790 struct cvmx_gmxx_tx_spi_drain_s {
6791 #ifdef __BIG_ENDIAN_BITFIELD
6792 uint64_t reserved_16_63:48;
6793 uint64_t drain:16;
6794 #else
6795 uint64_t drain:16;
6796 uint64_t reserved_16_63:48;
6797 #endif
6798 } s;
6799 struct cvmx_gmxx_tx_spi_drain_s cn38xx;
6800 struct cvmx_gmxx_tx_spi_drain_s cn58xx;
6801 struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
6802 };
6803
6804 union cvmx_gmxx_tx_spi_max {
6805 uint64_t u64;
6806 struct cvmx_gmxx_tx_spi_max_s {
6807 #ifdef __BIG_ENDIAN_BITFIELD
6808 uint64_t reserved_23_63:41;
6809 uint64_t slice:7;
6810 uint64_t max2:8;
6811 uint64_t max1:8;
6812 #else
6813 uint64_t max1:8;
6814 uint64_t max2:8;
6815 uint64_t slice:7;
6816 uint64_t reserved_23_63:41;
6817 #endif
6818 } s;
6819 struct cvmx_gmxx_tx_spi_max_cn38xx {
6820 #ifdef __BIG_ENDIAN_BITFIELD
6821 uint64_t reserved_16_63:48;
6822 uint64_t max2:8;
6823 uint64_t max1:8;
6824 #else
6825 uint64_t max1:8;
6826 uint64_t max2:8;
6827 uint64_t reserved_16_63:48;
6828 #endif
6829 } cn38xx;
6830 struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
6831 struct cvmx_gmxx_tx_spi_max_s cn58xx;
6832 struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
6833 };
6834
6835 union cvmx_gmxx_tx_spi_roundx {
6836 uint64_t u64;
6837 struct cvmx_gmxx_tx_spi_roundx_s {
6838 #ifdef __BIG_ENDIAN_BITFIELD
6839 uint64_t reserved_16_63:48;
6840 uint64_t round:16;
6841 #else
6842 uint64_t round:16;
6843 uint64_t reserved_16_63:48;
6844 #endif
6845 } s;
6846 struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
6847 struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
6848 };
6849
6850 union cvmx_gmxx_tx_spi_thresh {
6851 uint64_t u64;
6852 struct cvmx_gmxx_tx_spi_thresh_s {
6853 #ifdef __BIG_ENDIAN_BITFIELD
6854 uint64_t reserved_6_63:58;
6855 uint64_t thresh:6;
6856 #else
6857 uint64_t thresh:6;
6858 uint64_t reserved_6_63:58;
6859 #endif
6860 } s;
6861 struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
6862 struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
6863 struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
6864 struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
6865 };
6866
6867 union cvmx_gmxx_tx_xaui_ctl {
6868 uint64_t u64;
6869 struct cvmx_gmxx_tx_xaui_ctl_s {
6870 #ifdef __BIG_ENDIAN_BITFIELD
6871 uint64_t reserved_11_63:53;
6872 uint64_t hg_pause_hgi:2;
6873 uint64_t hg_en:1;
6874 uint64_t reserved_7_7:1;
6875 uint64_t ls_byp:1;
6876 uint64_t ls:2;
6877 uint64_t reserved_2_3:2;
6878 uint64_t uni_en:1;
6879 uint64_t dic_en:1;
6880 #else
6881 uint64_t dic_en:1;
6882 uint64_t uni_en:1;
6883 uint64_t reserved_2_3:2;
6884 uint64_t ls:2;
6885 uint64_t ls_byp:1;
6886 uint64_t reserved_7_7:1;
6887 uint64_t hg_en:1;
6888 uint64_t hg_pause_hgi:2;
6889 uint64_t reserved_11_63:53;
6890 #endif
6891 } s;
6892 struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
6893 struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
6894 struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
6895 struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
6896 struct cvmx_gmxx_tx_xaui_ctl_s cn61xx;
6897 struct cvmx_gmxx_tx_xaui_ctl_s cn63xx;
6898 struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1;
6899 struct cvmx_gmxx_tx_xaui_ctl_s cn66xx;
6900 struct cvmx_gmxx_tx_xaui_ctl_s cn68xx;
6901 struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1;
6902 struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx;
6903 };
6904
6905 union cvmx_gmxx_xaui_ext_loopback {
6906 uint64_t u64;
6907 struct cvmx_gmxx_xaui_ext_loopback_s {
6908 #ifdef __BIG_ENDIAN_BITFIELD
6909 uint64_t reserved_5_63:59;
6910 uint64_t en:1;
6911 uint64_t thresh:4;
6912 #else
6913 uint64_t thresh:4;
6914 uint64_t en:1;
6915 uint64_t reserved_5_63:59;
6916 #endif
6917 } s;
6918 struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
6919 struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
6920 struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
6921 struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
6922 struct cvmx_gmxx_xaui_ext_loopback_s cn61xx;
6923 struct cvmx_gmxx_xaui_ext_loopback_s cn63xx;
6924 struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1;
6925 struct cvmx_gmxx_xaui_ext_loopback_s cn66xx;
6926 struct cvmx_gmxx_xaui_ext_loopback_s cn68xx;
6927 struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1;
6928 struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx;
6929 };
6930
6931 #endif
6932
