Searched refs:cp_int_cntl (Results 1 – 7 of 7) sorted by relevance
| /Linux-v4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 3249 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local
3253 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3254 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3255 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3258 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3259 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state()
3260 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3271 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local
3275 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3276 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_compute_eop_interrupt_state()
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| D | gfx_v7_0.c | 4793 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local
4797 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4798 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4799 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4802 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4803 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state()
4804 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4867 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local
4871 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4872 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state()
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| /Linux-v4.19/drivers/gpu/drm/radeon/ |
| D | evergreen.c | 213 int ring, u32 cp_int_cntl);
4490 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local
4521 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4534 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set()
4535 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4558 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4562 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
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| D | ni.c | 1390 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1393 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
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| D | r600.c | 3760 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3818 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3819 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3870 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
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| D | si.c | 6049 u32 cp_int_cntl; in si_irq_set() local
6067 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6079 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6099 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
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| D | cik.c | 7028 u32 cp_int_cntl; in cik_irq_set() local
7048 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7050 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set()
7074 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7228 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
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