Searched refs:com_integloop_gain1_mode0 (Results 1 – 1 of 1) sorted by relevance
61 u32 com_integloop_gain1_mode0; member306 cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8); in pll_calculate()379 DBG("com_integloop_gain1_mode0 = 0x%x", cfg->com_integloop_gain1_mode0); in pll_calculate()489 cfg.com_integloop_gain1_mode0); in hdmi_8996_pll_set_clk_rate()
