Searched refs:com_integloop_gain0_mode0 (Results 1 – 1 of 1) sorted by relevance
60 u32 com_integloop_gain0_mode0; member305 cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff); in pll_calculate()378 DBG("com_integloop_gain0_mode0 = 0x%x", cfg->com_integloop_gain0_mode0); in pll_calculate()487 cfg.com_integloop_gain0_mode0); in hdmi_8996_pll_set_clk_rate()
