Searched refs:clock_div (Results 1 – 5 of 5) sorted by relevance
85 unsigned short clock_div = JZ_WDT_CLOCK_DIV_1; in jz4740_wdt_set_timeout() local91 if (clock_div == JZ_WDT_CLOCK_DIV_1024) { in jz4740_wdt_set_timeout()98 clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT); in jz4740_wdt_set_timeout()102 writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL); in jz4740_wdt_set_timeout()106 writew(clock_div | JZ_WDT_CLOCK_RTC, in jz4740_wdt_set_timeout()
49 uint32_t clock_div = 0; in cvmx_helper_qlm_jtag_init() local54 clock_div++; in cvmx_helper_qlm_jtag_init()63 jtgc.s.clk_div = clock_div; in cvmx_helper_qlm_jtag_init()
1461 int clock_div = 7; /* 0=30 1=25 2=20 3=15 4=12 5=7.5 6=6 7=3fps ?? */ in cit_get_clock_div() local1469 while (clock_div > 3 && in cit_get_clock_div()1472 fps[clock_div - 1] * 3 / 2) in cit_get_clock_div()1473 clock_div--; in cit_get_clock_div()1479 clock_div, fps[clock_div]); in cit_get_clock_div()1481 return clock_div; in cit_get_clock_div()1487 int clock_div; in cit_start_model0() local1489 clock_div = cit_get_clock_div(gspca_dev); in cit_start_model0()1490 if (clock_div < 0) in cit_start_model0()1491 return clock_div; in cit_start_model0()[all …]
423 u_char clock_div; member513 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); in cyber2000fb_set_timing()745 hw->clock_div = div2 << 6 | (best_div1 - 1); in cyber2000fb_decode_clock()750 hw->clock_div |= EXT_DCLK_DIV_VFSEL; in cyber2000fb_decode_clock()
390 u8 clock_div; /* Clock divider */ member
