| /Linux-v4.19/drivers/clk/zynq/ |
| D | pll.c | 93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
115 reg = clk_readl(clk->pll_ctrl); in zynq_pll_is_enabled()
141 reg = clk_readl(clk->pll_ctrl); in zynq_pll_enable()
144 while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit))) in zynq_pll_enable()
171 reg = clk_readl(clk->pll_ctrl); in zynq_pll_disable()
226 reg = clk_readl(pll->pll_ctrl); in clk_register_zynq_pll()
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| D | clkc.c | 161 enable_reg = clk_readl(fclk_gate_reg) & 1; in zynq_clk_register_fclk()
290 tmp = clk_readl(SLCR_621_TRUE) & 1; in zynq_clk_setup()
513 tmp = clk_readl(SLCR_DBG_CLK_CTRL); in zynq_clk_setup()
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| /Linux-v4.19/drivers/clk/ti/ |
| D | clkt_dflt.c | 68 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic()
103 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) & in _omap2_module_wait_ready()
228 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_enable()
234 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
258 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_disable()
284 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_is_enabled()
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| D | apll.c | 58 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()
63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable()
71 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()
102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable()
116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled()
246 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled()
272 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable()
278 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in omap2_apll_enable()
302 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_disable()
320 v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg); in omap2_apll_set_autoidle()
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| D | dpll3xxx.c | 57 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
76 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
154 if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) == in _omap3_noncore_dpll_lock()
320 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
327 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_program()
377 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
658 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_autoidle_read()
692 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_allow_idle()
717 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_deny_idle()
776 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
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| D | dpll44xx.c | 52 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
70 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
131 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap4_dpll_regm4xen_recalc()
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| D | clkt_iclk.c | 39 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_allow_idle()
54 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_deny_idle()
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| D | clkt_dpll.c | 216 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent()
252 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate()
259 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap2_get_dpll_rate()
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| D | clkctrl.c | 154 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_enable()
165 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_enable()
184 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_disable()
194 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_disable()
212 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_is_enabled()
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| D | autoidle.c | 76 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _allow_autoidle()
90 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _deny_autoidle()
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| D | mux.c | 42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
84 val = ti_clk_ll_ops->clk_readl(&mux->reg); in ti_clk_mux_set_parent()
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| D | clk.c | 113 ops->clk_readl = clk_memmap_readl; in ti_clk_setup_ll_ops()
289 ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ in ti_clk_latch()
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| D | gate.c | 79 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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| /Linux-v4.19/drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 355 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_recalc_rate()
356 mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); in lpc18xx_pll0_recalc_rate()
357 npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); in lpc18xx_pll0_recalc_rate()
418 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); in lpc18xx_pll0_set_rate()
433 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); in lpc18xx_pll0_set_rate()
461 stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT); in lpc18xx_pll1_recalc_rate()
462 ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); in lpc18xx_pll1_recalc_rate()
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| D | clk-lpc18xx-ccu.c | 145 val = clk_readl(gate->reg); in lpc18xx_ccu_gate_endisable()
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| /Linux-v4.19/drivers/clk/ |
| D | clk-multiplier.c | 33 val = clk_readl(mult->reg) >> mult->shift; in clk_multiplier_recalc_rate()
124 val = clk_readl(mult->reg); in clk_multiplier_set_rate()
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| D | clk-gate.c | 61 reg = clk_readl(gate->reg); in clk_gate_endisable()
94 reg = clk_readl(gate->reg); in clk_gate_is_enabled()
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| D | clk-fractional-divider.c | 33 val = clk_readl(fd->reg); in clk_fd_recalc_rate()
111 val = clk_readl(fd->reg); in clk_fd_set_rate()
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| D | clk-mux.c | 79 val = clk_readl(mux->reg) >> mux->shift; in clk_mux_get_parent()
100 reg = clk_readl(mux->reg); in clk_mux_set_parent()
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| D | clk-divider.c | 141 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_recalc_rate()
376 val = clk_readl(divider->reg) >> divider->shift; in clk_divider_round_rate()
426 val = clk_readl(divider->reg); in clk_divider_set_rate()
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| /Linux-v4.19/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 27 val = clk_readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
127 val = clk_readl(divider->reg); in clk_half_divider_set_rate()
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| D | clk-ddr.c | 86 val = clk_readl(ddrclk->reg_base + in rockchip_ddrclk_get_parent()
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| /Linux-v4.19/arch/arm/mach-omap2/ |
| D | clkt2xxx_dpllcore.c | 142 omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg); in omap2_reprogram_dpllcore()
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| /Linux-v4.19/drivers/clk/hisilicon/ |
| D | clk-hisi-phase.c | 78 val = clk_readl(phase->reg); in hisi_clk_set_phase()
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| /Linux-v4.19/include/linux/clk/ |
| D | ti.h | 229 u32 (*clk_readl)(const struct clk_omap_reg *reg); member
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