1 /*
2 * Marvell PXA25x family clocks
3 *
4 * Copyright (C) 2014 Robert Jarzmik
5 *
6 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
13 * should go away.
14 */
15 #include <linux/clk-provider.h>
16 #include <linux/clk.h>
17 #include <linux/clkdev.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <mach/pxa2xx-regs.h>
21 #include <mach/smemc.h>
22
23 #include <dt-bindings/clock/pxa-clock.h>
24 #include "clk-pxa.h"
25
26 #define KHz 1000
27 #define MHz (1000 * 1000)
28
29 enum {
30 PXA_CORE_RUN = 0,
31 PXA_CORE_TURBO,
32 };
33
34 #define PXA25x_CLKCFG(T) \
35 (CLKCFG_FCS | \
36 ((T) ? CLKCFG_TURBO : 0))
37 #define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
38
39 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
40 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
41
42 /* Define the refresh period in mSec for the SDRAM and the number of rows */
43 #define SDRAM_TREF 64 /* standard 64ms SDRAM */
44
45 /*
46 * Various clock factors driven by the CCCR register.
47 */
48
49 /* Crystal Frequency to Memory Frequency Multiplier (L) */
50 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
51
52 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
53 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
54
55 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
56 /* Note: we store the value N * 2 here. */
57 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
58
59 static const char * const get_freq_khz[] = {
60 "core", "run", "cpll", "memory"
61 };
62
get_sdram_rows(void)63 static int get_sdram_rows(void)
64 {
65 static int sdram_rows;
66 unsigned int drac2 = 0, drac0 = 0;
67 u32 mdcnfg;
68
69 if (sdram_rows)
70 return sdram_rows;
71
72 mdcnfg = readl_relaxed(MDCNFG);
73
74 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
75 drac2 = MDCNFG_DRAC2(mdcnfg);
76
77 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
78 drac0 = MDCNFG_DRAC0(mdcnfg);
79
80 sdram_rows = 1 << (11 + max(drac0, drac2));
81 return sdram_rows;
82 }
83
mdrefr_dri(unsigned int freq_khz)84 static u32 mdrefr_dri(unsigned int freq_khz)
85 {
86 u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
87
88 return interval / 32;
89 }
90
91 /*
92 * Get the clock frequency as reflected by CCCR and the turbo flag.
93 * We assume these values have been applied via a fcs.
94 * If info is not 0 we also display the current settings.
95 */
pxa25x_get_clk_frequency_khz(int info)96 unsigned int pxa25x_get_clk_frequency_khz(int info)
97 {
98 struct clk *clk;
99 unsigned long clks[5];
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
103 clk = clk_get(NULL, get_freq_khz[i]);
104 if (IS_ERR(clk)) {
105 clks[i] = 0;
106 } else {
107 clks[i] = clk_get_rate(clk);
108 clk_put(clk);
109 }
110 }
111
112 if (info) {
113 pr_info("Run Mode clock: %ld.%02ldMHz\n",
114 clks[1] / 1000000, (clks[1] % 1000000) / 10000);
115 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
116 clks[2] / 1000000, (clks[2] % 1000000) / 10000);
117 pr_info("Memory clock: %ld.%02ldMHz\n",
118 clks[3] / 1000000, (clks[3] % 1000000) / 10000);
119 }
120
121 return (unsigned int)clks[0] / KHz;
122 }
123
clk_pxa25x_memory_get_rate(struct clk_hw * hw,unsigned long parent_rate)124 static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
125 unsigned long parent_rate)
126 {
127 unsigned long cccr = readl(CCCR);
128 unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
129
130 return parent_rate / m;
131 }
132 PARENTS(clk_pxa25x_memory) = { "run" };
133 RATE_RO_OPS(clk_pxa25x_memory, "memory");
134
135 PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
136 PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
137 PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
138
139 #define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
140 bit, is_lp, flags) \
141 PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
142 is_lp, CKEN, CKEN_ ## bit, flags)
143 #define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
144 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
145 div_hp, bit, NULL, 0)
146 #define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
147 PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
148 div_hp, bit, NULL, 0)
149 #define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
150 PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
151 div_hp, bit, NULL, 0)
152
153 #define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
154 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
155 CKEN, CKEN_ ## bit, 0)
156 #define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
157 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
158 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
159
160 static struct desc_clk_cken pxa25x_clocks[] __initdata = {
161 PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
162 PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
163 PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
164 PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
165 PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
166 PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
167 PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
168 PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
169 PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
170 PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
171 PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
172 PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
173 PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
174 PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
175 PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
176
177 PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
178 PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
179 clk_pxa25x_memory_parents, 0),
180 };
181
182 /*
183 * In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
184 * - freq_cpll = n * m * L * 3.6864 MHz
185 * - n = N2 / 2
186 * - m = 2^(M - 1), where 1 <= M <= 3
187 * - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
188 */
189 static struct pxa2xx_freq pxa25x_freqs[] = {
190 /* CPU MEMBUS CCCR DIV2 CCLKCFG */
191 { 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
192 {199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
193 {298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
194 {398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
195 };
196
clk_pxa25x_core_get_parent(struct clk_hw * hw)197 static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
198 {
199 unsigned long clkcfg;
200 unsigned int t;
201
202 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
203 t = clkcfg & (1 << 0);
204 if (t)
205 return PXA_CORE_TURBO;
206 return PXA_CORE_RUN;
207 }
208
clk_pxa25x_core_set_parent(struct clk_hw * hw,u8 index)209 static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
210 {
211 if (index > PXA_CORE_TURBO)
212 return -EINVAL;
213
214 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
215
216 return 0;
217 }
218
clk_pxa25x_core_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)219 static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
220 struct clk_rate_request *req)
221 {
222 return __clk_mux_determine_rate(hw, req);
223 }
224
225 PARENTS(clk_pxa25x_core) = { "run", "cpll" };
226 MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
227
clk_pxa25x_run_get_rate(struct clk_hw * hw,unsigned long parent_rate)228 static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
229 unsigned long parent_rate)
230 {
231 unsigned long cccr = readl(CCCR);
232 unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
233
234 return (parent_rate / n2) * 2;
235 }
236 PARENTS(clk_pxa25x_run) = { "cpll" };
237 RATE_RO_OPS(clk_pxa25x_run, "run");
238
clk_pxa25x_cpll_get_rate(struct clk_hw * hw,unsigned long parent_rate)239 static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
240 unsigned long parent_rate)
241 {
242 unsigned long clkcfg, cccr = readl(CCCR);
243 unsigned int l, m, n2, t;
244
245 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
246 t = clkcfg & (1 << 0);
247 l = L_clk_mult[(cccr >> 0) & 0x1f];
248 m = M_clk_mult[(cccr >> 5) & 0x03];
249 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
250
251 return m * l * n2 * parent_rate / 2;
252 }
253
clk_pxa25x_cpll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)254 static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
255 struct clk_rate_request *req)
256 {
257 return pxa2xx_determine_rate(req, pxa25x_freqs,
258 ARRAY_SIZE(pxa25x_freqs));
259 }
260
clk_pxa25x_cpll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)261 static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
262 unsigned long parent_rate)
263 {
264 int i;
265
266 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
267 for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
268 if (pxa25x_freqs[i].cpll == rate)
269 break;
270
271 if (i >= ARRAY_SIZE(pxa25x_freqs))
272 return -EINVAL;
273
274 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR);
275
276 return 0;
277 }
278 PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
279 RATE_OPS(clk_pxa25x_cpll, "cpll");
280
pxa25x_register_core(void)281 static void __init pxa25x_register_core(void)
282 {
283 clkdev_pxa_register(CLK_NONE, "cpll", NULL,
284 clk_register_clk_pxa25x_cpll());
285 clkdev_pxa_register(CLK_NONE, "run", NULL,
286 clk_register_clk_pxa25x_run());
287 clkdev_pxa_register(CLK_CORE, "core", NULL,
288 clk_register_clk_pxa25x_core());
289 }
290
pxa25x_register_plls(void)291 static void __init pxa25x_register_plls(void)
292 {
293 clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
294 CLK_GET_RATE_NOCACHE, 3686400);
295 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
296 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
297 CLK_GET_RATE_NOCACHE,
298 32768));
299 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
300 clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
301 0, 26, 1);
302 clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
303 0, 40, 1);
304 }
305
pxa25x_base_clocks_init(void)306 static void __init pxa25x_base_clocks_init(void)
307 {
308 pxa25x_register_plls();
309 pxa25x_register_core();
310 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
311 clk_register_clk_pxa25x_memory());
312 }
313
314 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
315 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
316 struct dummy_clk {
317 const char *con_id;
318 const char *dev_id;
319 const char *parent;
320 };
321 static struct dummy_clk dummy_clks[] __initdata = {
322 DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
323 DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
324 DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
325 DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
326 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
327 DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
328 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
329 };
330
pxa25x_dummy_clocks_init(void)331 static void __init pxa25x_dummy_clocks_init(void)
332 {
333 struct clk *clk;
334 struct dummy_clk *d;
335 const char *name;
336 int i;
337
338 /*
339 * All pinctrl logic has been wiped out of the clock driver, especially
340 * for gpio11 and gpio12 outputs. Machine code should ensure proper pin
341 * control (ie. pxa2xx_mfp_config() invocation).
342 */
343 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
344 d = &dummy_clks[i];
345 name = d->dev_id ? d->dev_id : d->con_id;
346 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
347 clk_register_clkdev(clk, d->con_id, d->dev_id);
348 }
349 }
350
pxa25x_clocks_init(void)351 int __init pxa25x_clocks_init(void)
352 {
353 pxa25x_base_clocks_init();
354 pxa25x_dummy_clocks_init();
355 return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
356 }
357
pxa25x_dt_clocks_init(struct device_node * np)358 static void __init pxa25x_dt_clocks_init(struct device_node *np)
359 {
360 pxa25x_clocks_init();
361 clk_pxa_dt_common_init(np);
362 }
363 CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
364 pxa25x_dt_clocks_init);
365
