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Searched refs:clk_pll1 (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/arch/arm/mach-ep93xx/
Dclock.c74 static struct clk clk_pll1 = { variable
78 .parent = &clk_pll1,
81 .parent = &clk_pll1,
84 .parent = &clk_pll1,
217 INIT_CK(NULL, "pll1", &clk_pll1),
370 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()
386 mclk = &clk_pll1; in calc_clk_div()
552 clk_pll1.rate = clk_xtali.rate; in ep93xx_clock_init()
554 clk_pll1.rate = calc_pll_rate(value); in ep93xx_clock_init()
557 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; in ep93xx_clock_init()
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/Linux-v4.19/drivers/gpu/drm/sun4i/
Dsun8i_hdmi_phy.c497 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1"); in sun8i_hdmi_phy_probe()
498 if (IS_ERR(phy->clk_pll1)) { in sun8i_hdmi_phy_probe()
500 ret = PTR_ERR(phy->clk_pll1); in sun8i_hdmi_phy_probe()
553 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_probe()
577 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_remove()
Dsun8i_hdmi_phy_clk.c155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
Dsun8i_dw_hdmi.h165 struct clk *clk_pll1; member
/Linux-v4.19/drivers/clk/sirf/
Dclk-common.c218 static struct clk_pll clk_pll1 = { variable
410 if (rate == clk_get_rate(clk_pll1.hw.clk)) { in cpu_clk_set_rate()
411 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
428 if (cur_parent == clk_pll1.hw.clk) { in cpu_clk_set_rate()
433 ret2 = clk_set_rate(clk_pll1.hw.clk, rate); in cpu_clk_set_rate()
435 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
Dclk-prima2.c71 &clk_pll1.hw,
Dclk-atlas6.c72 &clk_pll1.hw,