| /Linux-v4.19/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_io_util.c | 37 clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); in msm_dss_get_clk()
42 clk_arry[i].clk_name, rc); in msm_dss_get_clk()
68 clk_arry[i].clk_name, in msm_dss_clk_set_rate()
76 clk_arry[i].clk_name, rc); in msm_dss_clk_set_rate()
83 clk_arry[i].clk_name); in msm_dss_clk_set_rate()
100 clk_arry[i].clk_name); in msm_dss_enable_clk()
107 clk_arry[i].clk_name, rc); in msm_dss_enable_clk()
111 clk_arry[i].clk_name); in msm_dss_enable_clk()
125 clk_arry[i].clk_name); in msm_dss_enable_clk()
132 clk_arry[i].clk_name); in msm_dss_enable_clk()
[all …]
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| /Linux-v4.19/drivers/clk/sunxi/ |
| D | clk-a10-pll2.c | 49 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() local
129 SUN4I_A10_PLL2_1X, &clk_name); in sun4i_pll2_setup()
130 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
144 SUN4I_A10_PLL2_2X, &clk_name); in sun4i_pll2_setup()
145 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
153 SUN4I_A10_PLL2_4X, &clk_name); in sun4i_pll2_setup()
154 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
162 SUN4I_A10_PLL2_8X, &clk_name); in sun4i_pll2_setup()
163 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
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| D | clk-sun4i-pll3.c | 31 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() local
39 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
44 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
65 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_pll3_setup()
72 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_pll3_setup()
79 clk_name); in sun4i_a10_pll3_setup()
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| D | clk-sun4i-display.c | 113 const char *clk_name = node->name; in sun4i_a10_display_init() local
123 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_display_init()
127 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_display_init()
133 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
165 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_display_init()
173 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_display_init()
179 pr_err("%s: Couldn't register DT provider\n", clk_name); in sun4i_a10_display_init()
206 clk_name); in sun4i_a10_display_init()
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| D | clk-sunxi.c | 663 const char *clk_name = node->name; in sunxi_mux_clk_setup() local
675 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_mux_clk_setup()
681 clk = clk_register_mux(NULL, clk_name, parents, i, in sunxi_mux_clk_setup()
688 clk_name, PTR_ERR(clk)); in sunxi_mux_clk_setup()
694 __func__, clk_name); in sunxi_mux_clk_setup()
787 const char *clk_name = node->name; in sunxi_divider_clk_setup() local
799 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_divider_clk_setup()
805 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, in sunxi_divider_clk_setup()
811 __func__, clk_name, PTR_ERR(clk)); in sunxi_divider_clk_setup()
817 __func__, clk_name); in sunxi_divider_clk_setup()
[all …]
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| D | clk-a10-codec.c | 26 const char *clk_name = node->name, *parent_name; in sun4i_codec_clk_setup() local
33 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_codec_clk_setup()
36 clk = clk_register_gate(NULL, clk_name, parent_name, in sun4i_codec_clk_setup()
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| D | clk-sun4i-tcon-ch1.c | 235 const char *clk_name = node->name; in tcon_ch1_setup() local
243 of_property_read_string(node, "clock-output-names", &clk_name); in tcon_ch1_setup()
247 pr_err("%s: Could not map the clock registers\n", clk_name); in tcon_ch1_setup()
253 pr_err("%s Could not retrieve the parents\n", clk_name); in tcon_ch1_setup()
261 init.name = clk_name; in tcon_ch1_setup()
273 pr_err("%s: Couldn't register the clock\n", clk_name); in tcon_ch1_setup()
279 pr_err("%s: Couldn't register our clock provider\n", clk_name); in tcon_ch1_setup()
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| D | clk-sun6i-apb0.c | 34 const char *clk_name = np->name; in sun6i_a31_apb0_clk_probe() local
49 of_property_read_string(np, "clock-output-names", &clk_name); in sun6i_a31_apb0_clk_probe()
51 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, in sun6i_a31_apb0_clk_probe()
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| D | clk-a10-hosc.c | 31 const char *clk_name = node->name; in sun4i_osc_clk_setup() local
45 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_osc_clk_setup()
53 clk = clk_register_composite(NULL, clk_name, in sun4i_osc_clk_setup()
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| D | clk-a20-gmac.c | 65 const char *clk_name = node->name; in sun7i_a20_gmac_clk_setup() local
69 if (of_property_read_string(node, "clock-output-names", &clk_name)) in sun7i_a20_gmac_clk_setup()
98 clk = clk_register_composite(NULL, clk_name, in sun7i_a20_gmac_clk_setup()
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| /Linux-v4.19/drivers/clk/h8300/ |
| D | clk-div.c | 19 const char *clk_name = node->name; in h8300_div_clk_setup() local
27 pr_err("%s: no parent found\n", clk_name); in h8300_div_clk_setup()
33 pr_err("%s: failed to map divide register\n", clk_name); in h8300_div_clk_setup()
42 hw = clk_hw_register_divider(NULL, clk_name, parent_name, in h8300_div_clk_setup()
50 __func__, clk_name, PTR_ERR(hw)); in h8300_div_clk_setup()
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| D | clk-h8s2678.c | 88 const char *clk_name = node->name; in h8s2678_pll_clk_setup() local
96 pr_err("%s: no parent found\n", clk_name); in h8s2678_pll_clk_setup()
107 pr_err("%s: failed to map divide register\n", clk_name); in h8s2678_pll_clk_setup()
113 pr_err("%s: failed to map multiply register\n", clk_name); in h8s2678_pll_clk_setup()
118 init.name = clk_name; in h8s2678_pll_clk_setup()
128 __func__, clk_name, ret); in h8s2678_pll_clk_setup()
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| /Linux-v4.19/drivers/clk/pxa/ |
| D | clk-pxa.h | 23 #define MUX_RO_RATE_RO_OPS(name, clk_name) \ argument
35 return clk_register_composite(NULL, clk_name, \
43 #define RATE_RO_OPS(name, clk_name) \ argument
50 return clk_register_composite(NULL, clk_name, \
58 #define RATE_OPS(name, clk_name) \ argument
67 return clk_register_composite(NULL, clk_name, \
75 #define MUX_OPS(name, clk_name, flags) \ argument
84 return clk_register_composite(NULL, clk_name, \
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| /Linux-v4.19/drivers/staging/clocking-wizard/ |
| D | clk-xlnx-clock-wizard.c | 136 const char *clk_name; in clk_wzrd_probe() local
197 clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); in clk_wzrd_probe()
198 if (!clk_name) { in clk_wzrd_probe()
203 &pdev->dev, clk_name, in clk_wzrd_probe()
206 kfree(clk_name); in clk_wzrd_probe()
216 clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); in clk_wzrd_probe()
217 if (!clk_name) { in clk_wzrd_probe()
223 &pdev->dev, clk_name, in clk_wzrd_probe()
247 clkout_name, clk_name, 0, 1, reg); in clk_wzrd_probe()
260 kfree(clk_name); in clk_wzrd_probe()
[all …]
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| /Linux-v4.19/arch/m68k/include/asm/ |
| D | mcfclk.h | 33 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \ argument
35 .name = clk_name, \
44 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \ argument
46 .name = clk_name, \
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| /Linux-v4.19/drivers/clk/mvebu/ |
| D | clk-cpu.c | 38 const char *clk_name; member
200 char *clk_name = kzalloc(5, GFP_KERNEL); in of_cpu_clk_setup() local
203 if (WARN_ON(!clk_name)) in of_cpu_clk_setup()
210 sprintf(clk_name, "cpu%d", cpu); in of_cpu_clk_setup()
213 cpuclk[cpu].clk_name = clk_name; in of_cpu_clk_setup()
220 init.name = cpuclk[cpu].clk_name; in of_cpu_clk_setup()
239 kfree(cpuclk[ncpus].clk_name); in of_cpu_clk_setup()
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| /Linux-v4.19/drivers/clk/ |
| D | clk-nspire.c | 73 const char *clk_name = node->name; in nspire_ahbdiv_setup() local
85 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_ahbdiv_setup()
88 hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0, in nspire_ahbdiv_setup()
115 const char *clk_name = node->name; in nspire_clk_setup() local
126 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_clk_setup()
128 hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, in nspire_clk_setup()
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| D | clk-pwm.c | 63 const char *clk_name; in clk_pwm_probe() local
99 clk_name = node->name; in clk_pwm_probe()
100 of_property_read_string(node, "clock-output-names", &clk_name); in clk_pwm_probe()
102 init.name = clk_name; in clk_pwm_probe()
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| D | clk-xgene.c | 186 const char *clk_name = np->full_name; in xgene_pllclk_init() local
196 of_property_read_string(np, "clock-output-names", &clk_name); in xgene_pllclk_init()
198 clk_name, of_clk_get_parent_name(np, 0), in xgene_pllclk_init()
203 clk_register_clkdev(clk, clk_name, NULL); in xgene_pllclk_init()
204 pr_debug("Add %s clock PLL\n", clk_name); in xgene_pllclk_init()
395 const char *clk_name = np->full_name; in xgene_pmdclk_init() local
418 of_property_read_string(np, "clock-output-names", &clk_name); in xgene_pmdclk_init()
423 clk = xgene_register_clk_pmd(NULL, clk_name, in xgene_pmdclk_init()
430 clk_register_clkdev(clk, clk_name, NULL); in xgene_pmdclk_init()
431 pr_debug("Add %s clock\n", clk_name); in xgene_pmdclk_init()
[all …]
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| /Linux-v4.19/drivers/clk/keystone/ |
| D | pll.c | 258 const char *clk_name = node->name; in of_pll_div_clk_init() local
260 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_div_clk_init()
286 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, in of_pll_div_clk_init()
291 pr_err("%s: error registering divider %s\n", __func__, clk_name); in of_pll_div_clk_init()
307 const char *clk_name = node->name; in of_pll_mux_clk_init() local
309 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_mux_clk_init()
332 clk = clk_register_mux(NULL, clk_name, (const char **)&parents, in of_pll_mux_clk_init()
338 pr_err("%s: error registering mux %s\n", __func__, clk_name); in of_pll_mux_clk_init()
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| /Linux-v4.19/drivers/clk/ti/ |
| D | fixed-factor.c | 39 const char *clk_name = node->name; in of_ti_fixed_factor_clk_setup() local
59 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags, in of_ti_fixed_factor_clk_setup()
65 ti_clk_add_alias(NULL, clk, clk_name); in of_ti_fixed_factor_clk_setup()
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| D | clockdomain.c | 110 const char *clk_name; in omap2_init_clk_clkdm() local
115 clk_name = __clk_get_name(hw->clk); in omap2_init_clk_clkdm()
120 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
124 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
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| /Linux-v4.19/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_10nm.c | 630 char clk_name[32], parent[32], vco_name[32]; in pll_10nm_register() local
663 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id); in pll_10nm_register()
666 hw = clk_hw_register_divider(dev, clk_name, in pll_10nm_register()
676 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id); in pll_10nm_register()
680 hw = clk_hw_register_divider(dev, clk_name, parent, in pll_10nm_register()
691 snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id); in pll_10nm_register()
695 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
703 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id); in pll_10nm_register()
706 hw = clk_hw_register_fixed_factor(dev, clk_name, parent, in pll_10nm_register()
713 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); in pll_10nm_register()
[all …]
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| /Linux-v4.19/arch/arm/mach-omap2/ |
| D | pm.c | 88 static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, in omap2_set_init_voltage() argument
97 if (!vdd_name || !clk_name || !oh_name) { in omap2_set_init_voltage()
124 clk = clk_get(NULL, clk_name); in omap2_set_init_voltage()
126 pr_err("%s: unable to get clk %s\n", __func__, clk_name); in omap2_set_init_voltage()
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| /Linux-v4.19/drivers/clk/socfpga/ |
| D | clk-periph-a10.c | 76 const char *clk_name = node->name; in __socfpga_periph_init() local
106 of_property_read_string(node, "clock-output-names", &clk_name); in __socfpga_periph_init()
108 init.name = clk_name; in __socfpga_periph_init()
125 clk_name); in __socfpga_periph_init()
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