Searched refs:clk_mul (Results 1 – 5 of 5) sorted by relevance
158 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets() local171 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; in sdhci_at91_set_clks_presets()172 gck_rate = clk_base * 1000000 * (clk_mul + 1); in sdhci_at91_set_clks_presets()187 clk_mul = real_gck_rate / (clk_base * 1000000) - 1; in sdhci_at91_set_clks_presets()189 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & in sdhci_at91_set_clks_presets()198 clk_mul, real_gck_rate); in sdhci_at91_set_clks_presets()
1400 int real_div = div, clk_mul = 1; in sdhci_calc_clk() local1412 if (host->clk_mul && in sdhci_calc_clk()1416 clk_mul = host->clk_mul; in sdhci_calc_clk()1427 if (host->clk_mul) { in sdhci_calc_clk()1429 if ((host->max_clk * host->clk_mul / div) in sdhci_calc_clk()1433 if ((host->max_clk * host->clk_mul / div) <= clock) { in sdhci_calc_clk()1440 clk_mul = host->clk_mul; in sdhci_calc_clk()1451 if (!host->clk_mul || switch_base_clk) { in sdhci_calc_clk()1480 *actual_clock = (host->max_clk * clk_mul) / real_div; in sdhci_calc_clk()3642 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> in sdhci_setup_host()[all …]
494 unsigned int clk_mul; /* Clock Muliplier value */ member
165 struct clk_hw clk_mul; member281 container_of(hw, struct vc5_driver_data, clk_mul); in vc5_dbl_recalc_rate()304 container_of(hw, struct vc5_driver_data, clk_mul); in vc5_dbl_set_rate()777 vc5->clk_mul.init = &init; in vc5_probe()778 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); in vc5_probe()
87 const unsigned long clk_mul = in rcar_gyroadc_hw_init() local89 unsigned long clk_len = clk_mhz * clk_mul; in rcar_gyroadc_hw_init()
