Searched refs:clk_hw_get_flags (Results 1 – 25 of 25) sorted by relevance
146 if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) { in of_ti_clockdomain_setup()
183 if (clk_hw_get_flags(hw) & CLK_IS_BASIC) in omap2_init_clk_hw_omap_clocks()
734 } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC)); in omap3_find_clkoutx2_dpll()
185 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in ti_clk_divider_bestdiv()
99 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in ccu_gate_round_rate()
93 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { in ccu_mux_helper_determine_rate()
61 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in __bestmult()
43 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_factor_round_rate()
290 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_divider_bestdiv()355 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in divider_ro_round_rate_parent()
79 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { in clk_composite_determine_rate()
671 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_msynth_round_rate()1050 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_clkout_round_rate()
310 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in cdce706_divider_round_rate()
367 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_apb_mul_round_rate()
390 unsigned long clk_hw_get_flags(const struct clk_hw *hw) in clk_hw_get_flags() function394 EXPORT_SYMBOL_GPL(clk_hw_get_flags);
126 if (clk_hw_get_flags(clk) & CLK_SET_RATE_PARENT) in sun9i_a80_cpus_clk_determine_rate()
109 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in clk_factors_determine_rate()
59 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) in sclk_div_bestdiv()
80 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_val_best()
47 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_half_divider_bestdiv()
122 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in flexgen_round_rate()
784 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
147 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in davinci_pll_determine_rate()
204 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_determine_rate()
821 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in clk_alpha_pll_postdiv_round_ro_rate()
423 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_determine_rate()
