Searched refs:clk_csr (Results 1 – 11 of 11) sorted by relevance
93 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()133 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write()175 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read()218 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write()
245 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set()247 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set()249 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set()251 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set()253 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set()255 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set()257 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set()262 priv->clk_csr = 0x03; in stmmac_clk_csr_set()264 priv->clk_csr = 0x02; in stmmac_clk_csr_set()266 priv->clk_csr = 0x01; in stmmac_clk_csr_set()[all …]
168 int clk_csr; member
72 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
47 int clk_csr; member
156 int clk_csr; member
179 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()181 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()183 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()185 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()187 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()189 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()2158 if (!priv->plat->clk_csr) in sxgbe_drv_probe()2161 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
51 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
492 int clk_csr; member
486 unsigned int clk_csr; in qat_hal_clr_reset() local502 clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE); in qat_hal_clr_reset()503 clk_csr |= handle->hal_handle->ae_mask << 0; in qat_hal_clr_reset()504 clk_csr |= handle->hal_handle->slice_mask << 20; in qat_hal_clr_reset()505 SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); in qat_hal_clr_reset()
123 int clk_csr;159 o clk_csr: fixed CSR Clock range selection.
