Home
last modified time | relevance | path

Searched refs:clear_state_gpu_addr (Results 1 – 9 of 9) sorted by relevance

/Linux-v4.19/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2427 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2437 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2849 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2956 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2964 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
Dgfx_v9_0.c924 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_rlc_fini()
950 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_rlc_init()
1002 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v9_0_csb_vram_pin()
1652 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v9_0_sw_fini()
1880 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
1882 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
Dgfx_v7_0.c3336 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_rlc_init()
3964 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3965 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4626 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
Damdgpu.h712 uint64_t clear_state_gpu_addr; member
Dgfx_v8_0.c1393 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_rlc_init()
2213 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
3994 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3996 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
/Linux-v4.19/drivers/gpu/drm/radeon/
Devergreen.c4263 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4282 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4289 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4409 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
Dsi.c5285 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5782 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5788 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
Dradeon.h998 uint64_t clear_state_gpu_addr; member
Dcik.c6629 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6630 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()