Searched refs:cik (Results 1 – 6 of 6) sorted by relevance
2331 u32 *tile = rdev->config.cik.tile_mode_array; in cik_tiling_mode_table_init()2332 u32 *macrotile = rdev->config.cik.macrotile_mode_array; in cik_tiling_mode_table_init()2334 ARRAY_SIZE(rdev->config.cik.tile_mode_array); in cik_tiling_mode_table_init()2336 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array); in cik_tiling_mode_table_init()2339 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()2340 rdev->config.cik.max_shader_engines; in cik_tiling_mode_table_init()2342 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_tiling_mode_table_init()2355 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3139 rdev->config.cik.backend_enable_mask = enabled_rbs; in cik_setup_rb()3188 rdev->config.cik.max_shader_engines = 2; in cik_gpu_init()[all …]
303 *value = rdev->config.cik.tile_config; in radeon_info_ioctl()357 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()358 rdev->config.cik.max_shader_engines; in radeon_info_ioctl()377 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()397 *value = rdev->config.cik.backend_map; in radeon_info_ioctl()426 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()452 *value = rdev->config.cik.max_shader_engines; in radeon_info_ioctl()464 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()499 value = rdev->config.cik.tile_mode_array; in radeon_info_ioctl()511 value = rdev->config.cik.macrotile_mode_array; in radeon_info_ioctl()[all …]
76 si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
1288 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()1344 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
793 struct cik_irq_stat_regs cik; member2203 struct cik_asic cik; member
58 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
