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Searched refs:ccm_base (Results 1 – 7 of 7) sorted by relevance

/Linux-v4.19/drivers/clk/imx/
Dclk-vf610.c18 #define CCM_CCR (ccm_base + 0x00)
19 #define CCM_CSR (ccm_base + 0x04)
20 #define CCM_CCSR (ccm_base + 0x08)
21 #define CCM_CACRR (ccm_base + 0x0c)
22 #define CCM_CSCMR1 (ccm_base + 0x10)
23 #define CCM_CSCDR1 (ccm_base + 0x14)
24 #define CCM_CSCDR2 (ccm_base + 0x18)
25 #define CCM_CSCDR3 (ccm_base + 0x1c)
26 #define CCM_CSCMR2 (ccm_base + 0x20)
27 #define CCM_CSCDR4 (ccm_base + 0x24)
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Dclk-imx51-imx53.c34 #define MXC_CCM_CCR (ccm_base + 0x00)
35 #define MXC_CCM_CCDR (ccm_base + 0x04)
36 #define MXC_CCM_CSR (ccm_base + 0x08)
37 #define MXC_CCM_CCSR (ccm_base + 0x0c)
38 #define MXC_CCM_CACRR (ccm_base + 0x10)
39 #define MXC_CCM_CBCDR (ccm_base + 0x14)
40 #define MXC_CCM_CBCMR (ccm_base + 0x18)
41 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
42 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
43 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)
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Dclk-imx6q.c238 static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base) in imx6q_mmdc_ch1_mask_handshake() argument
242 reg = readl_relaxed(ccm_base + CCM_CCDR); in imx6q_mmdc_ch1_mask_handshake()
244 writel_relaxed(reg, ccm_base + CCM_CCDR); in imx6q_mmdc_ch1_mask_handshake()
252 static void mmdc_ch1_disable(void __iomem *ccm_base) in mmdc_ch1_disable() argument
266 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_disable()
268 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_disable()
271 static void mmdc_ch1_reenable(void __iomem *ccm_base) in mmdc_ch1_reenable() argument
276 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
278 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
312 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) in init_ldb_clks() argument
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Dclk-imx6sl.c104 static void __iomem *ccm_base; variable
131 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
172 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()
173 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()
175 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()
177 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) in imx6sl_set_wait_clk()
290 ccm_base = base; in imx6sl_clocks_init()
Dclk-imx25.c54 #define ccm(x) (ccm_base + (x))
99 static int __init __mx25_clocks_init(void __iomem *ccm_base) in __mx25_clocks_init() argument
101 BUG_ON(!ccm_base); in __mx25_clocks_init()
/Linux-v4.19/arch/arm/mach-imx/
Dpm-imx6.c67 static void __iomem *ccm_base; variable
230 struct imx6_pm_base ccm_base; member
239 u32 val = readl_relaxed(ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
244 writel_relaxed(val, ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
258 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
261 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
264 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
267 writel(val, ccm_base + CCR); in imx6_enable_rbc()
285 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()
288 writel_relaxed(val, ccm_base + CLPCR); in imx6q_enable_wb()
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Dpm-imx5.c139 static void __iomem *ccm_base; variable
158 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()
200 imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); in mx5_cpu_lp_set()
392 ccm_base = ioremap(data->ccm_addr, SZ_16K); in imx5_pm_common_init()
395 WARN_ON(!ccm_base || !cortex_base || !gpc_base); in imx5_pm_common_init()