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Searched refs:cacheline_size (Results 1 – 11 of 11) sorted by relevance

/Linux-v4.19/tools/perf/util/
Dsort.h196 return (address & ~(cacheline_size() - 1)); in cl_address()
202 return (address & (cacheline_size() - 1)); in cl_offset()
Dutil.h46 int __pure cacheline_size(void);
Dutil.c52 int cacheline_size(void) in cacheline_size() function
Dsort.c2548 if (sd->entry == &sort_mem_dcacheline && cacheline_size() == 0) in sort_dimension__add()
2594 if (!cacheline_size() && !strncasecmp(tok, "dcacheline", strlen(tok))) in setup_sort_list()
/Linux-v4.19/drivers/gpu/drm/amd/amdkfd/
Dkfd_topology.h112 uint32_t cacheline_size; member
Dkfd_crat.c315 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
Dkfd_topology.c321 sysfs_show_32bit_prop(buffer, "cache_line_size", cache->cacheline_size); in kfd_cache_show()
/Linux-v4.19/drivers/pci/
Dpci.c4077 u8 cacheline_size; in pci_set_cacheline_size() local
4084 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
4085 if (cacheline_size >= pci_cache_line_size && in pci_set_cacheline_size()
4086 (cacheline_size % pci_cache_line_size) == 0) in pci_set_cacheline_size()
4092 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
4093 if (cacheline_size == pci_cache_line_size) in pci_set_cacheline_size()
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_pm.c566 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
573 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
580 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
587 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
594 .cacheline_size = I915_FIFO_LINE_SIZE,
601 .cacheline_size = I915_FIFO_LINE_SIZE,
608 .cacheline_size = I915_FIFO_LINE_SIZE,
615 .cacheline_size = I830_FIFO_LINE_SIZE,
622 .cacheline_size = I830_FIFO_LINE_SIZE,
629 .cacheline_size = I830_FIFO_LINE_SIZE,
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Dintel_drv.h985 u8 cacheline_size; member
/Linux-v4.19/drivers/net/ethernet/broadcom/
Dtg3.c17100 int cacheline_size; in tg3_calc_dma_bndry() local
17106 cacheline_size = 1024; in tg3_calc_dma_bndry()
17108 cacheline_size = (int) byte * 4; in tg3_calc_dma_bndry()
17148 switch (cacheline_size) { in tg3_calc_dma_bndry()
17173 switch (cacheline_size) { in tg3_calc_dma_bndry()
17190 switch (cacheline_size) { in tg3_calc_dma_bndry()