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/Linux-v4.19/tools/perf/Documentation/
Dperf-c2c.txt20 you to track down the cacheline contentions.
79 Specify sorting fields for single cacheline display.
113 The perf c2c record command setup options related to HITM cacheline analysis
140 - sort all the data based on the cacheline address
141 - store access details for each cacheline
147 2) offsets details for each cacheline
149 For each cacheline in the 1) list we display following data:
153 - zero based index to identify the cacheline
156 - cacheline address (hex number)
162 - cacheline percentage of all Remote/Local HITM accesses
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Dtips.txt36 To report cacheline events from previous recording: perf c2c report
Dperf-report.txt140 - dcacheline: the cacheline the data address is on at the time of the sample
/Linux-v4.19/drivers/soc/qcom/
Dsmem.c160 __le32 cacheline; member
276 size_t cacheline[SMEM_HOST_COUNT]; member
293 size_t cacheline) in phdr_to_first_cached_entry() argument
298 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*e), cacheline); in phdr_to_first_cached_entry()
327 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
331 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
519 size_t cacheline, in qcom_smem_get_private() argument
545 e = phdr_to_first_cached_entry(phdr, cacheline); in qcom_smem_get_private()
560 e = cached_entry_next(e, cacheline); in qcom_smem_get_private()
603 cacheln = __smem->cacheline[host]; in qcom_smem_get()
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/Linux-v4.19/include/asm-generic/
Dvmlinux.lds.h858 #define PERCPU_INPUT(cacheline) \ argument
863 . = ALIGN(cacheline); \
865 . = ALIGN(cacheline); \
895 #define PERCPU_VADDR(cacheline, vaddr, phdr) \ argument
898 PERCPU_INPUT(cacheline) \
914 #define PERCPU_SECTION(cacheline) \ argument
918 PERCPU_INPUT(cacheline) \
940 #define RW_DATA_SECTION(cacheline, pagealigned, inittask) \ argument
946 CACHELINE_ALIGNED_DATA(cacheline) \
947 READ_MOSTLY_DATA(cacheline) \
/Linux-v4.19/drivers/md/bcache/
Dbset.c530 unsigned int cacheline, in cacheline_to_bkey() argument
533 return ((void *) t->data) + cacheline * BSET_CACHELINE + offset * 8; in cacheline_to_bkey()
542 unsigned int cacheline, in bkey_to_cacheline_offset() argument
545 return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); in bkey_to_cacheline_offset()
562 static struct bkey *table_to_bkey(struct bset_tree *t, unsigned int cacheline) in table_to_bkey() argument
564 return cacheline_to_bkey(t, cacheline, t->prev[cacheline]); in table_to_bkey()
699 unsigned int j, cacheline = 1; in bch_bset_build_written_tree() local
720 while (bkey_to_cacheline(t, k) < cacheline) in bch_bset_build_written_tree()
724 t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); in bch_bset_build_written_tree()
/Linux-v4.19/drivers/lightnvm/
Dpblk-rb.c97 entry->cacheline = pblk_cacheline_to_addr(init_entry++); in pblk_rb_init()
103 entry->cacheline = pblk_cacheline_to_addr(init_entry++); in pblk_rb_init()
226 entry->cacheline); in __pblk_rb_update_l2p()
318 pblk_update_map_cache(pblk, w_ctx.lba, entry->cacheline); in pblk_rb_write_entry_user()
342 if (!pblk_update_map_gc(pblk, w_ctx.lba, entry->cacheline, line, paddr)) in pblk_rb_write_entry_gc()
Dpblk-write.c162 if (!pblk_ppa_comp(ppa_l2p, entry->cacheline)) in pblk_prepare_resubmit()
Dpblk.h157 struct ppa_addr cacheline; /* Cacheline for this entry */ member
/Linux-v4.19/drivers/gpu/drm/i915/
Dintel_ringbuffer.h876 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
877 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) && in assert_ring_tail_valid()
879 #undef cacheline in assert_ring_tail_valid()
/Linux-v4.19/scripts/gcc-plugins/
DKconfig132 bool "Use cacheline-aware structure randomization"
137 best effort at restricting randomization to cacheline-sized
/Linux-v4.19/kernel/
DKconfig.hz13 contention and cacheline bounces as a result of timer interrupts.
/Linux-v4.19/Documentation/sparc/
Dadi.txt34 size is same as cacheline size which is 64 bytes. A task that sets ADI
98 the corresponding cacheline, a memory corruption trap occurs. By
117 the corresponding cacheline, a memory corruption trap occurs. If
/Linux-v4.19/arch/sparc/kernel/
Dprom_irqtrans.c355 static unsigned char cacheline[64] in tomatillo_wsync_handler() local
366 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
Dcherrs.S203 sub %g1, %g2, %g1 ! Move down 1 cacheline
215 subcc %g1, %g2, %g1 ! Next cacheline
/Linux-v4.19/arch/parisc/kernel/
Dperf_asm.S145 ; Cacheline start (32-byte cacheline)
158 ; Cacheline start (32-byte cacheline)
/Linux-v4.19/Documentation/locking/
Dmutex-design.txt52 cacheline bouncing that common test-and-set spinlock implementations
/Linux-v4.19/Documentation/driver-api/
Dedac.rst46 lockstep is enabled, the cacheline is doubled, but it generally brings
/Linux-v4.19/Documentation/networking/
Dena.txt24 and CPU cacheline optimized data placement.
/Linux-v4.19/drivers/edac/
DKconfig96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
/Linux-v4.19/Documentation/
DDMA-API-HOWTO.txt137 buffers were cacheline-aligned. Without that, you'd see cacheline
Dmemory-barriers.txt2740 cacheline over to the accessing CPU and propagate the effects upon conflict.
2805 displace a dirty cacheline or to do a speculative load;
2839 cacheline holding p may get updated in one of the second CPU's caches whilst
2840 the update to the cacheline holding v is delayed in the other of the second
2913 obscure the fact that RAM has been updated, until at such time as the cacheline
/Linux-v4.19/drivers/scsi/aic7xxx/
Daic7xxx.seq754 * We fetch a "cacheline aligned" and sized amount of data
758 * cacheline size is unknown.
795 * If the ending address is on a cacheline boundary,
/Linux-v4.19/Documentation/filesystems/
Dpath-lookup.txt32 common path elements causes lock and cacheline queueing.
/Linux-v4.19/drivers/char/
DKconfig153 of threads across a large system which avoids bouncing a cacheline

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