c7 (reference) in projects: Linux-v4.19

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Searched refs:c7 (Results 1 – 25 of 89) sorted by relevance

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/Linux-v4.19/arch/arm/mm/
D	proc-arm1020.S	99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 159 mcr p15, 0, ip, c7, c10, 4 @ drain WB 167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 169 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-mohawk.S	75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c7, c10, 4 @ drain WB 77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 130 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
D	proc-arm926.S	83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 84 mcr p15, 0, ip, c7, c10, 4 @ drain WB 86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	cache-fa.S	48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 73 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 74 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 101 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-arm925.S	123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-arm920.S	91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	cache-v6.S	43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 137 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
D	proc-arm922.S	93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c7, c10, 4 @ drain WB 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm1020e.S	99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
D	proc-arm946.S	`61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 118 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache 119 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]`
D	proc-arm1026.S	90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm1022.S	90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-fa526.S	63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 92 mcr p15, 0, r0, c7, c10, 4 @ drain WB 109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 115 mcr p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-feroceon.S	82 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 171 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-xsc3.S	71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier 178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line [all …]
D	proc-xscale.S	94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 159 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 194 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 218 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 219 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer [all …]
D	cache-v4wb.S	62 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 81 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 98 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 115 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 120 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 121 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 126 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 167 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 168 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 173 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm940.S	`54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 56 mcr p15, 0, ip, c7, c10, 4 @ drain WB 70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 124 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index [all …]`
D	proc-arm720.S	`80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)`
D	tlb-fa.S	`43 mcr p15, 0, r3, c7, c10, 4 @ drain WB 46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 56 mcr p15, 0, r3, c7, c10, 4 @ drain WB 59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 63 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 64 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)`
D	proc-sa110.S	68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 120 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 157 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 158 mcr p15, 0, r0, c7, c10, 4 @ drain WB 165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 166 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
D	cache-v4.S	`43 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 62 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache 118 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache`
D	proc-sa1100.S	76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 169 mcr p15, 0, r0, c7, c10, 4 @ drain WB 188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs 189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache 204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 [all …]
D	cache-v4wt.S	`51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
/Linux-v4.19/arch/arm/include/asm/hardware/
D	cp14.h	57 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0) 72 #define RCP14_DBGBVR7() MRC14(0, c0, c7, 4) 88 #define RCP14_DBGBCR7() MRC14(0, c0, c7, 5) 104 #define RCP14_DBGWVR7() MRC14(0, c0, c7, 6) 120 #define RCP14_DBGWCR7() MRC14(0, c0, c7, 7) 137 #define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1) 152 #define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4) 153 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6) 154 #define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6) 155 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6) [all …]

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