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/Linux-v4.19/arch/unicore32/mm/
Dcache-ucv2.S34 movc p0.c5, r0, #14 @ Dcache flush all
38 movc p0.c5, r0, #20 @ Icache invalidate all
73 movc p0.c5, ip, #14 @ Dcache flush all
77 movc p0.c5, ip, #20 @ Icache invalidate all
113 103: movc p0.c5, r10, #11 @ Dcache clean line of R10
123 movc p0.c5, ip, #10 @ Dcache clean all
127 movc p0.c5, ip, #20 @ Icache invalidate all
140 movc p0.c5, ip, #14 @ Dcache flush all
167 1: movc p0.c5, r10, #11 @ Dcache clean line of R10
176 movc p0.c5, ip, #10 @ Dcache clean all
[all …]
Dproc-ucv2.S40 movc p0.c5, ip, #28 @ Cache invalidate all
78 3: movc p0.c5, r10, #11 @ clean D entry
87 movc p0.c5, ip, #10 @ Dcache clean all
125 movc p0.c5, r2, #11 @ Dcache clean line
129 movc p0.c5, ip, #10 @ Dcache clean all
/Linux-v4.19/arch/arm/mm/
Dcache-fa.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
74 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
102 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
138 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
Dproc-arm946.S61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
118 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
Dcache-v4wt.S51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
Dproc-arm940.S54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
285 mcr p15, 0, r0, c6, c5, 0
291 mcr p15, 0, r0, c6, c5, 1
323 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
324 mcr p15, 0, r0, c5, c0, 1
Dproc-xsc3.S152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
205 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
207 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
234 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
255 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
Dproc-fa526.S113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
116 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
153 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
155 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
Dproc-mohawk.S105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
331 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
374 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
Dproc-arm925.S157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
417 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dproc-arm926.S123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
243 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
378 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dtlb-v6.S51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
Dcache-v4wb.S62 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
81 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
Dproc-xscale.S151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
194 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
240 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
247 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
271 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
288 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
293 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
314 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
476 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
Dproc-arm922.S124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
369 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dtlb-v4wb.S41 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
Dtlb-v4wbi.S43 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
Dproc-arm920.S122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
Dproc-v6.S64 mcr p15, 0, r1, c7, c5, 4 @ ISB
105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, ip, c7, c5, 4 @ ISB
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
/Linux-v4.19/arch/arm/include/asm/
Dkvm_hyp.h60 #define DFSR __ACCESS_CP15(c5, 0, c0, 0)
61 #define IFSR __ACCESS_CP15(c5, 0, c0, 1)
62 #define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
63 #define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
64 #define HSR __ACCESS_CP15(c5, 4, c2, 0)
72 #define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1)
Dcp15.h68 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
69 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/Linux-v4.19/arch/arm/include/asm/hardware/
Dcp14.h55 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
70 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
86 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
102 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
118 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
135 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
150 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
160 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
175 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
191 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
/Linux-v4.19/arch/unicore32/boot/compressed/
Dhead.S87 movc p0.c5, r0, #28 @ cache invalidate all
143 movc p0.c5, r0, #14 @ flush dcache
145 movc p0.c5, r0, #20 @ icache invalidate all
/Linux-v4.19/arch/arm/boot/compressed/
Dhead.S35 mcr p14, 0, \ch, c0, c5, 0
643 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
644 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
648 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
658 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
671 mcr p15, 0, r0, c5, c0, 0 @ access permission
800 mcr p15, 0, r0, c7, c5, 4 @ ISB
804 mcr p15, 0, r0, c7, c5, 4 @ ISB
1068 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1104 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
[all …]

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