1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
3 *
4 * Description: CoreSight Trace Memory Controller driver
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/device.h>
11 #include <linux/io.h>
12 #include <linux/err.h>
13 #include <linux/fs.h>
14 #include <linux/miscdevice.h>
15 #include <linux/property.h>
16 #include <linux/uaccess.h>
17 #include <linux/slab.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/spinlock.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/of.h>
22 #include <linux/coresight.h>
23 #include <linux/amba/bus.h>
24
25 #include "coresight-priv.h"
26 #include "coresight-tmc.h"
27
tmc_wait_for_tmcready(struct tmc_drvdata * drvdata)28 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
29 {
30 /* Ensure formatter, unformatter and hardware fifo are empty */
31 if (coresight_timeout(drvdata->base,
32 TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
33 dev_err(drvdata->dev,
34 "timeout while waiting for TMC to be Ready\n");
35 }
36 }
37
tmc_flush_and_stop(struct tmc_drvdata * drvdata)38 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
39 {
40 u32 ffcr;
41
42 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
43 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
44 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
45 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
46 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
47 /* Ensure flush completes */
48 if (coresight_timeout(drvdata->base,
49 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
50 dev_err(drvdata->dev,
51 "timeout while waiting for completion of Manual Flush\n");
52 }
53
54 tmc_wait_for_tmcready(drvdata);
55 }
56
tmc_enable_hw(struct tmc_drvdata * drvdata)57 void tmc_enable_hw(struct tmc_drvdata *drvdata)
58 {
59 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
60 }
61
tmc_disable_hw(struct tmc_drvdata * drvdata)62 void tmc_disable_hw(struct tmc_drvdata *drvdata)
63 {
64 writel_relaxed(0x0, drvdata->base + TMC_CTL);
65 }
66
tmc_read_prepare(struct tmc_drvdata * drvdata)67 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
68 {
69 int ret = 0;
70
71 switch (drvdata->config_type) {
72 case TMC_CONFIG_TYPE_ETB:
73 case TMC_CONFIG_TYPE_ETF:
74 ret = tmc_read_prepare_etb(drvdata);
75 break;
76 case TMC_CONFIG_TYPE_ETR:
77 ret = tmc_read_prepare_etr(drvdata);
78 break;
79 default:
80 ret = -EINVAL;
81 }
82
83 if (!ret)
84 dev_info(drvdata->dev, "TMC read start\n");
85
86 return ret;
87 }
88
tmc_read_unprepare(struct tmc_drvdata * drvdata)89 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
90 {
91 int ret = 0;
92
93 switch (drvdata->config_type) {
94 case TMC_CONFIG_TYPE_ETB:
95 case TMC_CONFIG_TYPE_ETF:
96 ret = tmc_read_unprepare_etb(drvdata);
97 break;
98 case TMC_CONFIG_TYPE_ETR:
99 ret = tmc_read_unprepare_etr(drvdata);
100 break;
101 default:
102 ret = -EINVAL;
103 }
104
105 if (!ret)
106 dev_info(drvdata->dev, "TMC read end\n");
107
108 return ret;
109 }
110
tmc_open(struct inode * inode,struct file * file)111 static int tmc_open(struct inode *inode, struct file *file)
112 {
113 int ret;
114 struct tmc_drvdata *drvdata = container_of(file->private_data,
115 struct tmc_drvdata, miscdev);
116
117 ret = tmc_read_prepare(drvdata);
118 if (ret)
119 return ret;
120
121 nonseekable_open(inode, file);
122
123 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
124 return 0;
125 }
126
tmc_get_sysfs_trace(struct tmc_drvdata * drvdata,loff_t pos,size_t len,char ** bufpp)127 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
128 loff_t pos, size_t len, char **bufpp)
129 {
130 switch (drvdata->config_type) {
131 case TMC_CONFIG_TYPE_ETB:
132 case TMC_CONFIG_TYPE_ETF:
133 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
134 case TMC_CONFIG_TYPE_ETR:
135 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
136 }
137
138 return -EINVAL;
139 }
140
tmc_read(struct file * file,char __user * data,size_t len,loff_t * ppos)141 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
142 loff_t *ppos)
143 {
144 char *bufp;
145 ssize_t actual;
146 struct tmc_drvdata *drvdata = container_of(file->private_data,
147 struct tmc_drvdata, miscdev);
148 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
149 if (actual <= 0)
150 return 0;
151
152 if (copy_to_user(data, bufp, actual)) {
153 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
154 return -EFAULT;
155 }
156
157 *ppos += actual;
158 dev_dbg(drvdata->dev, "%zu bytes copied\n", actual);
159
160 return actual;
161 }
162
tmc_release(struct inode * inode,struct file * file)163 static int tmc_release(struct inode *inode, struct file *file)
164 {
165 int ret;
166 struct tmc_drvdata *drvdata = container_of(file->private_data,
167 struct tmc_drvdata, miscdev);
168
169 ret = tmc_read_unprepare(drvdata);
170 if (ret)
171 return ret;
172
173 dev_dbg(drvdata->dev, "%s: released\n", __func__);
174 return 0;
175 }
176
177 static const struct file_operations tmc_fops = {
178 .owner = THIS_MODULE,
179 .open = tmc_open,
180 .read = tmc_read,
181 .release = tmc_release,
182 .llseek = no_llseek,
183 };
184
tmc_get_memwidth(u32 devid)185 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
186 {
187 enum tmc_mem_intf_width memwidth;
188
189 /*
190 * Excerpt from the TRM:
191 *
192 * DEVID::MEMWIDTH[10:8]
193 * 0x2 Memory interface databus is 32 bits wide.
194 * 0x3 Memory interface databus is 64 bits wide.
195 * 0x4 Memory interface databus is 128 bits wide.
196 * 0x5 Memory interface databus is 256 bits wide.
197 */
198 switch (BMVAL(devid, 8, 10)) {
199 case 0x2:
200 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
201 break;
202 case 0x3:
203 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
204 break;
205 case 0x4:
206 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
207 break;
208 case 0x5:
209 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
210 break;
211 default:
212 memwidth = 0;
213 }
214
215 return memwidth;
216 }
217
218 #define coresight_tmc_reg(name, offset) \
219 coresight_simple_reg32(struct tmc_drvdata, name, offset)
220 #define coresight_tmc_reg64(name, lo_off, hi_off) \
221 coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
222
223 coresight_tmc_reg(rsz, TMC_RSZ);
224 coresight_tmc_reg(sts, TMC_STS);
225 coresight_tmc_reg(trg, TMC_TRG);
226 coresight_tmc_reg(ctl, TMC_CTL);
227 coresight_tmc_reg(ffsr, TMC_FFSR);
228 coresight_tmc_reg(ffcr, TMC_FFCR);
229 coresight_tmc_reg(mode, TMC_MODE);
230 coresight_tmc_reg(pscr, TMC_PSCR);
231 coresight_tmc_reg(axictl, TMC_AXICTL);
232 coresight_tmc_reg(devid, CORESIGHT_DEVID);
233 coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
234 coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
235 coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
236
237 static struct attribute *coresight_tmc_mgmt_attrs[] = {
238 &dev_attr_rsz.attr,
239 &dev_attr_sts.attr,
240 &dev_attr_rrp.attr,
241 &dev_attr_rwp.attr,
242 &dev_attr_trg.attr,
243 &dev_attr_ctl.attr,
244 &dev_attr_ffsr.attr,
245 &dev_attr_ffcr.attr,
246 &dev_attr_mode.attr,
247 &dev_attr_pscr.attr,
248 &dev_attr_devid.attr,
249 &dev_attr_dba.attr,
250 &dev_attr_axictl.attr,
251 NULL,
252 };
253
trigger_cntr_show(struct device * dev,struct device_attribute * attr,char * buf)254 static ssize_t trigger_cntr_show(struct device *dev,
255 struct device_attribute *attr, char *buf)
256 {
257 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
258 unsigned long val = drvdata->trigger_cntr;
259
260 return sprintf(buf, "%#lx\n", val);
261 }
262
trigger_cntr_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)263 static ssize_t trigger_cntr_store(struct device *dev,
264 struct device_attribute *attr,
265 const char *buf, size_t size)
266 {
267 int ret;
268 unsigned long val;
269 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
270
271 ret = kstrtoul(buf, 16, &val);
272 if (ret)
273 return ret;
274
275 drvdata->trigger_cntr = val;
276 return size;
277 }
278 static DEVICE_ATTR_RW(trigger_cntr);
279
buffer_size_show(struct device * dev,struct device_attribute * attr,char * buf)280 static ssize_t buffer_size_show(struct device *dev,
281 struct device_attribute *attr, char *buf)
282 {
283 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
284
285 return sprintf(buf, "%#x\n", drvdata->size);
286 }
287
buffer_size_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)288 static ssize_t buffer_size_store(struct device *dev,
289 struct device_attribute *attr,
290 const char *buf, size_t size)
291 {
292 int ret;
293 unsigned long val;
294 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
295
296 /* Only permitted for TMC-ETRs */
297 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
298 return -EPERM;
299
300 ret = kstrtoul(buf, 0, &val);
301 if (ret)
302 return ret;
303 /* The buffer size should be page aligned */
304 if (val & (PAGE_SIZE - 1))
305 return -EINVAL;
306 drvdata->size = val;
307 return size;
308 }
309
310 static DEVICE_ATTR_RW(buffer_size);
311
312 static struct attribute *coresight_tmc_attrs[] = {
313 &dev_attr_trigger_cntr.attr,
314 &dev_attr_buffer_size.attr,
315 NULL,
316 };
317
318 static const struct attribute_group coresight_tmc_group = {
319 .attrs = coresight_tmc_attrs,
320 };
321
322 static const struct attribute_group coresight_tmc_mgmt_group = {
323 .attrs = coresight_tmc_mgmt_attrs,
324 .name = "mgmt",
325 };
326
327 const struct attribute_group *coresight_tmc_groups[] = {
328 &coresight_tmc_group,
329 &coresight_tmc_mgmt_group,
330 NULL,
331 };
332
tmc_etr_can_use_sg(struct tmc_drvdata * drvdata)333 static inline bool tmc_etr_can_use_sg(struct tmc_drvdata *drvdata)
334 {
335 return fwnode_property_present(drvdata->dev->fwnode,
336 "arm,scatter-gather");
337 }
338
339 /* Detect and initialise the capabilities of a TMC ETR */
tmc_etr_setup_caps(struct tmc_drvdata * drvdata,u32 devid,void * dev_caps)340 static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
341 u32 devid, void *dev_caps)
342 {
343 u32 dma_mask = 0;
344
345 /* Set the unadvertised capabilities */
346 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
347
348 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(drvdata))
349 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
350
351 /* Check if the AXI address width is available */
352 if (devid & TMC_DEVID_AXIAW_VALID)
353 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
354 TMC_DEVID_AXIAW_MASK);
355
356 /*
357 * Unless specified in the device configuration, ETR uses a 40-bit
358 * AXI master in place of the embedded SRAM of ETB/ETF.
359 */
360 switch (dma_mask) {
361 case 32:
362 case 40:
363 case 44:
364 case 48:
365 case 52:
366 dev_info(drvdata->dev, "Detected dma mask %dbits\n", dma_mask);
367 break;
368 default:
369 dma_mask = 40;
370 }
371
372 return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(dma_mask));
373 }
374
tmc_probe(struct amba_device * adev,const struct amba_id * id)375 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
376 {
377 int ret = 0;
378 u32 devid;
379 void __iomem *base;
380 struct device *dev = &adev->dev;
381 struct coresight_platform_data *pdata = NULL;
382 struct tmc_drvdata *drvdata;
383 struct resource *res = &adev->res;
384 struct coresight_desc desc = { 0 };
385 struct device_node *np = adev->dev.of_node;
386
387 if (np) {
388 pdata = of_get_coresight_platform_data(dev, np);
389 if (IS_ERR(pdata)) {
390 ret = PTR_ERR(pdata);
391 goto out;
392 }
393 adev->dev.platform_data = pdata;
394 }
395
396 ret = -ENOMEM;
397 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
398 if (!drvdata)
399 goto out;
400
401 drvdata->dev = &adev->dev;
402 dev_set_drvdata(dev, drvdata);
403
404 /* Validity for the resource is already checked by the AMBA core */
405 base = devm_ioremap_resource(dev, res);
406 if (IS_ERR(base)) {
407 ret = PTR_ERR(base);
408 goto out;
409 }
410
411 drvdata->base = base;
412
413 spin_lock_init(&drvdata->spinlock);
414
415 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
416 drvdata->config_type = BMVAL(devid, 6, 7);
417 drvdata->memwidth = tmc_get_memwidth(devid);
418
419 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
420 if (np)
421 ret = of_property_read_u32(np,
422 "arm,buffer-size",
423 &drvdata->size);
424 if (ret)
425 drvdata->size = SZ_1M;
426 } else {
427 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
428 }
429
430 pm_runtime_put(&adev->dev);
431
432 desc.pdata = pdata;
433 desc.dev = dev;
434 desc.groups = coresight_tmc_groups;
435
436 switch (drvdata->config_type) {
437 case TMC_CONFIG_TYPE_ETB:
438 desc.type = CORESIGHT_DEV_TYPE_SINK;
439 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
440 desc.ops = &tmc_etb_cs_ops;
441 break;
442 case TMC_CONFIG_TYPE_ETR:
443 desc.type = CORESIGHT_DEV_TYPE_SINK;
444 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
445 desc.ops = &tmc_etr_cs_ops;
446 ret = tmc_etr_setup_caps(drvdata, devid, id->data);
447 if (ret)
448 goto out;
449 break;
450 case TMC_CONFIG_TYPE_ETF:
451 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
452 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
453 desc.ops = &tmc_etf_cs_ops;
454 break;
455 default:
456 pr_err("%s: Unsupported TMC config\n", pdata->name);
457 ret = -EINVAL;
458 goto out;
459 }
460
461 drvdata->csdev = coresight_register(&desc);
462 if (IS_ERR(drvdata->csdev)) {
463 ret = PTR_ERR(drvdata->csdev);
464 goto out;
465 }
466
467 drvdata->miscdev.name = pdata->name;
468 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
469 drvdata->miscdev.fops = &tmc_fops;
470 ret = misc_register(&drvdata->miscdev);
471 if (ret)
472 coresight_unregister(drvdata->csdev);
473 out:
474 return ret;
475 }
476
477 static const struct amba_id tmc_ids[] = {
478 {
479 .id = 0x000bb961,
480 .mask = 0x000fffff,
481 },
482 {
483 /* Coresight SoC 600 TMC-ETR/ETS */
484 .id = 0x000bb9e8,
485 .mask = 0x000fffff,
486 .data = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
487 },
488 {
489 /* Coresight SoC 600 TMC-ETB */
490 .id = 0x000bb9e9,
491 .mask = 0x000fffff,
492 },
493 {
494 /* Coresight SoC 600 TMC-ETF */
495 .id = 0x000bb9ea,
496 .mask = 0x000fffff,
497 },
498 { 0, 0},
499 };
500
501 static struct amba_driver tmc_driver = {
502 .drv = {
503 .name = "coresight-tmc",
504 .owner = THIS_MODULE,
505 .suppress_bind_attrs = true,
506 },
507 .probe = tmc_probe,
508 .id_table = tmc_ids,
509 };
510 builtin_amba_driver(tmc_driver);
511
